METHOD FOR FABRICATING 1T-DRAM ON BULK SILICON

Abstract

An integrated circuit includes a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon. The integrated circuit also includes a single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with the bulk IC.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will become more fully understood from the detailed description and the accompanying drawings, wherein:

FIG. 1A is a cross-section of a bulk silicon CMOS IC;

FIG. 1B is a partial cross-section of a 1T DRAM fabricated on a bulk silicon CMOS in accordance with the present disclosure;

FIG. 1C is a partial cross-section of a 1T DRAM fabricated on a bulk silicon CMOS in accordance with the present disclosure;

FIG. 1D is a partial cross-section of a 1T DRAM fabricated on a bulk silicon CMOS in accordance with the present disclosure;

FIG. 1E is a partial cross-section of a 1T DRAM fabricated on a bulk silicon CMOS in accordance with the present disclosure;

FIG. 2 illustrates a method for fabricating a 1T DRAM on bulk silicon technology in accordance with the present disclosure;

FIG. 3A is a functional block diagram of a laptop computer system;

FIG. 3B is a functional block diagram of a hard disk drive (HDD):

FIG. 3C is a functional block diagram of a digital versatile disk (DVD);

FIG. 3D is a functional block diagram of a high definition television;

FIG. 3E is a functional block diagram of a vehicle control system;

3F is a functional block diagram of a cellular phone;

FIG. 3G is a functional block diagram of a set top box; and

FIG. 3H is a functional block diagram of a media player.

Claims

1. An integrated circuit comprising: a bulk technology integrated circuit (bulk IC) including a bulk silicon layer and complementary MOSFET (CMOS) transistors fabricated thereon; anda first single transistor dynamic random access memory (1T DRAM) cell arranged adjacent to and integrated with said bulk IC.

2. The integrated circuit of claim 1 wherein said first 1T DRAM cell includes: an amorphous silicon layer; andfirst and second gates including first and second gate oxide layers arranged adjacent to said amorphous silicon layer and first and second gate polysilicon layers arranged in said first and second gate oxide layers.

3. The integrated circuit of claim 2 wherein said first 1T DRAM cell includes a first inter-layer dielectric (ILD) arranged adjacent to said amorphous silicon layer and said first and second gates.

4. The integrated circuit of claim 3 wherein said bulk silicon layer of said bulk IC includes an N well including first and second doped regions and a P well including third and fourth doped regions, and wherein said bulk IC further comprises third and fourth gates including third and fourth gate oxide layers arranged adjacent to said bulk silicon layer and third and fourth gate polysilicon layers arranged in said third and fourth gate oxide layers.

5. The integrated circuit of claim 4 further comprising a second ILD arranged adjacent to said bulk silicon layer and said third and fourth gates.

6. The integrated circuit of claim 5 further comprising first and second contacts that are arranged in said second ILD and that communicate with said first and fourth doped regions of said bulk silicon layer.

7. The integrated circuit of claim 6 further comprising third and fourth contacts arranged in said first ILD, wherein said first and second contacts communicate with said third and fourth contacts.

8. The integrated circuit of claim 7 further comprising a metal bit line that communicates with said third and fourth contacts.

9. The integrated circuit of claim 2 wherein said amorphous silicon layer includes first, second and third doped regions, wherein said first gate is arranged adjacent to parts of said first and second doped regions and said second gate is arranged adjacent to parts of said second and third doped regions.

10. The integrated circuit of claim 9 further comprising a fifth contact that is arranged in said first ILD and that communicates with said second doped region of said amorphous silicon layer.

11. The integrated circuit of claim 1 further comprising a bit line that communicates with said CMOS transistors and said first 1T DRAM cell.

12. The integrated circuit of claim 11 wherein said first 1T DRAM cell comprises a first transistor that includes a gate region.

13. The integrated circuit of claim 1 wherein said first 1T DRAM cell comprises a first transistor comprising a body region and a source region.

14. The integrated circuit of claim 13 wherein said body region stores data.

15. The integrated circuit of claim 14 wherein said body region comprises an amorphous silicon layer.

16. The integrated circuit of claim 13 further comprising a second 1T DRAM cell including a second transistor that shares said source region with said transistor of said first 1T DRAM cell.

17. The integrated circuit of claim 16 wherein said first 1T DRAM cell and said second 1T DRAM cell store two bits of data.

18. The integrated circuit of claim 1 wherein said first 1T DRAM comprises: a source region;a body region; anda drain region,wherein said source region, said body region, and said drain region are formed in a doped amorphous silicon layer arranged adjacent to said bulk IC.

19. The integrated circuit of claim 18 wherein said source region of said first 1T DRAM cell comprises crystallized silicon that is seeded with nickel.

20. The integrated circuit of claim 18 wherein said source region of said first 1T DRAM cell comprises a seeded crystallized silicon island.

21. The integrated circuit of claim 20 wherein said crystallized silicon island and said bulk IC have a common orientation.

22. A method for fabricating an integrated circuit comprising: fabricating complementary MOSFET (CMOS) transistors on a bulk technology integrated circuit (bulk IC) including a bulk silicon layer; andarranging a first single transistor dynamic random access memory (1T DRAM) cell adjacent to and integrated with said bulk IC.

23. The method of claim 22 further comprising: arranging first and second gates including first and second gate oxide layers adjacent to an amorphous silicon layer of said first 1T DRAM cell; andarranging first and second gate polysilicon layers in said first and second gate oxide layers.

24. The method of claim 23 further comprising arranging a first inter-layer dielectric (ILD) of said first 1T DRAM cell adjacent to said amorphous silicon layer and said first and second gates.

25. The method of claim 24 further comprising: arranging third and fourth gates of said bulk IC including third and fourth gate oxide layers adjacent to said bulk silicon layer; andarranging third and fourth gate polysilicon layers in said third and fourth gate oxide layers,wherein said bulk silicon layer of said bulk IC includes an N well including first and second doped regions and a P well including third and fourth doped regions.

26. The method of claim 25 further comprising arranging a second ILD adjacent to said bulk silicon layer and said third and fourth gates.

27. The method of claim 26 further comprising arranging first and second contacts in said second ILD, wherein said first and second contacts communicate with said first and fourth doped regions of said bulk silicon layer.

28. The method of claim 27 further comprising arranging third and fourth contacts in said first ILD, wherein said first and second contacts communicate with said third and fourth contacts.

29. The method of claim 28 further comprising arranging a metal bit line to communicate with said third and fourth contacts.

30. The method of claim 23 further comprising: arranging said first gate adjacent to parts of first and second doped regions of said amorphous silicon layer; andarranging said second gate adjacent to parts of second and third doped regions of said amorphous silicon layer.

31. The method of claim 30 further comprising arranging a fifth contact in said first ILD to communicate with said second doped region of said amorphous silicon layer.

32. The method of claim 22 further comprising arranging a bit line to communicate with said CMOS transistors and said first 1T DRAM cell.

33. The method of claim 32 wherein said first 1T DRAM cell comprises a first transistor that includes a gate region.

34. The method of claim 22 wherein said first 1T DRAM cell comprises a first transistor comprising a body region and a source region.

35. The method of claim 34 further comprising storing data in said body region.

36. The method of claim 35 wherein said body region comprises an amorphous silicon layer.

37. The method of claim 34 further comprising sharing said source region of said transistor of said first 1T DRAM cell with a second transistor for a second 1T DRAM cell.

38. The method of claim 37 further comprising storing two bits of data in said first 1T DRAM cell and said second 1T DRAM cell.

39. The method of claim 22 further comprising forming a source region, a body region, and a drain region of said first 1T DRAM in a doped amorphous silicon layer.

40. The method of claim 39 further comprising seeding crystallized silicon of said source region of said first 1T DRAM cell with nickel.

41. The method of claim 39 further comprising: seeding said source region of said first 1T DRAM cell; andcrystallizing a silicon island in said source region of said first 1T DRAM cell.

42. The method of claim 41 further comprising arranging said crystallized silicon island and said bulk IC in a common orientation.