The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. More specifically, the present invention relates to so-called MIS (Metal Insulator Semiconductor) structures or MIM (Metal Insulator Metal) structures.
A method of fabricating a capacitor in a semiconductor substrate is described in U.S. Pat. No. 6,693,016, which is incorporated herein by reference. The capacitor according to this patent comprises a dielectric layer with a relatively high dielectric constant and metallic electrode layers to avoid space charge regions.
Prior art methods of fabricating capacitors in a substrate induce a significant mechanical stress inside the substrate's surface. Due to this mechanical stress, the substrate may bow. Substrates such as wafers of large diameters are difficult to handle and to further process if they are bent or non-planar.
According to embodiments of the present invention, a trench having a lower region and an upper region is formed in the substrate. The trench's diameter is larger in the lower region and smaller in the upper region. A first electrode of the capacitor is formed inside the trench. If the first electrode is created by the substrate itself, the first electrode is automatically formed during the etch process of the trench. Alternatively, the first electrode may be realized by depositing an additional electrode layer (e.g., a metallic layer) onto the trench's sidewalls. Afterwards, a dielectric layer and a conductive layer are deposited. The deposited conductive layer forms a second electrode of the capacitor. The upper region of the trench is closed by a plug, thereby forming a closed cavity inside the lower region. Then, a contact layer is deposited that contacts the second electrode.
According to embodiments of the invention, a cavity is formed in the lower region of the capacitor. The cavity remains empty, so no material is filled therein. As the cavity does not contain material, it will not induce any stress inside the substrate's surface. The plug on top of the cavity allows to smooth the resulting surface and to create a planar surface for further processing. In contrast thereto, prior art capacitors are filled completely with material in order to create a planar surface. These fillings, however, induce stress inside the surface as described above.
In summary, embodiments of the invention significantly avoid stress inside the substrate by leaving the trench at least partly empty. The trench is closed on top in order to allow for further processing of the substrate. For example, dynamic random access memory (DRAM) or similar devices may be fabricated during further process steps as known in the art.
Preferably, the cross-section of the trench is formed like a bottle such that the upper region of the trench forms a bottleneck.
According to a first preferred embodiment of the invention, the contact layer is deposited on the second electrode above the plug. The plug may consist of insulating material.
The trench may be closed such that an upper part of the second electrode above the plug remains uncovered. In this case, the contact layer may be deposited directly on the upper part of the second electrode.
The closing of the upper region may include depositing an insulating layer at least in the upper region, and thereafter removing the insulating layer in the upper part of the second electrode.
According to a second preferred embodiment of the invention, the contact layer is deposited on the second electrode below the plug.
The upper region may be closed by firstly forming an outer plug ring consisting of insulating material. Then the contact layer is deposited through the plug ring opening onto the second electrode.
Preferably, the outer plug ring is formed by depositing a non-conformal layer of insulating material such that the upper region will narrow.
In order to facilitate the deposition of the contact layer on the second electrode below the plug, the non-conformal layer of insulating material is deposited such that the lower region of the trench remains at least partly uncovered.
Another aspect of the invention is directed to a capacitor formed inside a substrate.
With regard to such a capacitor, one aspect of the invention is to provide a capacitor with reduced mechanical stress inside the surface of the substrate.
According to embodiments of the invention, the capacitor comprises a trench formed inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameter in the lower region is larger than in the upper region. A plug closes the lower region forming a closed cavity.
In order that the manner in which the above-recited and other advantages of the invention are obtained will be readily understood, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof, which are illustrated in the appended drawings. Understanding that these drawings depict only typical embodiments of the invention and are not, therefore, to be considered to be limiting of its scope, the invention will be described and explained with additional specificity and detail through the use of the accompanying drawings in which:
The preferred embodiments of the present invention will be best understood by reference to the drawings, wherein like parts are designated by like numerals throughout.
The following list of reference symbols can be used in conjunction with the figures:
It will be readily understood that the process steps of the present invention, as generally described and illustrated in the figures herein, could vary in a wide range of different process steps. Thus, the following more detailed description of the embodiments of the present invention, as represented in
Embodiments of the present invention provide a method for fabricating a capacitor in a semiconductor substrate. Referring to
The bottle-like trench 20 as shown in
Subsequently, the bottom 80 is further etched down using an isotropic etch gas. The isotropic etch gas broadens the trench below the etch mask 70 such that the lower region 30 with a larger diameter D2 results (see
The trench 20 according to
Subsequently, a conformal dielectric layer 110 (e.g., an oxide layer), a second conformal conductive layer 120 and a conformal oxide layer 130 are deposited on the substrate 10. The resulting structure is shown in
Then, the second conductive layer 120 is etched down to a predetermined depth L as shown in
Subsequently, an oxide etch step is carried out. During this etch step, the conformal oxide layer 110 is removed partly and the conformal oxide layer 130 is removed completely. The conformal oxide layer 110 just remains below the conformal conductive layer 120. The resulting structure is depicted in
Starting from the structure as shown in
Then, the non-conformal oxide layer 200 is etched using an anisotropic etch gas such that layer 200 is removed from an upper part 240 of the second electrode layer 120. The resulting structure is shown in
Afterwards, a contact layer 250 is deposited on the upper part 240 of the second electrode layer 120 (
According to the first embodiment of the invention, the upper region 40 of the trench 20 is closed completely by the non-conductive plug 220. Therefore, the contact layer 250 is deposited above the plug 220 on the second electrode layer 120.
Then, a conformal contact layer 420 is deposited through the plug ring opening 430 onto the second electrode layer 120 inside the lower region 30 of the trench 20. As the lower region 30 is at least partly uncovered from layer 400, the conformal contact layer 420 will create an electrical contact to the second electrode layer 120 below the plug ring 410.
Due to the small diameter D3 of the plug ring opening 430, the conformal contact layer 420 closes the plug ring opening 430 and forms—together with the plug ring 410—a plug 450 that separates the lower region 30 from the upper region 40 of the trench 20. Accordingly, a cavity 230 is formed inside the lower region 30 of the trench 20 (
The conformal contact layer 420 may be filled with conductive polysilicon material 500 as shown in
Number | Name | Date | Kind |
---|---|---|---|
6200851 | Arnold | Mar 2001 | B1 |
6693016 | Gutsche et al. | Feb 2004 | B2 |
6838334 | Gluschenkov et al. | Jan 2005 | B1 |
20050212027 | Adam et al. | Sep 2005 | A1 |
Number | Date | Country | |
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20070007624 A1 | Jan 2007 | US |