Patent Application
20130168754
Example embodiments generally relate to memory device fabrication, and more particularly, relate to memory device fabrication including oxide densification of an interpoly dielectric layer for increased reliability.
Nonvolatile memory devices, such as EPROM, EEPROM and flash EPROM (e.g., NAND/NOR type flash memory) devices, are well known in the art. In general, nonvolatile memory devices comprise a series of transistors which act as memory cells. Each transistor includes source and drain regions formed on the surface of a n- or p-type semiconductor substrate, an insulating layer formed on the surface of the semiconductor substrate positioned between the source and drain regions, a floating gate positioned on the insulating layer for holding a charge, a layer of an insulating dielectric formed on the floating gate for insulating the floating gate, thereby enabling the floating gate to retain its charge and a control gate positioned on the insulating dielectric layer. In the case where both the floating gate and the control gate are made of polysilicon, the insulating dielectric between the respective layers is sometimes called an interpoly dielectric. The interpoly dielectric need not be strictly an oxide (e.g., silicon oxide); often it is made of an oxide-nitride-oxide (ONO) composite.
A bit of binary data is stored in the floating gate of each memory cell as either a high or low level charge, a high level charge corresponding to a first data value (e.g., 1), a low level charge corresponding to a second data value (e.g., 0). Since the value of the data stored in the floating gate is a function of the size of the charge stored in the floating gate, charge loss or gain by the floating gate can alter the value of the data stored in the memory cell. It is therefore essential to the functioning of a nonvolatile memory device that each floating gate be capable of long term charge retention.
The ability of a floating gate to retain a charge is primarily determined by the interpoly dielectric used to insulate the floating gate. In order to prevent charge loss, the dielectric must have a high break down voltage. For example, when a high potential is applied to the control gate during programming, the dielectric must have a sufficiently high breakdown voltage to block electrons from the floating gate to the control gate.
Once a charge is introduced into the floating gate, the dielectric must also be able to prevent charge leakage from the floating gate. Charge leakage generally occurs through defects in the dielectric layer. It is therefore very important for the interpoly dielectric to have a high degree of structural integrity which is generally associated with a low concentration of pinholes.
Charges are transferred to a floating gate by a variety of methods, such as avalanche injection, channel injection and Fowler-Nordheim tunneling. It is generally desirable for a memory device to have a high gate coupling ratio (GCR) between the floating gate and the control gate. The gate coupling ratio is a function of the capacitance between the floating gate and the control gate and hence is related to the thickness of the dielectric layer. In order to maximize the gate coupling ratio, as well as to minimize the amount of heat generated by the device, it is desirable to minimize the thickness of the interpoly dielectric layer. However, as the thickness of the dielectric is reduced such as in the case of a thinned-down interpoly dielectric, charge leakage through defects in the dielectric generally increases.
In light of the foregoing background, exemplary embodiments of the present disclosure provide a method of fabricating a memory device including oxide densification of an insulating dielectric layer (e.g., interpoly dielectric layer) between a floating gate and a control gate for increased reliability. The method of exemplary embodiments may improve quality of the dielectric layer without increasing its physical and electrical thickness. In one example, the oxide densification may be accomplished by plasma oxidation, which may be performed at a relatively low temperature, thereby meeting lower thermal budget requirements as the device is scaled down. It may allow the continued dielectric scaling to meet a gate coupling ratio requirement without sacrificing device reliability.
According to one example aspect of the present disclosure, a method of forming a semiconductor device is provided. The method of this example aspect includes providing a semiconductor substrate, and forming a first conductive layer over the substrate. The method also includes forming an interpoly dielectric layer over the first conductive layer. In this regard, forming the interpoly dielectric layer includes forming an oxide-densified silicon oxide layer and forming a second conductive layer over the interpoly dielectric layer.
In one example, forming the oxide-densified silicon oxide layer may include forming a silicon oxide layer and subjecting the silicon oxide layer to oxide densification to form an oxide-densified silicon oxide layer.
In one example, the silicon oxide layer is formed by low-pressure chemical vapor deposition or atomic layer deposition, or formed of a radical oxide.
In one example, subjecting the silicon oxide layer to oxide densification comprises subjecting the silicon oxide layer to plasma oxidation, such as by using a radio frequency or microwave source. In one example, the silicon oxide layer is subjected to plasma oxidation at a temperature at or below 700° Celsius. The oxide-densified silicon oxide layer in one example has a thickness between approximately 15 Å and 50 Å.
In one example, an insulating layer may be formed over the semiconductor substrate, with the first conductive layer being formed over the insulating layer.
In one example, the silicon oxide layer is a first silicon oxide layer, and the oxide-densified silicon oxide layer is a first oxide-densified silicon oxide layer. In this example, forming the interpoly dielectric layer may further include forming a second silicon oxide layer over the first oxide-densified silicon oxide layer, and subjecting the second silicon oxide layer to oxide densification to form a second oxide-densified silicon oxide layer. Even further, forming the interpoly dielectric layer may include forming a silicon nitride layer over the first oxide-densified silicon oxide layer, with the second silicon oxide layer being formed over the silicon nitride layer. In various examples, the first oxide-densified silicon oxide layer may have a thickness between approximately 15 Å and 50 Å, and the second oxide-densified silicon oxide layer may have a thickness between approximately 30 Å and 80 Å.
These and other processes, features, and characteristics of these and other embodiments, including method and semiconductor device embodiments, of the present invention, as well as additional details thereof, are further described herein.
Having thus described the disclosure in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:
a-1g, which are schematic diagrams in cross-sectional view illustrating a method of fabricating a semiconductor device according to one example embodiment of the present disclosure;
Exemplary embodiments now will be described more fully hereinafter with reference to the accompanying drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
Reference is made to
As shown in
An insulating layer 16 such as a tunnel oxide layer is formed or deposited over the substrate 10. A first conductive layer is formed over the tunnel oxide, and may function as a floating gate 18. In this embodiment, the first conductive layer is a polysilicon layer. A layer of an insulating dielectric may be formed on the floating gate for insulating the floating gate. The insulating dielectric may be referred to as an interpoly dielectric (IPD) and may be formed of or otherwise include a silicon oxide. In one example embodiment, the interpoly dielectric may be made of an oxide-nitride-oxide (ONO) composite. In this example, the interpoly dielectric may include a first silicon oxide layer 20 formed over the floating gate, as shown in
The first silicon oxide layer 20 may be formed in any of a number of different manners. For example, the first silicon oxide layer may be formed by low-pressure chemical vapor deposition (LPCVD) such as in the context of oxide deposited using tetra ethyl ortho silicate (TEOS), high-temperature deposited oxide (HTO) or the like. In other examples, the first silicon oxide layer may be formed by in-situ steam generation (ISSG), atomic layer deposition (ALD) or the like. And in one example, the first silicon oxide layer may be formed of a radical oxide.
As shown in
Also as part of the interpoly dielectric, a silicon nitride layer 22 may be formed over the first oxide-densified silicon oxide layer 20′, as shown in
As shown in
As demonstrated, oxide densification (e.g., plasma oxidation) of one or more layers of the interpoly dielectric of a semiconductor device (e.g, memory device) may improve reliability of the device, such as its retention and endurance, without increasing the interpoly dielectrics physical and electrical thickness. The oxide densification may also allow continued interpoly dielectric scaling to meet a gate coupling ratio requirement without sacrificing the device's reliability.
Many modifications and other embodiments of the invention will come to mind to one skilled in the art to which this invention pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. For example, although described as a multilayer interpoly dielectric, the interpoly dielectric may instead include a single silicon oxide layer, which may be subject to oxide densification as explained above. Also for example, although both the first and second silicon oxide layers may be subject to oxide densification as explained above, in other instances, only one or the other but not both of the silicon oxide layers may be subject to oxide densification. Even further, for example, oxide densification may be applied to other one or more oxide layers of other structures improve their quality. This may include, for example, the linear oxide layer of a shallow trench isolation structure. This method can also be applied at the spacer oxide (SPR DEP OX), and shallow trench isolation (STI) liner oxide quality improves. The spacer oxide application is for word-line spacer fill-in to avid the word-line-word-line bridge. So plasma oxide treatment is applied on the spacer oxide to improve the oxide quality and reduce the word-line-word-line bridge rate. It should therefore be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
