BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross-sectional view of an integrated circuit capacitor fabricated in accordance with the prior art.
FIG. 2 is a cross-sectional view of an integrated circuit capacitor fabricated in a copper damascene process in accordance with the prior art.
FIGS. 3A-3P are cross-sectional views of various stages of processing steps of a capacitor having both plates fabricated from copper in accordance with various exemplary embodiments of the present invention.
DETAILED DESCRIPTION
With reference to FIG. 3A, a base substrate 301 may be a silicon wafer. Alternatively, another elemental Group IV semiconductor or compound semiconductor (e.g., Groups III-V or II-VI) in either wafer or non-wafer forms may be selected for the base substrate 301. Further, the base substrate 301 may be fabricated from silicon-on-insulator or a variety of other base materials known to those of skill in the art.
The base substrate 301 may have fabricated thereon a plurality of active integrated circuit devices (not shown). Methods of fabrication of the plurality of active integrated circuit devices are known in the art. The base substrate 301 includes trenches which have a copper-barrier layer 303. The copper-barrier layer 303 substantially lines the trench prevents migration of copper molecules into surrounding areas of the base substrate 301. The copper-barrier layer 303 is formed from a material having a high electrical conductivity while maintaining a low copper diffusivity to chemically isolate any subsequently formed copper conductors from the base substrate 301. The copper-barrier layer 303 is frequently a single or bi-layer deposition from materials including cobalt-based alloys, ruthenium-based alloys, silicon nitride, silicon-copper-nitride, tantalum, and tantalum nitride. In a specific exemplary embodiment, the copper-barrier layer 303 is 300 Å of tantalum followed by a 400 Å to 600 Å copper seed layer. The copper seed layer is commonly used although ruthenium-based seedless layers are beginning to emerge in the art. If employed, the seed-layer provides a low-resistance conductor for plating current that drives a subsequent electroplating process and also facilitates film nucleation. The copper-barrier layer 303 further provides for adhesion of subsequently formed first 305A and second 305B copper fill areas.
In this exemplary embodiment, the first copper fill area 305A is not necessarily a part of the present invention. The first copper fill area 305A may simply be a copper conducting line proximate to the capacitor of the present invention or, alternatively, may be a copper conducting line which serves to electrically connect the second copper fill area 305B to other portions of the integrated circuit (not shown). Regardless, the second copper fill area 305B forms at least a portion of a bottom plate of the MIM capacitor. Further, the copper-barrier layer 303 and the second copper fill area 305B do not need to be formed in a trench. Consequently, in an alternative embodiment, the barrier layer 303 and the second copper fill area 305B may be formed in a planar fashion over an uppermost surface of the substrate 301.
As is known in the art, copper has superior properties over Al, Xi, Ta, and various other metallic materials in terms of both an inherently lower electrical resistivity and a pronounced resistance to electromigration. However, there are few volatile copper compounds. Consequently, copper can ordinarily not be patterned by typical subtractive patterning techniques such as photoresist masking and plasma etching typically used with other metallic materials. Copper processing thus typically uses an additive patterning process referred to as copper damascene processing.
In a copper damascene process, either an underlying dielectric layer and/or base substrate is patterned and etched (using standard photolithographic processes) with open trenches or openings v/here a conductor will be formed. A thick coating of copper is added such that the copper significantly overfills the trenches or openings. A chemical mechanical planarization (CMP) process removes the copper to a level coplanar with surrounding local features. Frequently, the surrounding local features are chosen to be a dielectric material, such as silicon dioxide (SiO2), which serves as a hard etch-stop material to determine an end-point to the CMP process step. Copper contained within the trenches or openings is not removed and becomes the patterned conductor. Any surrounding dielectric material may be etched or left in place depending upon subsequent processes.
In FIG. 3B, a first dielectric layer 307A is formed over uppermost portions of the base substrate 301 and the first 305A and second 305B copper fill areas. In a specific exemplary embodiment, the dielectric layer 307A is a deposited silicon nitride (Si3N4) layer, 500 Å to 1000 Å in thickness. Other types of dielectric materials may also be used such as, for example, a chemical vapor deposition (CVD) deposited silicon dioxide layer.
A bottom anti-reflective coating (BARC) layer 309 may be formed over the dielectric layer 307A (FIG. 3C), followed by a coated layer of photoresist. The photoresist is photolithographically exposed, developed, and etched, forming a patterned photoresist layer 311. Portions of the BARC layer 309 and the dielectric layer 309A are anisotropic ally etched, stopping on the second copper fill area 305B. The patterned photoresist layer 311 and any remaining portions of the BARC layer 309 are removed, leaving a patterned dielectric layer 307B (FIG. 3D). A wet clean may be performed to remove any oxide formation from exposed portions of the second copper fill area 305B.
With reference to FIG. 3E, a second copper-barrier layer 313A is formed. In a specific exemplary embodiment, the second copper-barrier layer is a deposited Ta layer, 200 Å to 500 Å thick. Exposed surfaces of tantalum quickly oxidize. An optional oxygen plasma treatment may be used to enhance the effective dielectric constant.
In FIG. 3F, an MIM dielectric layer 315A is formed. The MIM dielectric layer may be comprised of, for example, Si3N4 or one or more other high-k dielectric materials. High-k dielectric materials are known in the art and include films such as tantalum pentoxide (Ta2O5), zirconium oxide (ZrO2), hafnium oxide (HfO2), and lead-zirconate-titanate (PZT). However, other dielectric materials may readily be employed as well to form the MIM dielectric layer 315A. In a specific exemplary embodiment, the MIM dielectric layer 315A can range from 20 Å to 1000 Å in thickness.
In FIG. 3G, a third copper-barrier layer 317A is formed followed by a combined copper-seed/copper layer 319A and a dielectric cap layer 321A. In a specific exemplary embodiment, the third copper-barrier layer 317A is a Ta layer, 100 Å to 300 Å in thickness, the combined copper-seed/copper layer 319A is 600 Å to 2500 Å thick, and the dielectric cap layer 321A is Si3N4 300 Å to 1000 Å in thickness. Alternatively, the combined copper-seed/copper layer 319A may be comprised of, for example, a sputtered or electroplated copper layer only without a copper-seed layer. In either form of the copper layer 319A, the fabrication process is non-damascene in nature. For example, a CMP step is not required after formation of the copper layer 319A. Consequently, the copper layer 319A will not have any types of fine striations on either face as may be found in a damascene process (although such striations would have little or no effect on the present invention).
With reference to FIG. 3H, a sequence of lithography to form a MIM top plate commences. A second BARC layer 323A is formed over the dielectric cap layer 321A. A photoresist layer is formed over the second BARC layer 323A. The photoresist layer is exposed, developed, and etched, forming a MIM top plate patterned photoresist layer 325. The patterned photoresist layer 325 serves as an etch mask and protects underlying materials while portions of both the second BARC layer 323A and the dielectric cap layer 321A are each etched (FIG. 3I) forming an etched second BARC layer 323B and etched dielectric cap layer 321B, respectively.
An isotropic copper wet etch chemistry is employed to etch the combined copper-seed/copper layer 319A, thus slightly undercutting the etched dielectric cap layer 323B and forming a copper MIM top plate 319B (FIG. 3J). Although not required to practice or produce the MIM capacitor of the present invention, shortly after the etched copper is approximately equal to the thickness of the copper seed layer, the dielectric cap layer 3213 collapses, forming a collapsed dielectric layer 321C. The collapsed dielectric layer 321C protects the underlying MIM top plate 319B from subsequent etching. In a specific exemplary embodiment, the isotropic copper wet etch chemistry is selected to have an etch rate of less than 5000 Å per minute with a higher selectivity to BARC, photoresist, and copper.
Alternatively, an anisotropic dry etch such as, for example, a reactive-ion etch (RIE), may be used instead of the isotropic wet etch. Various combinations of chemicals may be incorporated to increase selectivity of the RIE such that, for example, silicon nitride is more readily etched than any adjacent non-silicon nitride layers. Such selectivity enhancements are known in the art. With the anisotropic dry etch, the etched dielectric cap layer 323B will not be undercut sufficiently to form the collapsed dielectric layer 321C. However, the collapsed dielectric layer 321C is not necessary to either practice or fabricate the present invention.
With reference to FIG. 3K, portions of each of the remaining layers overlying the patterned dielectric layer 307B, namely, the second copper-barrier layer 313A, the MIM dielectric layer 315A, and the third copper-barrier layer 317A, are etched thus forming an etched second copper-barrier layer 313B, an etched MIM dielectric layer 315B, and an etched third copper-barrier layer 317B. Note, also the patterned dielectric layer 307B may be partially etched, depending on the material selected to form the patterned dielectric layer 307B and the etchant selected, thus forming an etched patterned dielectric layer 307C. Consequently, the etched patterned dielectric layer 307C serves as an etch-stop layer. In a specific exemplary embodiment, RIE is selected to etch portions of the layers overlying the patterned dielectric layer 307B.
The MIM top plate patterned photoresist layer 325 and the etched second BARC layer 323B are removed in FIG. 3L by, for example, an oxygen-plasma ashing step. Construction of the high-Q planar MIM capacitor is substantially complete. Steps for producing a top-plate electrode commence with FIG. 3M in which a multi-layer dielectric is formed over the completed MIM capacitor in preparation for a dual-damascene electrode process. Each of the first 327A, second 329A, third 331A, and fourth 333A dielectric layers are chosen so as to allow a selective etchant to be used in which one layer is etched faster than one or more adjacent layers. For example, in a specific exemplary embodiment, the first dielectric layer 327A is selected to be Si3N4 ranging from 200 Å to 1000 Å in thickness, the second dielectric layer 329A is selected to be a deposited oxide ranging from 2000 Å to 8000 Å in thickness, the third dielectric layer 331A is selected to be Si3N4 ranging from 100 Å to 700 Å in thickness, and the fourth dielectric layer 333A is selected to be a deposited oxide ranging from 0.5 μm to 1 μm in thickness. One of skill in the art will recognize, however, that the ranges given are approximate and may vary depending upon factors such as particular films chosen and specific process parameters employed.
In FIG. 3N, a chemical-mechanical planarization step planarizes the fourth dielectric layer 333A creating a planarized dielectric layer 333B. In FIG. 3O, A fifth dielectric layer 335 is formed over the planarized dielectric layer 333B. A thickness range of the fifth dielectric layer 335 may be, for example, 300 Å to over 1000 Å in thickness.
In a specific exemplary embodiment, the fifth dielectric layer 335 is a Si3N4 hard mask. In this embodiment, the hard mask acts (1) as a complementary anti-reflection dielectric during subsequent via and trench lithography steps; and (2) to protect the planarized dielectric layer 333B during a subsequent etch of the first dielectric layer 327A. The etch of the first dielectric layer 327A is generally performed after the transfer of the trench pattern into the fifth dielectric layer 335 and the planarized dielectric layer 333B and oxygen-plasma ashing of a trench lithography BARC/photoresist stack (not shown). The first dielectric layer 327A etch is a self-aligned etch without the protection of the removed BARC/photoresist stack. Therefore, the Si3N4 hard mask is mainly a sacrificial layer and is used to preserve the trench depth in the underlying oxide.
With reference to FIG. 3P, the overlying multi-layer film stack is etched forming etched first 327B, second 329B, third 331B, and fourth 333B dielectric layers. The various layers define a trench bottom/via top wherein the via extends to electrically contact the copper MIM top plate 319B. Via and trench walls are lined with a copper-barrier layer 337 and a dual-damascene electroplated copper layer 339 simultaneously fills the via and the trench, thus completing the electrode connection to the copper MIM top plate 319B. As is known in the art, growth of the electroplated copper layer 339 is polycrystalline. Grain size within the copper layer 339 is dependent on factors such as texture (i.e., microroughness) of underlying layers, parameters of growth conditions such as temperature, plating voltages, etc., as well as dimensions of trenches to be filled (e.g., dimensions of grooves or vias). Grain size and consequently overall resistivity of the copper trench/via may be controlled through appropriate anneal steps as needed.
In the foregoing specification, the present invention has been described with reference to specific embodiments thereof. It will, however, be evident to a skilled artisan that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. For example, skilled artisans will appreciate that many types of deposition technology, such as sputtering, chemical vapor deposition (CVD), physical vapor deposition (PVD), electron beam evaporation (EBE), electrochemical deposition (ECD), thermal evaporation, and others may readily be employed for various layers described. Further, the substrate type may be selected based upon an intended use of a finalized product. For example, an ASIC used as an integrated circuit for a computer may be formed on a silicon wafer. In an RF integrated circuit used for lightweight applications or flexible circuit applications, such as a cellular telephone or personal data assistant (PDA), the integrated circuit may be formed on a polyethyleneterephthalate (PET) substrate deposited with silicon dioxide and polysilicon followed by an excimer laser annealing (ELA) anneal step. Skilled artisans will appreciate that other types of semiconducting and insulating materials other than those listed may be employed. For example, a BARC layer may improve processing and edge wall definition of photoresist layer used as etch masks, but the BARC layer is not required. Additional particular process fabrication and deposition techniques, such as low pressure chemical vapor deposition (LPCVD), ultra-high, vacuum CVD (UHCVD), and low pressure tetra-ethoxysilane (LPTEOS) may be readily employed for various layers and still be within the scope of the present invention. Although the exemplary embodiments describe particular types of dielectric and semiconductor materials, one skilled in the art will realize that other types of materials and arrangements of materials may also be effectively utilized and achieve the same or similar advantages. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.
Patent Application
20080089007
