1. Field of the Invention
The invention relates to a method for fabricating semiconductor device, and more particularly, to a method for fabricating metal-oxide semiconductor transistor.
2. Description of the Prior Art
A conventional MOS transistor generally includes a semiconductor substrate, such as silicon, a source region, a drain region, a channel positioned between the source region and the drain region, and a gate located above the channel. The gate is composed of a gate dielectric layer, a gate conductive layer positioned on the gate dielectric layer, and a plurality of spacers positioned on the sidewalls of the gate conductive layer. Generally, for a given electric field across the channel of a MOS transistor, the amount of current that flows through the channel is directly proportional to a mobility of the carriers in the channel. Therefore, how to improve the carrier mobility so as to increase the speed performance of MOS transistors has become a major topic for study in the semiconductor field.
The formation of SiGe source/drain regions is commonly achieved by epitaxially growing a SiGe layer adjacent to the spacers within the semiconductor substrate after forming the spacer. In this type of MOS transistor, a biaxial tensile strain occurs in the epitaxial silicon layer due to the silicon germanium, which has a larger lattice constant than silicon, and, as a result, the band structure alters, and the carrier mobility increases. This enhances the speed performance of the MOS transistor.
However, it should be noted in the conventional art for conducting selective epitaxial growth process to form epitaxial layer, the epitaxial layer is typically grown against the sidewall of the spacer. This type of growing behavior often causes reduced strain in the channel region of the transistor and induces a Ion degradation phenomenon. As a result, the performance of the device is affected substantially.
It is an objective of the present invention to provide a method for fabricating semiconductor transistor for resolving the aforementioned issue.
According to a preferred embodiment of the present invention, a method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate, wherein the substrate comprises a gate structure thereon; forming a film stack on the substrate and covering the gate structure, wherein the film stack comprises at least an oxide layer and a nitride layer; removing a portion of the film stack for forming recesses adjacent to two sides of the gate structure and a disposable spacer on the sidewall of the gate structure; and filling the recesses with a material comprising silicon atoms for forming a faceted material layer.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Referring to
Next, an offset spacer 20 is formed on the sidewall of the gate structure 12, in which the offset spacer 20 is composed of material such as silicon nitride. An ion implantation is then conducted by using the gate structure 12 and the offset spacer 20 as a mask to implant p-type or n-type dopants into the substrate 10 adjacent to two sides of the offset spacer 20. This ion implantation preferably forms a lightly doped drain 24 at two sides of the gate structure 12.
Next, as shown in
Next, as shown in
In addition to the above approach for forming the disposable spacer 30, another embodiment of present invention could first deposit an oxide layer 22 between 30-70 Angstroms, such as preferably at 50 Angstroms on the substrate 10, the offset spacer 20, and the gate structure 12, as shown in
It should be noted that despite a DPN process is conducted to inject nitrogen-containing substance 32 between the oxide layer 22 and the nitride layer 24 in the above embodiment, a rapid thermal anneal process or a furnace anneal process could also be performed on the oxide layer 22 in a nitrogen-containing environment for forming the oxide layer 22 having nitrogen-containing substance 32, which is also within the scope of the present invention.
Next, as shown in
In contrast to the conventional selective epitaxial growth process of growing the epitaxial layer right along the spacer composed of silicon nitride, the disposable spacer of the present invention is preferably composed of an L-shaped oxide layer and a nitride layer disposed on the L-shaped oxide layer. As the L-shaped oxide layer is adhered to the surface of the substrate and immediately adjacent to the source/drain region, the present invention could prevent the epitaxial layer to grow against the sidewall of the disposable spacer. Instead, a gap is formed between the epitaxial layer and the sidewall of the disposable spacer, and a faceted epitaxial layer, such as a hexagonal epitaxial layer is formed in the substrate. It should be noted that the faceted feature is preferably demonstrated in the portion of the epitaxial layer 36 above the substrate 10, such that the angle of the epitaxial layer 36 is preferably around 15-60 degrees. For instance, the angle included between the (111) face of the epitaxial layer and the (100) face of the substrate is about 54.74 degrees and the angle included between the (113) face of the epitaxial layer and the (100) face of the substrate is about 25.24 degrees. The entire shape of epitaxial layer 36 however is not limited to hexagonal. Instead, the parameter of the etching process carried out to form the recess 28 in the substrate 10 could be used to determine the shape of the epitaxial layer 36.
Next, as shown in
Similar to the aforementioned embodiment of using selective strain scheme for forming epitaxial layer, if the transistor fabricated is an NMOS transistor, a tensile stress layer could be formed on the gate structure and the substrate for carrying out the stress memorization technology. However, if the transistor fabricated is a PMOS transistor, a compressive stress layer could be formed on the gate structure and the substrate for carrying out the stress memorization technology. As the process of stress memorization technology is well known to those skilled in the art, the details of which are omitted herein for the sake of brevity.
Next, a salicide process is performed by sputtering a metal layer (not shown) composed of cobalt, titanium, platinum, palladium, or molybdenum on the epitaxial layer and conducting at least one rapid thermal anneal process to react the metal layer and the epitaxial layer for forming a silicide layer (not shown). A contact etch stop layer (CESL) and an interlayer dielectric layer could then be deposited on the substrate 10. As the process for fabricating these elements are well known to those skilled in the art, the details of which are omitted herein for the sake of brevity.
It should be noted that despite the disposable spacer 30 is removed before the formation of the stress transfer structure, the disposable spacer 30 could also be removed before the formation of the CESL, which is also within the scope of the present invention.
Overall, the present invention preferably forms a film stack composed of an oxide layer and a nitride layer on the substrate and the gate structure, such that during the formation of epitaxial layer, the epitaxial layer contacting the oxide layer would not grow along the sidewall of the disposable spacer. Instead, a gap is formed between the epitaxial layer and the disposable spacer and a faceted hexagonal source/drain region is formed. After removing a portion of the film stack, two recesses are formed in the substrate adjacent to two sides of the gate structure and a disposable spacer is formed on the sidewall of the gate structure.
Moreover, as the dry etching and wet etching process conducted for forming the recesses of the epitaxial layer typically damage the oxide material of the disposable spacer, another embodiment of the present invention preferably conducts a decoupled plasma nitridation process to form nitrogen-containing substance in the oxide layer, which could then be used to protect the oxide layer from damage caused by the subsequent etching processes.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.