Patent Application
20130005122
The invention generally relates to the manufacturing of substrates intended for applications in the fields of electronics, optics and optoelectronics. More specifically, it relates to a method for finishing a substrate known under the acronym of SeOI (“Semiconductor-On-Insulator”). The invention finds particular application in the finishing of an “SOI” substrate, wherein the semiconductor is silicon.
Among the different manufacturing methods used, mention may be made of those using steps for bonding and transferring layers. An example of such a method is described hereafter.
According to this method, an embrittlement area is generated within a first so-called “donor” substrate, covered with an insulating layer, for example, by implantation of atomic and/or ionic species. This substrate is then adhered by molecular adhesion to a second so-called “receiver” substrate.
Next, the donor substrate is separated into two portions, along this embrittlement area, for example, by detachment annealing (“exfoliation” or “splitting”), so that an intended thickness of the material of the donor substrate, as well as the insulator layer, are transferred onto the receiver substrate.
Reference may, for example, be made on this subject to the method known under the registered trade mark “UNIBOND®” of the applicant.
The appended
Now, additional treatments are frequently carried out on such an SOI (or SeOI) substrate notably for improving its surface condition, in particular, for reducing its roughness or for strengthening the adhesive bond between two layers. Such treatments often involve chemical etching, for example, with hydrofluoric acid (HF).
Such a treatment applied to an SOI substrate, as the one illustrated in
In order to overcome this problem, a method for treating an SOI substrate with Rapid Thermal Annealing (known as “RTA” to the person skilled in the art) is known from U.S. Pat. No. 6,939,783, this treatment having the effect of generating a side encapsulation of the edge of the silicon oxide layer 2 with the silicon located above.
The appended
Now, the applicant carried out tests and unfortunately noticed that the expected protective beneficial effects of the encapsulation were not always obtained since the edge of the transferred silicon layer 3 may have irregularities relative to the ideal case illustrated in
The applicant discovered that defects, present at the edge of an SeOI or SOI substrate and although being part of an exclusion area within which no electronic component will be produced, may perturb the encapsulation phenomenon.
Among the latter, a first type of defect designated as “flakes” is formed by pieces of the substrate that have appeared during detachment and that have been detached and then again notably adhesively bonded onto the edge of the substrate.
Such flakes 31 are visible in the appended
A second type of defect called “jagged edge” is formed by extensions of the surface of the upper layer of silicon beyond the usual edge of the transferred surface.
Such defects 32 are visible in the aforementioned
The applicant thus discovered that the obtained encapsulation, when it is achieved by an RTA treatment, may be perturbed, notably be too thin at the top of the jagged edges 32. When this encapsulation is carried out by epitaxy treatment, it may also be perturbed, or even completely anarchical at the flakes 31 on which a larger amount of encapsulation material may be formed with, for example, the formation of material excrescences.
The encapsulation may not even be complete, depending on the shape of the irregularities present at the edge of the substrate (plate edge) and, consequently, certain portions of the buried insulator may remain accessible to chemical etching, for example, with hydrofluoric acid (HF).
Moreover, certain flakes or jagged edge pieces may be detached from the receiver substrate before the encapsulation and be redeposited on the surface layer 3 of the SeOI substrate, and then be definitively sealed by the encapsulation, thereby generating defects on this layer.
The appended
The object of the invention is, therefore, to solve the aforementioned drawbacks of the state of the art.
The object of the invention is notably to provide a method for finishing a substrate of the SeOI type with which it is possible to have very good quality encapsulation of the side edge of the buried insulator, i.e., a homogeneous encapsulation, such that the side edge of the insulator is covered over its totality with a layer of semiconducting material with a relatively constant thickness and the edge of this layer forms a regular crown at a constant distance from the edge of the plate.
For this purpose, the invention relates to a method for finishing a substrate of the semiconductor-on-insulator (SeOI) type comprising an insulator layer buried between two layers of semiconducting material.
According to the invention, this method successively comprises:
According to other advantageous and non-limiting features of the invention, taken alone or as a combination:
Other features and advantages of the invention will become apparent from the description which will now be made, with reference to the appended drawings, which illustrate as an indication and not as a limitation, a possible embodiment thereof.
On these drawings, in addition to the ones already described:
In the diagrams of
The method according to the invention is a so-called “finishing” method for a substrate of the semiconductor-on-insulator SeOI type, since it relates to steps carried out after the detachment annealing, which results in the transfer of layer(s) and in the formation of this substrate comprising an insulator layer buried between two semiconducting material layers.
The method according to the invention will now be described with reference to
Referring to
As this may be seen in this figure, at the end of the step for transferring layer(s), the SeOI substrate 4 obtained has defects of the aforementioned type, i.e., flakes 44, only one of which is visible in this figure, and an annular peripheral jagged edge referenced as 45.
The first step of the method according to the invention consists of carrying out routing of the peripheral annular edge of the substrate 4. This step is illustrated in
Its application methods will be described hereafter. This routing step has the effect of removing over a certain width L the edge of the surface layer 41 and the edge of the buried insulator layer 42. Preferably, this routing is conducted so as to route the substrate at a constant and controlled distance from the physical edge of the substrate.
Optionally, the routing may also be conducted until a portion of the annular periphery of the support 43 is removed over a depth P.
L is a width typically varying from 0.5 to 3 mm. L is selected to be slightly greater than the width of the crown present on the SeOI so as to remove by routing the defects of the flake or jagged edge type and to obtain a crown of constant width after routing.
P varies from 0 to a few thousands of angstroms, typically 500-1,000 Å (50 to 100 nm).
In
The routed substrate is referenced as 4′.
The following step, illustrated in
The portion of the material 41 encapsulating the insulator 42 is referenced as 410. The routed and encapsulated substrate is referenced as 4″.
The methods for applying this encapsulation step will be described hereafter.
Preferably, the encapsulation step is carried out immediately after the routing one, so as to avoid any accidental contamination of the routed substrate before the encapsulation and to at most limit the risk of alteration of the quality of the film edge obtained by routing. The encapsulation should be made before the edge loses its regularity. The film consisting of the surface layer 41 and of the buried insulator 42 is then only still slightly adhered to the receiving supporting substrate 43 and its edge notably should be reinforced in order to avoid tears or scratches.
According to an alternative embodiment, the encapsulation may also be carried out immediately after a cleaning step, itself carried out after routing.
This routing may be carried out by various techniques and notably by mechanical grinding or an etching step.
The grinding may, for example, be achieved by placing the substrate 4 on a support driven into rotation, by bringing into the proximity of its edge, a polishing shoe, optionally covered with an abrasive solution (“slurry”) and by applying the latter on the edge of the substrate 4 over a width L to be routed.
Reference may be made on this subject to documents U.S. Pat. No. 6,797,632 and U.S. Patent Publication 2007/0243694, which describe routing by grinding and/or polishing.
The routing may also be carried out by wet or dry etching.
Wet etching consists of forming a protective mask on a central portion of the front face 411 of the surface layer 41, this mask being of a diameter of less than that of the layer 41, so as to leave an unprotected annular peripheral area. The substrate is then successively exposed to specific etching solutions for the materials forming the surface layer 41 and the insulating layer 42, so as to etch and remove the unprotected edges of the substrate 4.
Dry etching consists of submitting the edge of the substrate 4 unprotected by a mask, to gas etching, for example with an isotropic or anisotropic plasma.
Reference may for example be made to document U.S. Patent Publication 2009/0170285, which describes a dry etching method.
When it is desired to obtain a particularly clean routed edge, i.e., perpendicular or quasi perpendicular to the plane of the front face 411, it is possible to use the installation and the routing method, which will now be described in connection with
In these figures, the substrate 4 is chamfered, so that its front face 411 is broken down into a non-chamfered planar central area 411a and into a chamfered peripheral area 411b and so that also its rear face 430 is broken down into a non-chamfered planar area 430a and a chamfered area 430b.
Its side edge is referenced as 46.
The routing is carried out inside a reactor 5 for forming plasma, as the one illustrated in
This reactor comprises an enclosure 50, inside which are installed two insulating elements 53, 54 and two electrodes 51, 52, the latter being connected to an electric power supply not shown in the figures.
The substrate 4 to be routed rests on the lower electrode 52 and the lower insulating element 54, through its rear face 430.
The lower electrode 52 is surrounded by the lower insulating element 54 with a circular contour. Preferably, the electrode 52 is circular and the insulating element 54 is annular.
Moreover, the upper insulator 53 is disk-shaped and the electrode 51 that surrounds it is ring-shaped.
The upper insulating element 53 is mounted on driving means, not shown in the figures, that allow its displacement along a vertical axis perpendicular to the middle plane of the substrate 4, itself parallel to the rear face 430. It may thereby be displaced between a position illustrated in
The gases used for forming a plasma are introduced into the inside of the enclosure 50 via ducts, for example, here two in number, referenced as 55 and 56.
The volatile materials, produced during the reaction that occurs in the inside of the enclosure 50, may be discharged out of the latter by suction means and through an orifice not shown in the figures.
Voltage is applied to the electrodes 51 and 52, which has the effect of generating an electric field inside the enclosure 50 and of transforming the gases introduced into the ducts 55 and 56 into plasma.
Different parameters, such as the temperature and pressure prevailing inside the enclosure 50, the nature, the flow rate and the ratios of the gases introduced into the inside of the enclosure 50, the frequency of the plasma, as well as the power applied on the terminals of the electrodes 51 and 52, have an incidence on the chemical composition of the formed plasma and on its nature, i.e., a deposition plasma or an etching plasma. These parameters will be detailed hereafter.
Preferably, the plasma formed, both for deposition and for etching, is isotropic. This means that the action of the plasma is preferably achieved via radicals created in the plasma and, optionally, may be carried out via ions accelerated in the sheath of the plasma.
The fact that the rear face 430 of the substrate 4 is in contact with the lower electrode 52 and with the lower insulator 54, allows an exclusion area to be defined on the rear face, referenced as 540, inaccessible to the plasma since it is masked.
As this may be seen in the figures, the outer diameter of the insulator 54 exactly corresponds to the diameter of the exclusion area on the rear face 540 since the substrate 4 to be routed is directly in contact with the insulator 54.
Further, the substrate 4 to be routed is, of course, positioned so as to be centered relatively to the annular insulator 54.
Moreover, the upper insulator 53 also allows definition on the front face 411 of the substrate, of a so-called “front face exclusion” area 530, inaccessible to the plasma.
The diameter of the front face exclusion area 530 not only depends on the diameter of the upper insulator 53, but also on its distance from the substrate 4 to be routed. Thus, the more the insulator 53 is moved away from the front face 411 of the substrate, the smaller the diameter is of the front face exclusion area 530 (see
The annular peripheral area substrate 4 that remains accessible to the plasma, i.e., the area that extends out of the aforementioned areas 530 and 540, is referenced as 500.
The different steps of the routing method will now be described.
After the substrate 4 to be routed has been introduced into the enclosure 5, so that its rear face 430 rests against the insulating element 54 and the lower electrode 52, the parameters for forming the plasma are adjusted so as to deposit on the accessible annular area 400, a layer of a protective material 6.
Preferably, this protective material 6 is a polymer.
Still preferably, this is a polymer of the polyethylene type, obtained with a plasma formed from ethylene C2H4.
The upper insulator 53 is then brought closer to the front face 411 of the substrate 4, so as to enlarge the front face exclusion area 530 and to increase the diameter thereof. It will be noted that the insulator 53 is never brought into contact with the upper face 411 of the substrate, so as to avoid damaging or contaminating the latter.
In this position, illustrated in
This partial etching is possible because of the enlargement of the front face exclusion area 530. In the position of the insulator 53 illustrated in
The nature of the plasma for etching the protective material 6 is, of course, dependent on the chemical nature of this material.
As an example, for a protective material in polyethylene, etching is carried out with a plasma based on oxygen (O2).
The following step is illustrated in
As an example, when the material forming the surface layer 41 is silicon, the etching plasma is a mixture of argon and SF6 (sulfur hexafluoride) and optionally nitrogen and when the material forming the insulator 42 is oxide, the etching plasma is then a mixture of nitrogen and CHF3 (trifluoromethane) or further a mixture of oxygen (O2) and of tetrafluoromethane (CF4).
As illustrated in
If necessary, routing may be continued in order to etch a portion of the support 43 over a depth P.
Finally, as illustrated in
For all the steps that have just been described and that relate to the use of a deposition plasma or an etching plasma, the conventional frequency of the plasma is 13.56 MHz. The power is of the order of 100 to 500 W. The duration of application of the plasma varies between 5 and 40 seconds. The combination of the power and of the duration of the plasma notably induces an effect on the etched thickness. Finally, the pressure inside the enclosure is of the order of a few torrs (1 torr being equal to about 102 Pa or more precisely 133 Pa).
This encapsulation may be achieved with a rapid thermal annealing treatment known under the acronym of “RTA” (Rapid Thermal Annealing), which may advantageously be preceded by a cleaning step.
Typically, this may be standard cleaning such as a sequence: ozone (O3)/RCA, the latter treatment consisting of treating the surfaces successively with:
The RTA treatment is carried out at a high temperature for a short period.
Preferably, this heat treatment is carried out at a temperature comprised between about 1,150° C. and 1,300° C., still preferably at about 1,200° C. This treatment is conducted for a duration of 15 seconds to 5 minutes, preferably for less than 3 minutes. This RTA is preferably achieved in a hydrogen and/or argon atmosphere.
The encapsulation treatment may also be carried out by epitaxy.
The encapsulation may be achieved by an RTA treatment followed by epitaxy or vice versa, these steps being achieved under the same conditions as those described earlier.
The encapsulation may also be achieved with laser annealing (“laser anneal”). This annealing may optionally be local and limited to the edge of the routed film comprising the surface layer 41 and the insulator 42.
The method according to the invention, therefore, has many advantages. With it, it is possible to obtain a peripheral crown width L1 around the encapsulated portion, not only regularly all around the SeOI substrate, but also in a reproducible way from one substrate to the other (see
The method according to the invention further allows a substantial reduction in the overall defectivity of the substrates made. Indeed, the routing step not only allows removal of the flakes 44 and of the jagged edges 45, but also of a large proportion of the particles present at the edge and, which, in the absence of such a step, would be capable of being deposited on the surface layer 41 of the SeOI during the cleaning step preceding the RTA treatment. Without this routing step, such semiconducting material particles may be displaced from the periphery toward the center of the substrate and be definitively sealed on this substrate during the RTA treatment.
Finally, the invention finds a particular application in finishing treatments including sacrificial oxidation and deoxidation steps.
Two exemplary methods will be mentioned including the finishing steps according to the invention.
A first method comprises the following steps:
A second method is the following:
Both of these methods are particularly used for providing substrates intended for partially or fully depleted SOI applications.
| Number | Date | Country | Kind |
|---|---|---|---|
| 1051918 | Mar 2010 | FR | national |
This is a national phase entry under 35 U.S.C. §371 of International Patent Application PCT/EP2011/053760, filed Mar. 14, 2011, published in English as International Patent Publication WO 2011/113775 A1 on Sep. 22, 2011, which claims the benefit under Article 8 of the Patent Cooperation Treaty to French Patent Application Serial No. 1051918, filed Mar. 18, 2010, the disclosure of each of which is hereby incorporated herein by this reference in its entirety.
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/EP2011/053760 | 3/14/2011 | WO | 00 | 9/5/2012 |
