Claims
- 1. A method for forming an interconnection in an integrated circuit comprising the steps of:
- providing a semiconductive substrate of a first conductivity type;
- forming a cavity in said substrate;
- forming an insulating layer on the walls of said cavity;
- forming a conductive layer on said insulating layer;
- forming a crevice between said conductive layer and said substrate by removing a portion of said insulating layer between said substrate and said conductive layer; and
- filling said crevice with a conductive contacting material.
- 2. The method of claim 1 further comprising forming a region of a second conductivity type in said substrate adjacent to said conductivde contacting material.
- 3. A method as in claim 1 wherein said removed portion of said insulating layer is removed by liquid chemical etching.
- 4. A method as in claim 1 wherein said conductive material is polycrystalline silicon deposited by conformal deposition.
- 5. A method as in claim 4 wherein said conformal deposition is chemical vapor deposition.
- 6. A method as in claim 2 wherein said region of a second conductivity is formed by diffusion of dopant atoms from said conductive layer through said conductive contacting material into said substrate.
RELATED APPLICATIONS
This application is a continuation of application Ser. No. 06/799,048, filed 11/18/85, now abandoned, which is a continuation-in-part of Ser. No. 666,715 filed Oct. 31, 1984, now abandoned.
US Referenced Citations (6)
Foreign Referenced Citations (2)
Number |
Date |
Country |
59-32168 |
Feb 1984 |
JPX |
62-208671 |
Sep 1987 |
JPX |
Continuations (1)
|
Number |
Date |
Country |
Parent |
799048 |
Nov 1985 |
|
Continuation in Parts (1)
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Number |
Date |
Country |
Parent |
666715 |
Oct 1984 |
|