Claims
- 1. A method used during the formation of a semiconductor device comprising the following steps:providing a semiconductor substrate assembly; forming a conductive layer over said semiconductor substrate assembly; depositing a first dielectric layer overlying said conductive layer; removing a portion of said first dielectric layer to form at least first and second openings therein, wherein said conductive layer is exposed by said openings in said first dielectric layer and provides an electrical path between said first and second openings; subsequent to said step of removing a portion of said first dielectric layer, etching said conductive layer at said openings to recess said conductive layer within said first dielectric layer; and subsequent to said step of etching said conductive layer, forming a second dielectric layer within said openings in said first dielectric layer to electrically isolate said conductive layer from said openings.
- 2. The method of claim 1 further comprising the step of electrically isolating said conductive layer from any other conductive layer during said step of forming said second dielectric layer.
- 3. The method of claim 1 further comprising the step of etching said second dielectric layer wherein said conductive layer remains electrically isolated subsequent to etching said second dielectric layer.
- 4. The method of claim 1 further comprising the step of forming a substantially vertical sidewall in said dielectric layer during said step of removing a portion of said dielectric layer.
- 5. A method used during the formation of a semiconductor device comprising the following steps:providing a semiconductor substrate assembly comprising at least first and second conductive lines each having a sidewall; forming a first blanket dielectric layer over said sidewalls of said first and second conductive lines; forming first and second conductive spacers between said first and second conductive lines; depositing and planarizing a second blanket dielectric layer over said spacers and said first dielectric layer; etching said second blanket dielectric layer to form an opening therein and a substantially vertical sidewall, wherein said conductive spacers are exposed at said opening; and subsequent to said step of etching said second blanket dielectric layer, etching said conductive spacers.
- 6. The method of claim 5 further comprising the step of forming a third dielectric layer within said opening subsequent to said step of etching said conductive spacers, thereby electrically isolating said conductive spacer from said opening.
- 7. The method of claim 5 wherein said step of etching said conductive spacers includes the step of forming a substantially vertical end of each said spacer, said ends being substantially aligned with said sidewall of said second dielectric layer.
- 8. The method of claim 5 wherein said step of etching said conductive spacers includes the steps of forming an end of each said spacer and recessing said ends into said second dielectric layer.
- 9. A method used during the formation of a semiconductor device comprising the following steps:providing a semiconductor substrate assembly; forming at least one conductive spacer over said semiconductor substrate assembly; depositing and planarizing a dielectric layer over said conductive spacer; etching said dielectric layer to form a sidewall from said dielectric layer and to expose said conductive layer; and subsequent to forming said sidewall from said dielectric layer, etching said conductive spacer to form first and second conductive spacer ends, wherein said etch recesses said first and second ends within said dielectric layer.
- 10. The method of claim 9 wherein said dielectric layer is a first dielectric layer further comprising the step of forming a second dielectric layer over said sidewall and electrically isolating said conductive spacer from contact with any other conductive spacer.
- 11. A semiconductor device comprising:a semiconductor substrate assembly; at least one conductive spacer having first and second ends, wherein said spacer overlies said semiconductor substrate assembly; and a dielectric layer overlying said conductive spacer, wherein said first and second ends of said spacer are recessed within said dielectric layer and said conductive spacer does not contact any other conductive layer.
Parent Case Info
This is a continuation of application Ser. No. 08/968,564 filed Nov. 12, 1997 and issued Apr. 4, 2000 as U.S. Pat. No. 6,046,505, which was a continuation of application Ser. No. 08/500,293 filed Jul. 10, 1995 and issued Nov. 11, 1997 as U.S. Pat. No. 5,686,357.
US Referenced Citations (8)
Non-Patent Literature Citations (1)
Entry |
S. Wolf, “Silicon Processing for the VLSI Era vol. 2” Lattice Press, Calif. (1990) p. 199. |
Continuations (2)
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Number |
Date |
Country |
Parent |
08/968564 |
Nov 1997 |
US |
Child |
09/542124 |
|
US |
Parent |
08/500293 |
Jul 1995 |
US |
Child |
08/968564 |
|
US |