Claims
- 1. A method for forming a trench isolation structure in an integrated circuit comprising:etching a first portion of a semiconductor substrate to form a trench; forming a first dielectric layer by thermal oxidation along a wall of the trench, wherein the first dielectric layer does not completely fill the trench; annealing the first dielectric layer after its formation; depositing a second dielectric layer within the trench, wherein the second dielectric layer is formed after the first dielectric layer is annealed; and removing a portion of the second dielectric layer to form a trench plug within the trench.
- 2. The method of claim 1, further comprising annealing the second dielectric layer before removing the portion of the second dielectric layer.
- 3. The method of claim 1, wherein removing the portion of the second dielectric layer comprises chemically mechanically polishing the second dielectric layer.
- 4. The method of claim 1, further comprising:forming a buffer layer overlying the semiconductor substrate; forming an oxidation resistant layer overlying the buffer layer; patterning the oxidation resistant layer and the buffer layer to leave a remaining portion of the oxidation resistant layer overlying a remaining portion of the buffer layer, and to form the first portion of the semiconductor substrate, wherein patterning is performed before etching the first portion of the semiconductor substrate; and removing the remaining portion of the oxidation resistant layer to expose the remaining portion of the buffer layer after removing a portion of the second dielectric layer.
- 5. The method of claim 4, further comprising:annealing the remaining portion of the buffer layer in an oxidizing ambient to form a sacrificial oxide layer underlying the remaining portion of the buffer layer, wherein the sacrificial oxide layer is formed after the remaining portion of the oxidation resistant layer has been removed; and removing the sacrificial oxide layer to form a second exposed portion of the semiconductor substrate.
- 6. The method of claim 1, further comprising isotropically etching a portion but not all of the first dielectric layer before forming the second dielectric layer.
- 7. The method of claim 1, wherein the second dielectric layer comprises silicon and oxygen.
- 8. The method of claim 1, wherein:thermally growing a gate dielectric layer from a second portion of the semiconductor substrate outside of the trench; and forming a gate electrode over the gate dielectric layer, wherein: the gate electrode includes a conductive layer; and the conductive layer is a first layer formed after thermally growing the gate dielectric layer.
RELATED APPLICATIONS
This application is related to U.S. patent application Ser. No. 08/416,243, filed on Apr. 4, 1995 now U.S. Pat. No. 5,786,263, entitled “Method For Forming A Trench Isolation Structure In An Integrated Circuit”, and assigned to the currant assignee hereof. This application is related to U.S. patent application Ser. No. 09/059,496, filed on Apr. 13, 1998 now abandoned, entitled “Method For Forming A Trench Isolation Structure In An Integrated Circuit”, and assigned to the currant assignee hereof.
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