Patent Application
20130277810
The present disclosure relates to a method of fabricating semiconductor devices with backside cooling. The present disclosure is particularly applicable to semiconductor devices in 65 nanometer (nm) technology nodes and beyond.
The integration of hundreds of millions of circuit elements, such as transistors, on a single integrated circuit necessitates further scaling down or micro-miniaturization of the physical dimensions of circuit elements, including interconnection structures. Micro-miniaturization has engendered a dramatic increase in transistor engineering complexity, resulting in several problems.
One such problem is the difficulty in dissipating heat generated by the integrated circuit. This difficulty is compounded based on the micro-miniaturization of the physical dimensions of circuit elements such that more heat is produced in smaller areas. This heat may build-up in the substrates of the integrated circuits causing, for example, degradation of the substrate.
A need therefore exists for methodology enabling fabrication of semiconductor devices with improved cooling efficiency and the resulting structure.
An aspect of the present disclosure is an efficient method of fabricating a semiconductor device with through silicon vias extending into the semiconductor substrate from a backside surface.
Another aspect of the present disclosure is a semiconductor device including through silicon vias extending into the semiconductor substrate from a backside surface.
Additional aspects and other features of the present disclosure will be set forth in the description which follows and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present disclosure. The advantages of the present disclosure may be realized and obtained as particularly pointed out in the appended claims.
According to the present disclosure, some technical effects may be achieved in part by a method including: forming a cavity in a backside surface of a substrate, the substrate including a gate stack on a frontside surface; and filling the cavity with a thermally conductive material.
Aspects of the present disclosure include forming a liner material layer in the cavity prior to filling the cavity with the thermally conductive material. Another aspect includes filling the cavity by electrochemical plating (ECP). A further aspect includes forming a second cavity in the backside surface of the substrate, and filling the second cavity with the thermally conductive material, where a pitch ratio of an average diameter of the first and second cavities to a distance between the first and second cavities is 1:x, where x can be 2 or larger. An additional aspect includes forming the cavity to a depth of 6 to 10 μm. Yet an additional aspect includes forming the cavity to a width of 6 μm or larger at the backside surface of the substrate. Yet an additional aspect includes aligning the cavity with an area of higher heat generation. Another aspect includes forming a layer of the thermally conductive material on the backside surface of the substrate.
Another aspect of the present disclosure includes a method including: etching a backside surface of a silicon substrate forming cavities in the backside surface, the substrate including at least one gate stack on a frontside surface; forming a liner in each cavity; forming a metal barrier layer over the liner; and electrochemical plating copper on the backside surface of the substrate, filling the cavities with copper, forming through silicon vias (TSVs) in the backside surface of the substrate.
Another aspect of the present disclosure is a device including: a substrate having a frontside surface and a backside surface, the substrate including a gate stack on the frontside surface; and a thermally conductive material extending into the substrate from the backside surface.
Aspects include a device including copper as the thermally conductive material. Further aspects include a layer of liner material between the thermally conductive material and the substrate, for example, having a thickness of 0.3 to 0.8 μm. An additional aspect includes a metal barrier layer over the layer of liner material. Yet another aspect includes the thermally conductive material comprising a pair of TSVs, and a pitch ratio of an average diameter of the TSVs and a distance between the pair of TSVs is 1:x, where x can be 2 or larger. Another aspect includes the TSVs having a width at the backside surface of the substrate of 6 μm or larger. A further aspect includes the thermally conductive material being aligned with an area of higher heat generation. An additional aspect includes the thermally conductive material extending 6 to 10 μm into the substrate. Further aspects include a layer of the thermally conductive material on the backside surface of the substrate, for example, having a thickness of 3 to 6 μm.
Additional aspects and technical effects of the present disclosure will become readily apparent to those skilled in the art from the following detailed description wherein embodiments of the present disclosure are described simply by way of illustration of the best mode contemplated to carry out the present disclosure. As will be realized, the present disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present disclosure. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
The present disclosure is illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which like reference numerals refer to similar elements and in which:
In the following description, for the purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of exemplary embodiments. It should be apparent, however, that exemplary embodiments may be practiced without these specific details or with an equivalent arrangement. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring exemplary embodiments. In addition, unless otherwise indicated, all numbers expressing quantities, ratios, and numerical properties of ingredients, reaction conditions, and so forth used in the specification and claims are to be understood as being modified in all instances by the term “about.”
The present disclosure addresses and solves the current problem of the buildup of heat in semiconductor devices. In accordance with embodiments of the present disclosure, TSVs are formed extending into a substrate of a semiconductor device from a backside surface of the substrate to increase the cooling efficiency of the semiconductor device.
Methodology in accordance with embodiments of the present disclosure includes forming a cavity in a backside surface of a substrate, such as by etching the substrate. The substrate may include a gate stack on a frontside surface of the substrate or may be subsequently processed to include a gate stack on the frontside surface. Next, a liner material layer is formed in the cavity, and a metal barrier layer may be formed over the liner material layer. Subsequently, the cavity is filled with a thermally conductive material forming a through silicon via. The through silicon via may be formed in an area that is expected to experience heat in the operation of the gate stack.
Still other aspects, features, and technical effects will be readily apparent to those skilled in this art from the following detailed description, wherein preferred embodiments are shown and described, simply by way of illustration of the best mode contemplated. The disclosure is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
Adverting to
Next, cavities 201 are formed extending into the substrate 100 from the backside surface 101a, as illustrated in
The cavities 201 may be formed without being aligned with any gate stack and/or logic device that may be on the frontside surface 101b of the substrate 100. Alternatively, the cavities 201 may be formed to be in alignment with any gate stack and/or logic device that may be on the frontside surface 101b of the substrate 100. As a further alternative, although the cavities 201 may not be in alignment with any gate stack and/or logic device on the frontside surface 101b of the substrate 100, the placement of the cavities 201 may be concentrated at an area where heat generation from the gate stacks and/or logic devices on the frontside surface 101b is the highest.
As illustrated in
Adverting to
Subsequently, the cavities 201 are filled with a thermally conductive material 501, as illustrated in
As illustrated in
The embodiments of the present disclosure achieve several technical effects, including improved cooling efficiency of semiconductor devices. Embodiments of the present disclosure enjoy utility in various industrial applications as, for example, microprocessors, smart phones, mobile phones, cellular handsets, set-top boxes, DVD recorders and players, automotive navigation, printers and peripherals, networking and telecom equipment, gaming systems, and digital cameras. The present disclosure therefore enjoys industrial applicability in any of various types of highly integrated semiconductor devices.
In the preceding description, the present disclosure is described with reference to specifically exemplary embodiments thereof. It will, however, be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the present disclosure, as set forth in the claims. The specification and drawings are, accordingly, to be regarded as illustrative and not as restrictive. It is understood that the present disclosure is capable of using various other combinations and embodiments and is capable of any changes or modifications within the scope of the inventive concept as expressed herein.
