This application claims priority to Taiwan Application Serial Number 96132100, filed Aug. 29, 2007, which is herein incorporated by reference.
1. Field of Invention
The present invention relates to semiconductor manufacturing technology. More particularly, the present invention relates to a method for forming micro-patterns on a semiconductor device
2. Description of Related Art
In general, the smallest feature size that photo-lithography technique can define is limited by the wave-length and the coherence of the light source. Before the next generation patterning equipment being developed and commercialized, integrated circuit (IC) manufacturers have tried to break the limit by playing with processing tricks for making finer structures. These techniques could be classified into two groups: double-exposure or spacer patterning technology.
An object of the present invention is to provide a method for forming micro-patterns smaller than the feature size that photo-lithography processes can define by double-etching the masking material so as to duplicate the line density.
In accordance with the foregoing and other objectives, the present invention provides a method for forming micro-patterns, comprising forming a sacrificial layer and a masking layer on a substrate, and then double etching of the sacrificial layer dedicated to shortening the line width so as to get the smallest feature size.
In a preferred embodiment of the present invention, the method for forming micro-patterns comprises:
forming a sacrificial layer and a masking layer on a substrate, and then forming a patterned masking layer and a patterned photoresist layer on the sacrificial layer;
using the patterned masking layer and the patterned photoresist layer as a mask to etch the sacrificial layer so as to form a first taper trench;
filling a photoresist layer in the first taper trench, and then using the photoresist layer as a mask to etch the sacrificial layer so as to form a second taper trench; and
stripping the photoresist layer, and etching the masking layer via the first taper trench and the second taper trench so as to form a patterned masking layer.
As embodied and broadly described herein, the invention provides a method for forming micro-patterns which has the following advantages:
Original equipment for manufacturing processes do not need to be changed, and processing tricks to duplicate the line density increases the integration of components on the wafer
It is to be understood that both the foregoing general description and the following detailed description are by examples, and are intended to provide further explanation of the invention as claimed.
These and other features, aspects, and advantages of the present invention will become better understood with regard to the following description, appended claims, and accompanying drawings where:
It is to be understood that the following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples.
This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. Moreover, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed interposing the first and second features, such that the first and second features may not be in direct contact.
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A stack layer 210 is formed on the substrate 200. The stack layer 210 comprises a first masking layer 213, a second masking layer 212 and a sacrificial layer 214. The sacrificial layer 214 and the first masking layer 213 have an etch selectivity ratio and are respectively selected from two of polysilicon, silicon oxide, silicon nitride or nitride. The sacrificial layer 214 and the second masking layer 212 have an etch selectivity ratio and are respectively selected from two of polysilicon, silicon oxide, silicon nitride or nitride. In the present embodiment, the sequence of forming the stack layer 210 is described as followed. The first masking layer 213 is formed on the substrate 200, preferably by deposition. The sacrificial layer 214 is formed on the first masking layer 213, preferably by deposition. The second masking layer 212 is formed on the sacrificial layer 214, preferably by deposition.
In the present embodiment, the first masking layer 213 and the second masking layer 212 are respectively a nitride layer, preferably silicon nitride (SiN). The sacrificial layer 214 is an oxide layer, preferably silicon dioxide (SiO2).
A photoresist layer 220 is formed on the stack layer 210, preferably with spin coating. The photoresist layer 220 is made of a usual material, such as positive photoresist or negative photresist.
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In the follow-up manufacturing process, the patterned first masking layer 213′ is used as a mask after the second patterned sacrificial layer 214″ is stripped so as to perform the later manufacturing process.
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In Step 810 a substrate is provided. The provided substrate comprises forming a stack layer on the substrate. The stack layer is formed by depositing a first masking layer on the substrate, forming a sacrificial layer on the first masking layer, and depositing a second masking layer on the sacrificial layer.
In Step 820 a patterned second masking layer and a patterned photoresist layer are formed. A pattern on a mask (e.g., a photomask or reticle) is transferred to the photoresist layer, and then the photoresist layer is etched to form a patterned photoresist layer. Then the patterned photoresist layer is used as a mask to etch the second masking layer so as to form a patterned second masking layer.
In Step 830 the first taper trenches are formed. The patterned photoresist layer and patterned second masking layer are used as a hard mask. Etching the sacrificial layer is performed to form the first taper trenches in the second masking layer and the sacrificial layer of the stack layer. And then, the patterned photoresist layer is removed so as to form a first patterned sacrificial layer.
In Step 840 the photoresist is spin coated, wherein comprises etching back the photoresist. The photoresist fills in the first taper trench and then etches back the photoresist.
In Step 850 the patterned second masking layer is stripped to expose the part of the first patterned sacrificial layer.
In Step 860 the second taper trenches are formed. The exposed first patterned sacrificial layer is etched to form the second taper trenches in the first patterned sacrificial layer.
In Step 870 the patterned first masking layer is formed. Stripping the photoresist filled in the first taper trench and using the second patterned sacrificial layer as a mask to etch the first masking layer so as to form the patterned first masking layer.
In the present embodiment, providing a method of duplicate the line density by double etching the sacrificial layer to produce a hard mask which line width is narrowed so as to get the smallest feature size.
It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.
Number | Date | Country | Kind |
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96132100 | Aug 2007 | TW | national |