Priority to Korean patent application number 10-2007-0140860, filed on Dec. 28, 2007, which is incorporated by reference in its entirety, is claimed.
The present invention relates to a method for forming a pattern of a semiconductor device using a Spacer Patterning Technology (SPT).
As a pattern size is reduced due to the high-integration of semiconductor devices, various approaches have been made in equipment and processes to obtain a fine pattern. For example, an exposure wavelength is reduced, and a size of lens is increased in order to obtain a fine pattern.
The above-described methods requires development of equipment which increases cost, so that there is a difficulty in the management of equipment.
Another method for forming a fine pattern of high-integration using conventional equipment includes a double exposure technology using two exposure masks and a Spacer Patterning Technology (SPT) using three exposure masks.
a to 1d are cross-sectional diagrams illustrating a conventional method for forming a pattern of a semiconductor device.
Referring to
An anti-reflection film 140 and a photoresist pattern 150 having a line shape are formed over the hard mask layer 130 of a cell region I. The underlying layer 110 includes an amorphous carbon layer 103 and a nitride film 105.
Referring to
The sacrificial film 120 is etched with the hard mask pattern as a mask to obtain a sacrificial pattern 120a. The hard mask pattern is removed.
A spacer 155 is formed at sidewalls of the sacrificial pattern 120a.
The spacer 155 includes a polysilicon layer and a nitride film.
Referring to
A second photoresist pattern 160 for forming a pad is formed over the underlying layer 110 of a peripheral circuit region (II).
The underlying layer 110 is etched with the spacer 155 and the second photoresist pattern 160 as a mask to form an underlying pattern 110a.
Referring to
A third photoresist pattern (not shown) is formed which is used to expose the line end of the underlying pattern 110a.
The third photoresist pattern is a cutting mask for separating the underlying pattern part formed by the spacer of the line end region generated from deposition of a spacer material layer.
A part of the underlying pattern 110a disposed at the line end is removed with the third photoresist pattern as a mask to separate each line, thereby removing the third photoresist pattern.
a to 2c are photographs illustrating patterns formed by a conventional method.
a shows a photograph after a spacer 155 remains. There are spaces A1 and B1 between spacers 155.
b shows a photograph after a nitride film 105 is etched with the spacer 155 as a mask. There are spaces A2 and B2 between hard mask patterns.
Referring to
In the above-described conventional method for forming a pattern of a semiconductor device, the hard mask layer and the underlying layer are etched with the horn-shaped spacer as a mask. As a result, the uniformity of the critical dimension (CD) of the final pattern is degraded, so that it is difficult to control the CD.
Various embodiments of the present invention relate to a method for forming a pattern of a semiconductor device that comprises forming a spacer including an oxide film in a SPT process and removing the spacer formed to have a horn shape before etching an underlying layer, so that the horn shape is not transcribed in a lower portion, thereby facilitating CD control in etching the underlying layer so as to improve a characteristic of the device.
According to an embodiment of the present invention, a method for forming a pattern of a semiconductor device comprises: forming an underlying layer and a hard mask layer over a semiconductor substrate; forming a sacrificial pattern over the hard mask layer; forming a spacer at both sides of the sacrificial pattern; removing the sacrificial pattern to remain the spacer; etching the hard mask layer with the spacer as a mask to form a hard mask pattern; removing the spacer; and etching the underlying layer with the hard mask pattern as a mask.
The underlying layer includes one selected from the group consisting of an amorphous carbon layer, a nitride film and combinations thereof. The hard mask layer includes a polysilicon layer. The sacrificial pattern includes one selected from the group consisting of an amorphous carbon layer, a spin on carbon (SOC) layer and combinations thereof. The sacrificial pattern is formed to have a line/space shape, and the ratio of line:space is 1:3. The removing-the-sacrificial-pattern step is performed with O2 plasma.
The forming-a-spacer step includes: depositing an oxide film over the resulting structure including the sacrificial pattern; and performing an etch-back process to form a spacer at both sides of the sacrificial pattern. The oxide film is deposited at a temperature ranging from 100 to 200° C. The removing-the-spacer step is performed by a wet dip-out process using a buffer oxide etchant (BOE) solution.
a to 1d are cross-sectional diagrams illustrating a conventional method for forming a pattern of a semiconductor device.
a to 2c are photographs illustrating patterns formed by a conventional method.
a to 3g are cross-sectional diagrams illustrating a method for forming a pattern of a semiconductor device according to an embodiment of the present invention.
a to 3g are cross-sectional diagrams illustrating a method for forming a pattern of a semiconductor device according to an embodiment of the present invention.
Referring to
The underlying layer 310 includes an amorphous carbon layer 303 and a nitride film 305. The hard mask layer 320 includes a polysilicon layer.
The sacrificial film 330 may include an amorphous carbon layer, a spin on carbon (SOC) layer and combinations thereof.
A first photoresist pattern 340 is formed over the sacrificial film 330 of the cell region (I). The first photoresist pattern 340 includes a line and a space and the ratio of line to space is 1:3. The first photoresist pattern 340 has a thickness ranging from 800 to 1200 Å.
Since the thickness of the first photoresist pattern 340 is thin, a silicon oxide nitride (SiON) film, a multi function hard mask and combinations thereof can be formed under the first photoresist pattern 340.
Referring to
Referring to
A second photoresist pattern (not shown) is formed which Is covers the regions of the semiconductor substrate where the spacer 350 is not formed. The second photoresist pattern (not shown) is a cutting mask for separating the spacer part of the line end region generated from deposition of a spacer material layer.
A part of the spacer 350 disposed at the line end is removed with the second photoresist pattern (not shown) as a mask to separate each line, thereby removing the second photoresist pattern.
Referring to
The spacer 350 is removed. The spacer 350 includes an oxide film material, which can be removed by a wet dip-out process.
The dip-out process may be performed using a buffer oxide etchant (BOE) solution. The polysilicon layer and a low-pressure (LP) nitride film formed under the spacer 350 are not etched by the BOE solution.
Referring to
Referring to
After the spacer remains, the lower hard mask layer is etched with the spacer as a mask to form the hard mask pattern. After the spacer is removed, the underlying layer is etched with the hard mask pattern as a mask, thereby preventing CD non-uniformity of patterns generated when the lower layer is etched with the horn-shaped spacer.
The above embodiments of the present invention are illustrative and not limitative. Various alternatives and equivalents are possible. The invention is not limited by the type of deposition, etching polishing, and patterning steps describe herein. Nor is the invention limited to any specific type of semiconductor device. For example, the present invention may be implemented in a dynamic random access memory (DRAM) device or non volatile memory device. Other additions, subtractions, or modifications are obvious in view of the present disclosure and are intended to fall within the scope of the appended claims.
Number | Date | Country | Kind |
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10-2007-0140860 | Dec 2007 | KR | national |