Patent Application
20150325585
1. Field of Invention
This invention relates to a semiconductor process and a product formed thereby, and particularly relates to a method for forming a three-dimensional (3D) memory, and a 3D memory formed with the method.
2. Description of Related Art
As the demand for storage subsystems of electronic products is increased, the standard for the read/write speeds or capacities of products is higher, so high-capacity related products have become the mainstream in the industry. Therefore, 3D memory, especially 3D vertical-gate (VG) NAND flash memory, has been developed recently.
In a conventional 3D memory process, a stacked structure including alternately arranged semiconductor layers and insulating layers is formed and patterned into linear stacks in a row direction, a blanket charge trapping layer is formed over the resultant, and then a conductive layer is formed filling in between the linear stacks and patterned in a column direction into a 2D array of vertical word lines between the linear stacks.
However, since the gaps between the linear stacks have a high aspect ratio, the patterning etching of the conductive layer deep in the gaps is difficult. Therefore, the conventional VG NAND memory easily suffers from serious word-line bridging issue.
In view of the foregoing, this invention provides a method for forming a 3D memory, which is capable of preventing bridging of vertical word-lines.
This invention also provides a 3D memory formed with the same method.
The method for forming a 3D memory of this invention is described below. A stacked structure, which includes a plurality of semiconductor layers and a plurality of insulating layers arranged alternately, is formed on a substrate. The stacked structure is patterned into a plurality of linear stacks in a row direction, wherein each linear stack includes a plurality of channel layers and a plurality of linear insulators arranged alternately, the channel layers are defined from the semiconductor layers, and the linear insulators are defined from the insulating layers. An insulating material is filled in between the linear stacks. A plurality of damascene openings is formed in the insulating material between each two neighboring linear stacks, wherein each damascene opening exposes a portion of each of the opposite sidewalls of all the channel layers of two neighboring linear stacks. A charge trapping layer is formed. A plurality of word lines is formed in the damascene openings.
In an embodiment of the above method, a linear hard mask part is left on each linear stack, a plurality of column-direction trenches contiguous with the damascene opening is formed through the row-direction linear hard mask parts during the definition of the damascene opening, and then the trenches are also filled by the same material of the word lines, in the step of forming the word lines, to form a plurality of interconnect lines each connected with a column of word lines.
In another embodiment, after the word lines are formed, a plurality of contact plugs and a plurality of interconnect lines in a column direction are formed over the word lines, wherein each interconnect line is electrically connected with a column of word lines via a column of contact plugs.
In an embodiment, the charge trapping layer is formed in the damascene openings after the damascene openings are formed but before the word lines are formed. In another embodiment, the charge trapping layer is formed after the stacked structure is patterned into the linear stacks but before the insulating material is filled in between the linear stacks.
The 3D memory of this invention includes a plurality of linear stacks in a row direction, an insulating material between the linear stacks, a charge trapping layer and a plurality of word lines. Each linear stack includes a plurality of channel layers and a plurality of linear insulators arranged alternately. The insulating material has therein a plurality of damascene openings between each two neighboring linear stacks, wherein each damascene opening exposes a portion of each of the opposite sidewalls of all the channel layers of two neighboring linear stacks. The charge trapping layer is disposed on all sidewalls of each of the damascene openings. The word lines are disposed in the damascene openings, separated from the linear stacks by the charge trapping layer.
Because the word lines are formed in the damascene openings in the method for forming a 3D memory of this invention, word-line bridging can be prevented in the 3D memory of this invention formed with the above method.
In order to make the aforementioned and other objects, features and advantages of this invention comprehensible, a preferred embodiment accompanied with figures is described in detail below.
This invention is further explained with the following embodiments, which are not intended to limit the scope thereof. For example, although the stacked structure includes four semiconductor layers to form four levels of memory cells in the following embodiments, the stacked structure may alternatively include two, three or more than four semiconductor layers to form two, three or more than four levels of memory cells in other embodiments.
Referring to
Referring to
Referring to
Each damascene opening 26 exposes a portion of each of the opposite sidewalls of all the channel layers 16a of two neighboring linear stacks 12a. Each trench 24 is contiguous with a column of damascene openings 26. Such dual damascene structure may result from an etching recipe that makes the etching rate of the insulting material 20 several times higher than the etching rate of the hard mask layer 18. In addition, the photoresist lines 22 may be all consumed in the anisotropic etching, or a residue of the photoresist lines 22 is stripped away after the anisotropic etching is finished.
Referring to
Though the interconnect lines for the word lines are formed simultaneously with the word lines in a dual damascene process in the first embodiment, it is possible to form the interconnect lines and the word lines in two steps alternatively, as described in the following second embodiment.
The formations and/or materials of the stacked structure 12, the hard mask layer 18, the linear stacks 12a, the insulating material 20, the trenches 24, the damascene openings 26 and so on are as described above and as illustrated in
Referring to
Referring to
In addition, although in the above embodiments the charge trapping layer (28) is formed in the damascene openings (26) after the damascene openings (26) are formed but before the word lines (30b) are formed, in other embodiments, the charge trapping layer may alternatively be formed after the stacked structure (12) is patterned into the linear stacks (12a) but before the insulating material (20) is filled in between the linear stacks (12a). This is illustrated in
Referring to
After the charge trapping layer 28′ and the insulating material 20 are formed, the trenches 24, the damascene openings 26, the interconnect lines 30a and the word lines 30b (
Because the word lines are formed in the damascene openings in the methods for forming a 3D memory of the above embodiments of this invention, word-line bridging can be prevented in the 3D memory of the above embodiments formed with the above methods.
This invention has been disclosed above in the preferred embodiments, but is not limited to those. It is known to persons skilled in the art that some modifications and innovations may be made without departing from the spirit and scope of this invention. Hence, the scope of this invention should be defined by the following claims.
