Claims
- 1. A method for in situ electrical testing of a flip-chip semiconductor assembly during its manufacture, the method comprising:
providing one or more integrated circuit (IC) dice, each with a surface having interconnection bumps thereon; providing a substrate with conductive pads deposited on a surface thereof for flip-chip attachment to the interconnection bumps of the one or more IC dice; providing an in situ electrical test socket for connection to the substrate; inserting the substrate into the in situ electrical test socket; positioning the one or more IC dice on the surface of the substrate with the interconnection bumps of the one or more IC dice in conductive contact with the conductive pads of the substrate to form the flip-chip semiconductor assembly; while the substrate is inserted into the in situ electrical test socket and the one or more IC dice are positioned on the surface of the substrate, and before sealing of the one or more IC dice, electrically testing the flip-chip semiconductor assembly using the in situ electrical test socket; repairing the flip-chip semiconductor assembly if it fails the electrical testing; and sealing the one or more IC dice of the flip-chip semiconductor assembly.
- 2. The method of claim 1, wherein providing one or more IC dice comprises providing one or more IC dice selected from a group comprising Dynamic Random Access Memory (DRAM) IC dice, Static RAM (SRAM) IC dice, Synchronous DRAM (SDRAM) IC dice, microprocessor IC dice, Application-Specific IC (ASIC) dice and Digital Signal Processor (DSP) dice.
- 3. The method of claim 1, wherein providing one or more IC dice, each with a surface having interconnection bumps thereon, comprises providing one or more IC dice, each with a surface having interconnection bumps made from solder thereon.
- 4. The method of claim 1, wherein providing a substrate comprises providing a printed circuit board (PCB).
- 5. The method of claim 1, wherein the interconnection bumps comprise a material selected from the group consisting of heat-snap-curable epoxy, radiation-curable epoxy and moisture-curable epoxy.
- 6. The method of claim 1, further comprising speed grading the one or more IC dice.
- 7. The method of claim 6, wherein speed grading is performed after the electrical testing the flip-chip semiconductor assembly.
- 8. The method of claim 1, wherein repairing the flip-chip semiconductor assembly includes at least one of:
removing and replacing at least one of the one or more IC dice; repairing one or more of the interconnection bumps on the one or more IC dice; and repairing at least one of the conductive pads on the surface of the substrate.
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a divisional of application Ser. No. 10/721,110, filed Nov. 24, 2003, pending, which is a divisional of application Ser. No. 10/338,530, filed Jan. 8, 2003, pending, which is a divisional of application Ser. No. 09/819,472, filed Mar. 28, 2001, now U.S. Pat. No. 6,545,498, issued Apr. 8, 2003, which is a divisional of application Ser. No. 09/166,369, filed Oct. 5, 1998, now U.S. Pat. No. 6,329,832, issued Dec. 11, 2001.
Divisions (4)
|
Number |
Date |
Country |
Parent |
10721110 |
Nov 2003 |
US |
Child |
10900602 |
Jul 2004 |
US |
Parent |
10338530 |
Jan 2003 |
US |
Child |
10721110 |
Nov 2003 |
US |
Parent |
09819472 |
Mar 2001 |
US |
Child |
10338530 |
Jan 2003 |
US |
Parent |
09166369 |
Oct 1998 |
US |
Child |
09819472 |
Mar 2001 |
US |