In the design layout of integrated circuits (ICs) a library of reference cell descriptions is maintained in a computer database, each cell description including a circuit layout for a cell typically having from 2 to 50 transistor gates. The circuit designer places these cells and plans out connective lines. A particular reference cell may be used in many different locations in an IC layout, each such location being referred to as an “instance” of the reference cell.
After the circuit designers complete a circuit layout, the design is sent to a fabrication facility where mask data preparation engineers run an optical proximity correction (OPC) engine, which computes a mask layout that is aimed at producing the circuit layout that has been designed. Unfortunately, due to resource constraints the OPC engine will typically not design the masking system so that all instances of a particular cell will be uniform when fabricated in silicon.
Moreover, even if the OPC created a mask that would theoretically produce exactly uniform instances of a cell, variations in the manufacturing process and instance contexts would create non-uniformities between the electrical performance characteristics of one cell instance and another. These non-uniformities greatly complicate the task of computing actual cell performance for parameters such as timing, thereby necessitating the use of wider performance guard bands to ensure that all the circuit elements can properly work together. But the use of wider timing guard bands, for example, reduces potential circuit performance as it means that some circuit elements will have their timing slowed down to avoid a timing glitch, due to the difficulty in determining what timing relationships are required between cells.
Moreover, the OPC engine is executed on the circuit layout as a whole and there is no check on the fidelity of any particular post-OPC cell to the library cell upon which it is based. There is also typically no effort to understand how variations introduced by OPC and/or fabrication affects performance on the cell electrical level or to correct or prevent this variation on the cell level. Also, the library cells with which the process begins are designed without IC layout knowledge, so they are not optimized to result in cell instance uniformity in the finished product.
Although efforts have been made to analyze timing differences added by differences between instances of the same cell in an IC, and to subtract out these differences, this has proven to be difficult to accomplish. It appears that some further step is needed to more tightly predict timing and other performance parameters, so that guard bands can be tightened and IC performance boosted.
The present invention includes a method of making instances of a reference cell more uniform across an integrated circuit (IC) by providing a nominal cell for the reference cell and, after an initial Optical Proximal Correction engine run, modifying a subsequent OPC engine run, to force the cell instances to more closely conform to the nominal cell, during an IC layout process.
Other features of the present invention will be apparent from the accompanying drawings and from the detailed description that follows.
Exemplary embodiments are illustrated in the drawings. It is intended that the embodiments and figures disclosed herein are to be considered illustrative rather than restrictive.
For ease of presentation, a relatively detailed preferred embodiment will be presented first, with reference to
Generalized block 14 represents the derivation of a nominal cell from a reference cell. There are many ways of deriving a nominal cell from its reference cell, based on the expected applications and the performance criteria being used. Generally speaking, a nominal cell is chosen such that it represents an optimized version of its reference cell, that is most likely to yield a properly functioning cell under a probable range of manufacturing process and design context variations. In other words, a nominal cell represents the true “performance center” of a given reference cell under variations. Therefore, using nominal cells in design analysis and optimization allows the designer to full exploit available design margins under variations. This benefit can be observed with the illustrations in
There are three main categories of variations that can be considered in the derivation of nominal cells: (neighboring) context, process variations and measured/characterized performance corners. Below we describe three embodiments of nominal cell derivation considering each of the three variations. Note however that variations considered in nominal cell derivation may not be limited to the above-mentioned categories. Moreover, multiple categories of variations may be considered simultaneously during nominal cell derivation. Lastly, based on whether the design criterion is a worst-case one, a nominal cell may be chosen to represent the worst-case performance (instead of the nominal performance) of a given reference cell under variations.
First, we illustrate how to derive a nominal cell from a reference considering variations introduced via different (neighboring) context surrounding instances of the reference. As noted above, each cell has a set of gates, and in the nominal cell each gate is described in terms of an effective length and width (Leff and Weff). Leff and Weff define a theoretical rectangular gate. The OPC engine will return a masking system adapted to produce gates that approximate an aspect of the electrical performance that would be yielded by the theoretical rectangular gates. In this specific example a context is chosen for the reference cell (block 16), which in this case will be a typical set of circuitry that surrounds the typical cell instance in the IC layout. The cell, together with its context, is input into an OPC engine (block 18), which outputs a descriptor set for a masking system, adapted to fabricate the cell in silicon. Alternatively, a nominal cell can be empirically determined by averaging values of Leff and Weff under all contexts of a set of given representative designs.
This, in turn, may be used as input to a lithography simulation program, which outputs a shape for each gate. This gate shape is typically not a simple rectangle, so Leff and Weff for a particular gate will typically not be immediately apparent from an examination of the lithography simulation output. To find Leff and Weff it is typical to execute a shape-to-electrical simulation, which accepts the cell having the specific gate shapes output by the lithography simulation program and outputs an approximation of the electrical characteristics of the set of gates of the nominal circuit (block 22). The Leff and Weff are then computed, from the electrical characteristics, for each gate of the nominal cell (block 24). A nominal cell has now been derived.
Second, referring to
Third, referring to
Turning now to the right hand side of
Returning to the method of the preferred embodiment, for each cell instance (for the cells corresponding to the nominal cell derived in block 14) an evaluation is performed (block 32) according to an evaluation method that may parallel the method by which the nominal cell was derived. In the detailed case of
These are used to derive Leff and Weff for each gate (block 38). In the computation of Leff and Weff, Leff may be held constant, or Weff may be held constant, or both may be allowed to vary, depending on the constraints imposed by cell geometry. In some instances, it may be possible to set Leff and Weff to yield identical electrical characteristics, in cases where Leff and Weff of the nominal cell cannot be matched, due to context constraints for the cell instance.
At this point in the process, a nominal cell exists in which each gate is defined in terms of its Leff and Weff and a cell instance from the IC layout has been described in terms, for each gate, of Leff and Weff. Each gate of the cell instance is now compared to each gate of the nominal cell, with the differences being noted (block 50). These differences are compared to a threshold (decision box 52) to determine if the cell instance is close enough to the nominal cell so that the process may be brought to an end. If it is not, the OPC engine is run again, but with some modifications that are designed to force the cell instance (after further simulation or experimental fabrication) to have Leff and Weff values that are closer to those of the nominal cell.
One modification that can be made to the running of the OPC engine is that input for the IC can be manipulated in the region of the cell instance, with the OPC input Leff and Weff for each out-of-tolerance gate being adjusted in a manner intended to yield a closer simulation output Leff and Weff on the next iteration (block 54). These changes can be implemented via annotation layers of the IC layout input to the OPC engine. In another method of modifying an OPC engine run, the lithography model or the OPC recipe that forms a part of the OPC engine can be modified in a manner anticipated to bring about a closer result. Also, the modifications could be encoded into text, fields that accompany the annotation layers of the IC layout description. In another alternative, information embedded in the computer data structure (resident in memory) used by the OPC engine could be modified to effect a modified OPC run. Also, a cell variant could be substituted for the original cell, for one or more instances. Variants may be classified, with a particular variant used in one situation, and another variant used in another. In addition, the layout could be modified by modifying individual cell instances or by modifying a group of cell instances, together.
After the above discussed process has been performed for each cell instance, a modified OPC engine run is performed, and the process is iterated (starting with block 34) until each Leff and Weff is within tolerance.
Returning to the nominal cell side of
If the circuit designer knows the performance of a set of cell instances to a finer specificity, he may design the circuit with faster timing than would otherwise be possible. Knowing ahead of time that the cell instances will be forced to match the characteristics of the nominal cell, the circuit designer can design a circuit differently, taking advantage of the more specific knowledge of cell instance performance.
Referring to
The evaluation method of block 32 typically parallels the evaluation method used in the derivation of the nominal cells, choices for which are listed in the second column of Table I. Table II shows level to which IC fabrication is simulated or characterized by experiment, or the effect that is taken into account in the fabricated IC. This level or effect is the level or effect to which cell instances are made uniform.
With respect to block 60, in a preferred embodiment the performance characteristics for the nominal cell are derived in terms of both mean and variation. Table III describes some methods used to evaluate these quantities. This is a necessary step in achieving the more accurate circuit analysis afforded by the use of nominal cells.
In an alternative preferred embodiment the temperature differences that occur during operation of the IC under a defined set of conditions is taken into account in the computation of Leff and Weff for the cell instance gates. In an additional alternative embodiment, voltage drop across a cell is taken into account in the computation of Leff and Weff.
Neighboring cell instances may be grouped together in practicing the method of a preferred embodiment, to increase efficiency.
In an alternative preferred embodiment more than one nominal reference cell is made for a library reference cell. In some cases it is advantages to use a first nominal reference first cell when a first cell is being fabricated into a first portion of the circuit and a second nominal reference first cell when a first cell is being fabricated into a second portion of the circuit, particularly when it would be impossible or impractical to fabricate the first nominal reference first cell in the second portion of the circuit.
In one preferred embodiment, critical timing paths are first determined by way of a static timing engine. Then, those cell instances that lie along a critical timing path are normalized as described above, to tighten up the timing along the critical paths. In another preferred embodiment, all cell instances are normalized. In yet another preferred embodiment cell instances to be normalized are picked by the circuit designer by way of a heuristic process.
It is a great advantage of the process, that for those cell instances that have been normalized according to this process, timing characteristics can be known to a much greater accuracy than had heretofore been generally possible. Although the normalization of cell instances does not take away every variation from cell performance, it can serve to greatly increase the knowledge of how a cell will perform.
It should be specifically noted that although in the preferred embodiments described in this application, a set of nominal cells, distinct from the library reference cells, are created, this step of creating distinct nominal cells is not an essential part of the process. This is because in an alternative preferred embodiment the library reference cells are used as the nominal cells, without any further derivation.
While a number of exemplary aspects and embodiments have been discussed above, those of skill in the art will recognize certain modifications, permutations, additions and sub-combinations thereof. It is therefore intended that the following appended claims and claims hereafter introduced are interpreted to include all such modifications, permutations, additions and sub-combinations as are within their true spirit and scope.