Patent Application
20090079004
This invention relates to the domain of integrated circuits and more particularly transistors, and its purpose is to describe a microelectronic device provided with at least one double gate structure for a transistor. In particular, the invention uses an improved method for making double gate transistors.
A classical transistor structure is usually formed on a substrate, for example of the SOI (Silicon on Insulator) type, a source region and a drain region, for example in the form of a first conducting zone and a second conducting zone respectively, joined together through a third semiconductor structure that will act as one channel or several channels in which a current will circulate, and that may be in the form of a block or a bar, or possibly several separate semiconducting bars. This or these semiconducting bars are covered by a semiconducting or metallic gate that can be used to control the intensity of a current passing through the channel, or possibly in the channels between the source region and the drain region.
In particular, new transistor gates structures have appeared so as to improve control over channel conduction. These new structures include the so-called double-gate structure that is formed from a first layer of gate material located under a semiconducting zone of the transistor channel, and a second layer of gate material located on the semiconducting transistor channel zone.
Document WO 03/075355 A1 presents a method for making a double gate structure including the formation of a dummy double-gate structure formed from a dummy gate pattern based on an insulating material, and another dummy gate pattern based on insulating material, then removal of said insulating material and replacement of this material by a gate dielectric and then by a gate material. The steps to deposit the gate dielectric and the gate material make the manufacture of gates with the same dimensions in the double gate structure difficult. Furthermore, with such a method, the gates of the double gate structure are formed from the same material.
The document by Lee J-H., Taraschi G., Wei A., Langdo T. A., Fitzgerald E. A., Antoniadis D. A., “Super Self-Aligned Double-Gate (SSDG) MOSFETs Utilizing Oxidation Rate Difference and Selective Epitaxy”, IEDM pp. 71-74>> presents a method for the formation of a double gate structure for a transistor, comprising the formation of a stack on a substrate provided with a first layer of gate material, a first layer of gate dielectric, a semiconducting layer in which the channel is to be made, a second layer of gate dielectric and a second layer of gate material. The stack is then etched through a mask to form the double gate patterns. A differential oxidation is then applied to make spacers, between the gate patterns for example made of polysilicon and the channel semiconducting zone for example made of silicon, followed by controlled deoxidation to expose the channel semiconducting zone. This method includes a high temperature oxidation step that could degrade the gate materials. Furthermore, it is difficult to deoxidize the channel semiconducting zone without removing the oxide from spacers formed on each side of the gates.
Document WO 03/103035 also discloses a method for making a double gate structure for a transistor. In particular, this method includes a step to form a first gate that will be called the <<lower>> gate in a layer of gate material in a stack also comprising a semiconducting layer in which a channel will be formed, a second layer of gate material, and an insulating layer; a step to form a channel zone in the semiconducting layer and a pattern in the insulating layer, using the lower gate as a mask. This method also includes bonding-turning over supports, followed by removal of said pattern formed in the insulating layer, and replacement by a gate material. This method also includes a step to selectively eliminate a silicon layer stopping on an undoped polysilicon layer, that is difficult to implement.
Document U.S. Pat. No. 6,365,465 presents a method for making a double gate structure for a transistor including the formation of a suspended channel structure, for example made of silicon, between source and drain zones, followed by photolithography to define the upper and lower gates of a double gate structure. With this method, the critical dimensions of the lower gate and the upper gate are different, the size of the lower gate being equal to the space between the source and the drain minus twice the thickness of the gate insulation, while the size of the upper gate is equal to the size of the gate lithography level. The transistor structure obtained using such a method includes source and drain zones isolated from the gates only by the gate dielectric, and it is then impossible to form spacers. With such a method, it is also difficult to reduce the gate patterns and obtain small critical dimensions.
Document JP-A-2001-102590 discloses a method for making a gate structure for a transistor including formation of a first gate vertically in line with a channel semiconducting zone by photolithography, and then production of an upper gate using a second photolithography operation. The disadvantages of this approach are that two different sized gates are formed, making alignment of said two gates difficult, particularly when the critical dimensions become very small, for example less than 20 nm.
Document FR 2 829 294 also discloses a method for making a double gate structure for a transistor and a plurality of spacers, particularly to protect the upper gate when the channel is being etched, to protect the channel when the lower gate is being etched, and to isolate the lower gate from the source and drain regions. The sizes of the upper and lower gates made using such a method are different.
The problem that arises is to find a new method for making a double gate structure for a transistor, that does not have the disadvantages mentioned above.
The purpose of this invention is to present a microelectronic device comprising at least one transistor provided with a double gate structure comprising a first gate or <<lower gate>> located under a channel zone of the transistor, a second gate or <<upper gate>> located on a channel zone of the transistor, first gate and second gate having respective critical dimensions equal or substantially equal similar to or lower than the critical dimensions of the channel. Critical dimensions <<approximately equal to>> or <<similar to>> means dimensions that are not different by more than two nanometers. The term <<critical dimension>> or <<minimum dimension>> as used throughout this description means the minimum dimension of a geometric pattern made in a thin layer, apart from the dimension(s) defined by the thickness of this thin layer.
The invention relates to a method for making a microelectronic device provided with at least one double gate structure for a transistor, including the following steps:
a) formation of at least one stack comprising at least one first layer of gate material (s), at least one first gate dielectric layer supported on the first layer of gate material(s), at least one semiconducting zone supported on said first gate dielectric layer, at least one second gate dielectric layer supported on said semiconducting zone and on said first gate dielectric layer, and at least one second layer of gate material(s) supported on said second gate dielectric layer,
b) etching, for example anisotropic etching, of said stack through a mask, so as to make at least one first structure facing the semiconducting zone, comprising a so-called <<channel>> semiconducting zone formed from said etched semiconducting zone, at least one first pattern of a first gate formed from the first etched layer of gate material, and at least one second pattern of a second gate formed from the second etched layer of gate material,
c) etching, for example isotropic etching, of at least part of the first pattern and at least part of the second pattern, selectively with regard to the channel semiconducting zone.
Isotropic etching in step c) is done to reduce the first gate pattern and the second gate pattern. After step b), the first pattern of the first gate, the second pattern of the second gate and the semiconducting zone formed have equal or approximately equal critical dimensions. After step c), the first pattern of the first gate, the second pattern of the second gate have critical dimensions less than the corresponding critical dimensions of the channel semiconducting zone.
In one variant, said first layer of gate materials may be formed from a stack of several sub layers of different materials.
Said stack may for example comprise at least one material that can be selectively etched with respect to the semiconducting zone and at least one other material chosen for its electricity conducting properties. This makes it possible to form gate patterns with critical dimensions smaller than the channel semiconducting zone, while having good control over the gate.
According to one possible embodiment, said second layer of gate materials may be formed from a stack of several sub layers of different materials.
According to one variant in which said first layer of gate materials is formed from a first stack of several sub layers of different materials and the second layer of gate materials is formed from a second stack of several sub layers of different materials, the first stack may be different from the second stack and/or may comprise at least one material different from the material from which the first stack is formed. In the case in which the first stack is formed from one or several materials different from the materials in the second stack, a lower gate and an upper gate can be formed with different electrical characteristics while having a critical dimension less than the critical dimension of the channel semiconducting zone.
According to another variant, the first stack and the second stack may be formed from the same materials but have different arrangements. The first stack and the second stack may be formed from a stack of two layers called the <<first bilayer>> and another stack of two layers called a <<second bilayer>> respectively, the second bilayer being formed from the same materials as the first bilayer but with a different arrangement from the arrangement of the first bilayer.
The first layer of gate material(s) and/or the second layer of gate material(s) may comprise at least one semiconducting material.
According to one variant, isotropic etching in step c) may include at least one dry etching step of said semiconducting material using a plasma.
According to one particular embodiment, said semiconducting material may be polySiGe.
The first layer of gate material(s) and/or the second layer of gate materials may include at least one sub layer based on at least one metallic material.
For example, the metallic material may be chosen from among Ti, TiN, W, WN, Ta, TaN.
According to one variant, isotropic etching in step c) may include at least one wet etching step using an SC2 type solution (SC2 stands for <<standard clean 2>>) based on HCl+H2O2+H2O of said sub layer(s) based on metallic material.
According to one variant, said semiconducting zone may be based on silicon.
The anisotropic etching step b) may also comprise manufacturing of at least one second structure facing a zone or in a zone of the stack in which the second gate dielectric layer is supported on the first gate dielectric layer, the second structure comprising at least a third pattern joined to said first pattern, and formed from the first etched layer of gate material(s) and at least one fourth pattern joined to said second pattern, and formed from the second etched layer of gate material(s), the third pattern and the fourth pattern being separated by gate dielectric layers. Said second structure is joined to the first structure and may be used to act as zones for making contact for the first gate and for the second gate.
The method according to the invention may also comprise manufacturing of at least one first metallic contact in contact with said third pattern on said second structure without being in contact with said fourth pattern, for example after making the source and drain zones, and at least one second metallic contact in contact with the fourth pattern without being in contact with said third pattern.
The method may possibly also include the formation of insulating blocks or insulating spacers after step c), on each side of the first pattern of the first gate and on each side of the second pattern of the second gate.
Manufacturing of said insulating spacers may possibly include the following steps:
After step c), the method may also include the formation of at least one first zone that will act as the source region in contact with the channel semiconducting zone, and at least one second zone that will act as the drain region in contact with the channel semiconducting zone.
According to one variant, formation of said first zone and said second zone may include epitaxial growth of semiconducting blocks on the sides of the channel semiconducting zone. In this case, the semiconducting blocks may advantageously be based on a semiconducting material different from the semiconducting material(s) in the channel semiconducting zone.
According to a second variant, formation of said first source region zone and said second drain region zone may include the following steps:
According to a third variant, formation of said first source region zone and said second drain region zone may include the following steps:
Formation of said stack in step a) may include the following steps:
The invention also relates to a microelectronic device comprising:
According to one variant, the first stack may have an arrangement different from that of the second stack and/or may comprise at least one material different from the material in the first stack.
The first stack and/or the second stack may be formed from at least one semiconducting sub layer. The first stack and/or the second stack may also be formed from at least one metallic sub layer.
According to one variant embodiment, the first stack may be formed from a first metallic sub layer supported on a first semiconducting sub layer, and the second stack of a second semiconducting sub layer supported on a second metallic sub layer respectively, the composition of the first semiconducting sub layer being identical to the composition of the second semiconducting sub layer, and the composition of the first metallic sub layer being different from the composition of the second metallic sub layer.
The microelectronic device may also comprise at least one first zone that can form a transistor source region, at least one second zone that can act as a transistor drain region, the first zone and the second zone comprising at least a first semiconducting block and at least one second semiconducting block each formed by epitaxy on the channel semiconducting zone.
According to one variant, the microelectronic device may also comprise at least one first zone that can form one transistor source region, at least one second zone that can form a transistor drain region, the first zone and the second zone each comprising at least one first metallic block and at least one second metallic block in contact with said channel semiconducting zone.
According to another variant, the microelectronic device may also comprise at least one first zone that can form a transistor source region, at least one second zone that can form a transistor drain region, the first zone and the second zone comprising at least one first semiconducting block formed by epitaxy on the channel semiconducting zone, and at least one first metallic block in contact with said first semiconducting block respectively, the second zone comprising at least one semiconducting block formed by epitaxy on the channel semiconducting zone, and at least one second metallic block in contact with said second semiconducting block.
The microelectronic device according to the invention may also comprise insulating spacers on each side of the first pattern of the first gate and on each side of the second pattern of the second gate.
The microelectronic device according to the invention may also comprise at least one second contact making structure on the first gate and the second gate, the second structure being joined to said first structure and comprising:
The device according to the invention may also comprise at least one first metallic contact in contact with said third pattern without being in contact with said fourth pattern, and at least one second metallic contact in contact with the fourth pattern, without being in contact with said third pattern. Such contacts may be used to make a first gate pattern and a second gate pattern polarized independently. In other words, said first contact and said second contact may be useful for producing an upper gate and a second lower gate pattern with different polarizations.
This invention will be better understood after reading the description of example embodiments given purely for guidance and in no way limitatively, with reference to the appended figures, wherein:
FIGS. 7 and 8A-8C illustrate a variant embodiment of source and drain zones for a double gate transistor used according to the invention,
Identical, similar or equivalent parts of the different figures have the same numeric references so as to facilitate comparison between the various figures.
The different parts shown on the figures are not necessarily shown at the same scale, to make the figures more easily understandable.
An example method according to the invention for making a microelectronic device provided with at least one double gate structure for a transistor will now be given with reference to
For example, the initial material may be a substrate that may be of the semiconductor on insulator type, for example an SOI (silicon on insulator) substrate or a germanium on insulator (GeOI) substrate or an SiGe on insulator (SiGeOI) substrate. The substrate may include a layer 101 that will be called the <<first support>>, for example based on a semiconducting material such as silicon on which an insulating layer 102 is supported, for example a buried oxide layer based on SiO2, itself covered with a semiconducting layer 104. The semiconducting layer 104 may for example be based on silicon, or germanium or SiGe (
A step to thin this semiconducting layer 104 may then be made for example by oxidation of the semiconducting material of layer 104 so as to form a thickness 105 of semiconducting oxide, then by removal of this oxide thickness 105, for example by HF. For example, the thinned semiconducting layer 104 may be between 5 and 10 nanometers thick (
A dielectric gate layer 107 is then deposited that will be called the <<first gate dielectric layer>>. The dielectric layer 107 may for example be between 1 and 5 nanometers thick and may for example be formed from a so-called high dielectric constant material or high-k material, for example made of HfO2 or Al2O3.
A layer 108 of gate material is then deposited that will be called the <<first gate material layer>>. The gate material used to form the layer 108 was chosen so that it can be selectively etched with respect to the semiconducting layer 104. The first layer of gate material may for example be formed from a semiconducting material such as polySiGe, particularly in the case in which the semiconducting layer is based on Si (
The next step is to form another insulating layer 111 called the <<bonding>> layer, for example based on SiO2, on the first layer 108 of gate material (
The next step is to remove the first support 101, for example using polishing and then chemical etching based on TMAH, and at least part of the thickness of the insulating layer 102, for example using HF. According to one variant embodiment, the bonding interface 113 between the insulating layer 111 and the insulating layer of the second support may for example be located at not less than 300 or 350 or 400 nanometers from layer 108 (
The next step is to make a mask on the insulating layer 102 and above or facing the semiconducting layer 104, comprising at least one pattern of the active transistor zone. For example, this mask may be formed by deposition of a resin layer 115 on the remaining thickness of the insulating layer 102, and then formation of the active zone pattern in the resin layer 115 (
The next step is to etch the semiconducting layer 104 and the insulating layer 102 through the mask, so as to reproduce the pattern of the active zone in this layer 104. The etched semiconducting layer will be referenced 104a and will be called the <<semiconducting zone>>. A transistor channel will be made in at least part of this semiconducting zone 104a. Anisotropic etching, for example dry plasma etching based on Cl2 (+O2) or HBr (+O2) may be done through said resin mask 115, to the level of the first gate dielectric layer 107, to form the semiconducting zone 104a.
The mask 115 and the insulating layer 102 are then removed. The device formed then comprises at least one semiconducting zone 104a on the surface and at least one so-called <<insulation>> zone formed by the first gate dielectric layer 107 (
The next step is to deposit another insulating layer 127 called the <<second gate dielectric layer>> on the semiconducting zone 104a and on the dielectric layer 107. The next step is to deposit a layer of gate material that will be called the <<second gate material layer>>. The second layer 128 of gate material may for example comprise a semiconducting material. The gate material used to form the second layer 128 of gate material was chosen so that it can be etched selectively with respect to the semiconducting layer 104. For example, in a case in which the semiconducting zone 104a is based on silicon, the second layer 128 of gate material may for example be based on polySiGe. According to one variant embodiment, the first layer 108 of gate material and the second layer 128 of gate material may have exactly the same composition and/or be based on the same material. The first layer 108 of gate material and the second layer 128 of gate material may also have equal or approximately equal thicknesses. The next step is to form another mask layer 130 on the second layer 128 of gate material (
The next step is etching through patterns 132 and 134 of the mask layer in a stack comprising the second layer 128 of gate material, the second gate dielectric layer 127, the semiconducting zone 104a, the first gate dielectric layer 107, the first layer 108 of gate material. Etching of said stack is done so as to reproduce the form of said patterns 132 and 134 in said stack and to expose the insulating support layer 111. Said etching of the stack may be anisotropic etching made for example using plasma etching, for example based on Cl2 (+O2) or HBr+(O2) or BCl3.
The etched semiconducting zone 104a will now be called the channel semiconducting zone and will be referenced 104b. This channel semiconducting zone reproduces the form or the design of the first gate pattern 132. After the stack has been etched, a first structure 140 was formed comprising patterns 108a, 128a of a double gate under and on the channel semiconducting zone 104b respectively. A second structure 142 joined to the first structure 140 and reproducing the second pattern of contact making zones was also formed and includes patterns 108b, 128b based on the first layer 108 of gate material, and the second layer 128 of gate material respectively, separated by zones derived from the dielectric layers 107 and 127 (
The next step is to etch the patterns 108a, 128a, 108b, 128b of gate material under the masking patterns 132 and 134, selectively with regard to the channel semiconducting zone 104b. This etching may be isotropic etching, for example dry etching done using plasma. For example, a CF4 based plasma may be used. This isotropic etching may be used to laterally reduce the patterns 108a, 108b, 128a, 128b, or to reduce the critical dimension of the double gate patterns 108a, 128a, and patterns 108b and 128b of the second structure 142.
After this isotropic etching, the critical dimensions d1 of patterns 108a, 128a, 108b, 128b are equal to or approximately equal to each other (the critical dimension being a dimension measured along a direction parallel to the direction defined by a vector {right arrow over (i)} in the orthogonal coordinate system [O; {right arrow over (i)}; {right arrow over (j)}; {right arrow over (k)}]). The critical dimension d1 of the etched patterns 108a, 128a, 108b, 128b is less than the critical dimension dc of the channel zone 104a (the critical dimension of the active zone dc being a dimension measured along a direction parallel to the direction defined by a vector {right arrow over (i)} of the orthogonal coordinate system [O; {right arrow over (i)}; {right arrow over (j)}; {right arrow over (k)}]). Selective etching of patterns 108a, 128a, 108b, 128b with regard to the semiconducting zone 104a also provides a means of forming cavities 143 on each side of the patterns 108a, 128a, 108b, 128b (
The next step can then be to dope the ends also called <<extensions>> of the semiconducting zone 104b. The <<ends>> of the semiconducting zone 104b means regions of this semiconducting zone 104b that are not located between the patterns 108a and 128a of the double gate and that project beyond the patterns 108a and 128a of the double gate. For example, the extensions may be doped using at least one implantation. This implantation may be done at a non-zero angle with a normal to the principal plane of the insulating layer 111 (the principal plane of the insulating layer being defined by a plane passing through this layer 111 and parallel to the plane [O; {right arrow over (i)}; {right arrow over (k)}] on
The next step (
These spacers 148 may be made firstly by deposition, for example a conforming deposition, of a thin layer, for example of the order of 5 nanometers thick based on a first insulating material 145, for example SiO2, and then by deposition, for example a conforming deposition, of a second insulating material 146 for example made of Si3N4, on the structures 140 and 142. The thickness of the second deposited insulating material 146 is chosen so as to fill in the cavities 143. The thickness of the second deposited insulating material 146 may be chosen to be greater than or equal to half the depth of the cavities 143 (the cavity depth 143 being a dimension defined in a direction parallel to the vector {right arrow over (j)} in the orthogonal coordinate system [O; {right arrow over (i)}; {right arrow over (j)}; {right arrow over (k)}] on
The second insulating material 146 can then be anisotropically etched, for example using an HBr based plasma. The next step is to partly remove the first insulating material 145, so as to expose the channel semiconducting zone 104b. For example, this removal can be done by etching using hydrofluoric acid. After these etching operations, insulating zones 148 based on the second insulating material 146 and the first insulating material 145 are formed in said cavities 143, on each side of the patterns 108a, 128a, 108b, 128b (
The next step is to form source and drain regions on each side of the channel semiconducting zone 104b, on the sides of this semiconducting zone 104b.
This can be done firstly by depositing a thin layer (or <<liner>>) that may be insulating, for example based on SiO2 and of the order of several nanometers thick, for example 5 nanometers thick, and then another insulating layer called the <<stop layer>> (not referenced), for example based on Si3N4 and of the order of several nanometers thick, for example 30 nanometers thick, so as to form a layer 152 that may be insulating and conforming, on the insulating layer 111 and on the structures 140 and 142 (
The next step is to form a thick layer 154 that may be insulating and for example based on SiO2, of the order of a hundred nanometers thick, for example 300 nanometers thick. The thickness of the layer 154 is chosen so as to be at least equal to or greater than the height of the second structure 142, so as to cover this structure (the height of the structure being a dimension measured along a direction parallel to the vector {right arrow over (j)} in the orthogonal coordinate system [O; {right arrow over (i)}; {right arrow over (j)}; {right arrow over (k)}]). If the thickness of the layer 154 is greater than the height of the first structure 140, the thickness of the layer 154 above the structures 140 and 142 can be reduced to the insulating thickness 152 covering the top of the first structure 140, for example using a CMP (<<Chemical Mechanical Polishing>>) step stopping on the layer 152 and particularly on the Si3N4 based stop layer (
In the next step (
Before the source and the drain blocks are made, conducting zones can be formed in a part of the ends of the semiconducting zone 104b. To achieve this, part of the ends of the semiconducting zone 104b can be silicided. This siliciding can improve future contacts firstly between a future source region and the channel semiconducting zone 104b, and secondly between a future drain region and the channel semiconducting zone 104b. Siliciding may for example comprise a nickel deposit on the exposed parts of the channel structure 104b, followed by a siliciding annealing, then selective removal of unconsumed Ni so as to form NiSi based zones 158 at part of the ends of the semiconducting zone 104b (
The next step is to form metallic blocks 164, 166, on each side of the first structure 140 that will act as source region and drain region. This can be done by making one or several depositions of metallic materials in the cavities 156, 157. Formation of the blocks 164, 166 may include deposition of a thin layer of metal 160, for example TiN, then deposition of another metal layer 161, for example based on W, or WSi, on each side of the first structure 140.
In one case (
The second structure may be used as contact making zones to polarize the double gate. The method may also comprise manufacture of at least one first contact 181 on part of the third pattern 108b formed from the first layer 108 of gate material, and at least one second contact 182 on part of said fourth pattern 128b formed from the second layer 128 of gate material on the second structure, for example after the source and drain semiconducting zones have been manufactured, the first contact 181 not being joined to or in contact with the fourth pattern 128b, the second contact 182 not being joined to or in contact with the third pattern 108b (
One variant of the example method described above will now be given with reference to
The next step is partial etching of the gate patterns 208a, 228a and particularly patterns 208a, 228a based on the second bilayer material 238. This etching may be an isotropic etching, for example dry etching done using a CF4 based plasma (
The next step is to do another etching of another part of the patterns 208a, 228a, and particularly another part of the patterns 208a, 228a based on a first bilayer material 237. This etching may be isotropic etching, for example wet etching, for example using SC2 etching (
As described for the previous example method, the next step could be to dope the extensions. Insulating spacers 148 can then be formed on each side of the patterns 208a, 228a so as to insulate the double gate from future source and drain regions. These spacers 148 may be made as described previously with reference to
According to one variant of the example method that has just been described with reference to
Another variant of the example method described above with reference to
Said first stack of the first layer 308 of gate materials may comprise a sub layer based on a first gate material 337. The first gate material 337 may be chosen for its electricity conducting properties. The first gate material 337 may for example be a metal such as Ti or TiN or W or WN or Ta or TaN. The other sub layer may be based on a second gate material 338 that can be selectively etched with respect to the material of the semiconducting layer 104. The second gate material 338 may for example be a semiconducting material, for example polySiGe, particularly in the case in which the semiconducting zone 104a is based on silicon. In the first layer 308 of gate materials, the arrangement of the material bilayers 337, 338 may be such that the first gate material 337 is in contact with the first gate dielectric 107, while the second gate material 338 is supported on the insulating support layer 111. Said second stack of the second layer 328 of gate materials may comprise a sub layer based on the third gate material 339. The third gate material 339 may be chosen for its electricity conducting properties and for example may be a metal different from the first metal 337, for example chosen from among the Ti, TiN, W, WN, Ta, TaN materials. The other sub layer of the second stack may be based on the second gate material 338 that can be selectively etched with respect to the material from which the semiconducting layer 104 is made. The second gate material 338 may for example be a semiconducting material, for example polySiGe in the case in which the semiconducting zone 104a is based on silicon. In the second layer 328 of gate materials, the arrangement of the bilayer of materials 339, 338 may be such that the third gate material 339 is supported on the second gate dielectric 127, while the second gate material 338 is supported on the third gate material 339.
The next step is partial etching of the second material 338 of the bilayers, so as to reduce the parts of the gate patterns 308a, 328a that are based on the second dielectric material 338. This etching may be dry etching, for example done using a CF4 plasma (
The next step is a second partial etching of the first material 337 and the third gate material 339, so as to reduce the parts of the pattern 308a that are based on the first material 337 and to reduce the parts of the pattern 328a that are based on the second material 339. For example, this etching may be done using SC2 (
The next step may be to complete the formation of a double gate transistor, particularly by forming insulating spacers on each side of the patterns 308a, 328a of the double gate, and then possibly siliciding the channel semiconducting zone 104b, then forming source and drain blocks, for example metallic blocks, in contact with the channel structure, for example as described above with reference to
One variant formation of source and drain blocks for a double gate transistor comprising a double gate structure will now be described. This variant describes the formation of a device, for example like that described above with reference to
The next step is to form semiconducting blocks 462 and 464 on each side of the first structure 140, at the ends of the channel semiconducting zone 104b. These semiconducting blocks 462, 464 may be formed by epitaxial growth on the edges or ends of the channel semiconducting zone 104b and will be used to form a source region and a drain region respectively, or a region that will belong to a future source or drain region respectively. According to a first variant, the semiconducting blocks 462, 464 may be formed based on the same semiconducting material as the channel semiconducting zone 104b, for example Si in the case in which the channel semiconducting zone 104b is based on Si (
According to one advantageous embodiment, the semiconducting blocks 462, 464 may be formed based on a semiconducting material 468 different from the material used in the channel semiconducting zone 104b, for example Ge or SiGe, particularly in the case in which the channel semiconducting zone 104b is based on Si (
| Number | Date | Country | Kind |
|---|---|---|---|
| 05 53510 | Nov 2005 | FR | national |
