Claims
- 1. A method for making a thin film load device for completing non-programmable interconnections in a memory device, comprising:
- providing a substrate having a first electrically conductive feature;
- forming an insulating layer over said first electrically conductive feature;
- providing a conductive via through said insulating layer in electrically conductive contact with said first electrically conductive feature;
- depositing an amorphous silicon material having a resistivity of at least 1.times.10.sup.4 ohms over and in electrically conductive contact with said conductive via;
- forming a second electrically conductive feature over and in electrically conductive contact with said amorphous silicon material; and
- interconnecting the first electrically conductive feature to a first node of the memory device and the second electrically conductive feature to a second node of the memory device, and said amorphous silicon material provides a non-programmable resistive load between said first and second electrically conductive features.
- 2. A method for making a thin film load device as recited in claim 1, wherein said amorphous silicon material is formed using an antifuse fabrication process.
- 3. A method for making a thin film load device as recited in claim 1, wherein said amorphous silicon material is deposited and patterned to form a resistive pad that overlies said conductive via.
- 4. A method for making a thin film load device as recited in claim 3, wherein said resistive pad has a thickness of between about 200 .ANG. and 2,000 .ANG. when said conductive via have a diameter of between about 2,000 .ANG. and about 20,000 .ANG..
- 5. A method for making a thin film load device as recited in claim 3, wherein said resistive pad has a thickness of between about 500 .ANG. and 1,200 .ANG. when said conductive via has a diameter of between about 3,000 .ANG. and about 6,000 .ANG..
- 6. A method for making a thin film load device as recited in claim 1, wherein said conductive via includes a thin glue layer and a tungsten fill.
- 7. A method for making a thin film load device as recited in claim 6, wherein said thin glue layer is selected from the group consisting of titanium tungsten, tantalum nitride, titanium-tungsten-nitride and tungsten nitride.
- 8. A method for making a thin film load device as recited in claim 1, wherein said amorphous silicon material is deposited using a plasma enhanced chemical vapor deposition process carried out at a temperature of between about 150.degree. C. and 600.degree. C., and a pressure of between about 0.5 and 10 Torr.
- 9. A method for making a thin film load device as recited in claim 8, wherein said plasma enhanced chemical vapor deposition process is carried out at a power of between about 100 and 2,000 watts.
- 10. A method for making a thin film load structure for use in a memory device, comprising:
- forming a first electrically conductive feature over a substrate;
- forming an insulating layer over said first electrically conductive feature;
- forming a conductive via having a diameter of between about 3,000 .ANG. and about 6,000 .ANG. through said insulating layer in electrically conductive contact with said first electrically conductive feature;
- depositing an amorphous silicon material using a combination of a silane gas (SiH.sub.4), a nitrogen gas (N.sub.2), and an argon gas (Ar), until a thickness between about 500 .ANG. and 1,200 .ANG. is formed to produce a resistivity of at least 1.times.10.sup.4 ohms over and in electrically conductive contact with said conductive via;
- forming a second electrically conductive feature over and in electrically conductive contact with said amorphous silicon material; and
- interconnecting the first electrically conductive feature to a first node of the memory device and the second electrically conductive feature to a second node of the memory device, such that said amorphous silicon material provides a non-programmable resistive load between said first and second electrically conductive features.
- 11. A method for making a thin film load structure as recited in claim 1, wherein the memory device is an SRAM cell having the first node electrically connected to a passgate transistor and having the second node electrically connected to a power supply.
- 12. A method for making a thin film load structure as recited in claim 11, wherein the non-programmable resistive load defines a pull-up device of the SRAM cell.
- 13. A method for making a thin film load structure as recited in claim 10, wherein the amorphous silicon material is deposited using a plasma enhanced chemical vapor deposition process carried out at a temperature of between about 150.degree. C. and 600.degree. C., and a pressure of between about 0.5 and 10 Torr.
- 14. A method for making a thin film load structure as recited in claim 13, wherein said plasma enhanced chemical vapor deposition process is carried out at a power of between about 100 and 2,000 watts.
- 15. A method for making an SRAM cell having a pair of pull-up thin film load devices, the method comprising:
- forming a first pull-up thin film load device between a first node and a second node, including,
- forming a first electrically conductive feature;
- forming an insulating layer over said first electrically conductive feature;
- forming a conductive via having a diameter of between about 3,000 .ANG. and about 6,000 .ANG. through said insulating layer in electrically conductive contact with said first electrically conductive feature;
- depositing an amorphous silicon material having a thickness between about 500 .ANG. and 1,200 .ANG. to produce a resistivity of at least 1.times.10.sup.4 ohms over and in electrically conductive contact with said conductive via;
- forming a second electrically conductive feature over and in electrically conductive contact with said amorphous silicon material; and
- interconnecting the first electrically conductive feature to the first node of the first pull-up thin film load device and the second electrically conductive feature to the second node of the first pull-up thin film load device.
- 16. A method for making an SRAM cell having a pair of pull-up thin film load devices as recited in claim 15, further comprising:
- forming a second pull-up thin film load device between a third node and the second node, including,
- forming a third electrically conductive feature;
- forming an insulating layer over said third electrically conductive feature;
- forming a conductive via having a diameter of between about 3,000 .ANG. and about 6,000 .ANG. through said insulating layer in electrically conductive contact with said third electrically conductive feature;
- depositing an amorphous silicon material having a thickness between about 500 .ANG. and 1,200 .ANG. to produce a resistivity of at least 1.times.10.sup.4 ohms over and in electrically conductive contact with said conductive via;
- forming a fourth electrically conductive feature over and in electrically conductive contact with said amorphous silicon material; and
- interconnecting the third electrically conductive feature to the third node of the second pull-up thin film load device and the fourth electrically conductive feature to the second node of the first pull-up thin film load device.
- 17. A method for making an SRAM cell having a pair of pull-up thin film load devices as recited in claim 16, wherein the first node is connected to a first passgate transistor, the third node is connected to a second passgate transistor, and the second node is connected to a power supply.
- 18. A method for making an SRAM cell having a pair of pull-up thin film load devices as recited in claim 17, wherein the first pull-up thin film load device and the second pull-up thin film device are non-programmable devices implemented in non-antifuse applications.
- 19. A method for making an SRAM cell having a pair of pull-up thin film load devices as recited in claim 15, wherein the depositing of the amorphous silicon material includes:
- implementing a deposition gas combination of a silane gas (SiH.sub.4), a nitrogen gas (N.sub.2), and an argon gas (Ar).
- 20. A method for making an SRAM cell having a pair of pull-up thin film load devices as recited in claim 16, wherein the depositing of the amorphous silicon material includes:
- implementing a deposition gas combination of a silane gas (SiH.sub.4), a nitrogen gas (N.sub.2), and an argon gas (Ar).
- 21. A method for making a thin film load structure for use in a memory device, comprising:
- forming a first electrically conductive feature over a substrate;
- forming an insulating layer over said first electrically conductive feature;
- forming a conductive via having a diameter of between about 3,000 .ANG. and about 6,000 .ANG. through said insulating layer in electrically conductive contact with said first electrically conductive feature;
- depositing an amorphous silicon material using a combination of a silane gas (SiH.sub.4), a nitrogen gas (N.sub.2), and an argon gas (Ar), until a thickness between about 500 .ANG. and 1,200 .ANG. is formed to produce a resistivity of at least 1.times.10.sup.4 ohms over and in electrically conductive contact with said conductive via,
- forming a second electrically conductive feature over and in electrically conductive contact with said amorphous silicon material; and
- interconnecting the first electrically conductive feature to a first node of the memory device and the second electrically conductive feature to a second node of the memory device, such that said amorphous silicon material provides a non-programmable resistive load between said first and second electrically conductive feature;
- wherein the memory device is an SRAM cell having the first node that electrically connects to a passgate transistor and having the second node that electrically connects to a power supply.
- 22. A method for making a thin film load structure as recited in claim 21, wherein the non-programmable resistive load defines a pull-up device of the SRAM cell.
Parent Case Info
This is a Divisional application of prior application Ser. No. 08/723,007 filed on Sep. 30, 1996, now U.S. Pat. No. 5,764,563.
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Divisions (1)
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Number |
Date |
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Parent |
723007 |
Sep 1996 |
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