Claims
- 1. A capacitor comprised of:
- a semiconductor substrate having devices formed therein;
- a first insulating layer;
- a first conducting layer on said first insulating layer patterned to provide a capacitor bottom electrode;
- a capacitor dielectric layer on said capacitor bottom electrode;
- a second conducting layer patterned to provide a capacitor top electrode on said capacitor dielectric layer over said capacitor bottom electrode;
- a second insulating layer having an array of via holes distributed over and extending to said capacitor top electrode and said second insulating layer having recesses for a third conducting layer;
- conductive plugs formed in said array of via holes; and,
- a third conducting layer in said recesses in said second insulating layer and electrically contacting said conductive plugs, said third conducting layer in said recesses forming conductive regions over said capacitor providing electrical contacts through said conductive plugs to said capacitor top electrode.
- 2. The capacitor of claim 1, wherein said third conducting layer is formed of metal.
- 3. The capacitor of claim 1, wherein said conducting plugs and said third conducting layer are formed of the same metal.
- 4. The capacitor of claim 1, wherein said conducting plugs and said third conducting layer are formed of different metals.
- 5. The capacitor of claim 1, wherein said first and said second insulating layers are planar.
- 6. The capacitor of claim 1, wherein said capacitor is a decoupling capacitor.
- 7. The capacitor of claim 1, wherein said capacitor forms part of an analog/logic integrated circuits.
Parent Case Info
This is a division of patent application Ser. No. 09/044,761, filing date Mar. 20, 1998 U.S. Pat. No. 5,946,567, A Method For Making Metal Capacitors For Deep Submicrometer Processes For Semiconductor Integrated Circuits, assigned to the same assignee as the present invention.
US Referenced Citations (7)
Divisions (1)
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Number |
Date |
Country |
Parent |
044761 |
Mar 1998 |
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