Claims
- 1. A method for controlling stack memory comprising the steps of:a) providing a system memory coupled to a processor; b) providing a stack memory coupled to said processor, said stack memory constructed and arranged to store values of a program counter; c) providing a stack pointer coupled to said stack memory, said stack pointer comprising: a master latch, said master latch storing a next unutilized address location in said stack memory device; a slave latch coupled to said master latch, said slave latch constructed and arranged to update said master latch; an increment/decrement circuit coupled to said master latch and further coupled to an input of said slave latch, said increment/decrement circuit constructed and arranged to determine a preceding address location to said next unutilized address location; a selection circuit coupled to said stack memory device, to said master latch and to said increment/decrement circuit; d) decoding an instruction at an address retained by said program counter; e) providing a call instruction whereby said address in said program counter is written to said stack memory; f) reading a memory location from said system memory; g) executing an operation of an instruction with said processor to obtain a result; and h) writing said result into a memory location on said system memory.
- 2. The method in accordance with claim 1 wherein said step f) further comprises the step of decrementing a stack pointer address.
- 3. The method in accordance with claim 1 wherein said step f) further comprising the step of selecting an address from the group consisting of said stack pointer address and a decremented stack pointer address.
- 4. The method in accordance with claim 1 wherein said step h) further comprises the step of providing a return instruction wherein a previously stored program counter address is read from said stack memory.
- 5. The method in accordance with claim 4 wherein said step f) further comprises the step of decrementing a stack pointer address.
- 6. The method in accordance with claim 5 further comprising the step of selecting an address from the group consisting of said stack pointer address and said decremented stack pointer address.
Parent Case Info
This application is a division of application Ser. No. 08/958,939, filed Oct. 28, 1997, now U.S. Pat. No. 5,958,939.
US Referenced Citations (4)