Patent Application
20230339745
The present invention relates to a method for manufacturing a micromechanical sensor. The present invention further relates to a micromechanical sensor.
In surface micromechanics (SMM), there is invariably the requirement of having to remove sacrificial layers from under large-surface areas. If these areas are unable to be structured in such a way as to be extensively permeated by an etching medium in order, for example, to be able to keep paths for removing a sacrificial layer short, a sacrificial layer must be etched starting from the outermost edges of the area/of the structure. This requires a very long etching time, which may result in higher costs. For this reason, there are various approaches for implementing in a targeted manner channels in the area of a sacrificial layer, with the aid of which the etching medium may be rapidly distributed in the area and as a result significantly shorter etching times may be implemented.
It is an object of the present invention to provide an improved method for manufacturing a micromechanical sensor.
The object may achieved according to one first aspect of the present invention. In accordance with an example embodiment of the present invention, the method for manufacturing a micromechanical sensor include the following steps:
In this way, a sensing area is provided on a carrier structure, which is mechanically decoupled or separated from the underlying substrate, for example, from a silicon substrate (Si substrate) and is connected on the front side at only a few points to the Si substrate. This allows for the creation of a stress-decoupled sensing area with the aid of a sacrificial oxide removed in a large area. A spacing between a carrier structure with the sensing area formed thereon and a support structure is advantageously variable via layer thicknesses. As a result, a stress-related decoupled micromechanical sensor may be manufactured in this way. As a result, a sensing area of a micromechanical sensor (which is conventionally produced on a silicon wafer (Si wafer or also Si substrate) without stress decoupling), is produced according to the present invention on the carrier structure. This means that the complete manufacturing process of a sensor is transferred from a Si wafer surface to the surface of a carrier structure, which makes a stress decoupling possible.
According to one second aspect of the present invention, the object may be achieved with a micromechanical sensor. In accordance with an example embodiment of the present invention, the micromechanical sensor includes:
Preferred refinements of the method are disclosed herein.
In one advantageous refinement of the method of the present invention, trenches and/or trench structures are formed in the substrate for removing the oxide sacrificial layers between the carrier structure and the substrate. In this way, structures are provided in the substrate for distributing etching gas, which make it possible to rapidly distribute an etching gas over a large area. In this way, the release of the carrier structure may be achieved in a simple manner.
In one further advantageous refinement of the method of the present invention, support structures in the form of trenches and/or the trench structures in the substrate are filled with a first oxide sacrificial layer and are used in the further manufacturing process for supporting the carrier structure. In this way, it is possible to carry out a subsequently implemented layer structure in an even, low-deformation and mechanically stable manner, as a result of which it is possible to provide large-area carrier structures, below which silicon may be partially or else also extensively removed for producing etching channels.
In one further advantageous refinement of the method of the present invention, the etching process for producing trenches and/or trench structures as etching channels and/or support structures for supporting a carrier structure in the substrate is isotropic or anisotropic in design. The shape of the trenches may be easily manipulated as a result.
In one further advantageous refinement of the method of the present invention, to form the trenches and/or trench structures, a partial removal of the substrate below a first oxide sacrificial layer takes place through the openings in the first oxide sacrificial layer and the openings in the first oxide sacrificial layer are closed by applying a second oxide sacrificial layer. In this way, a further variant for creating the substructure below the carrier structure is provided.
In one further advantageous refinement of the method of to present invention, nubs on the carrier structure oriented toward the substrate and/or nubs formed on the substrate are formed. As a result, a supporting function in the layer structure of the sensor element is implemented on the one hand, on the other hand, this may prevent the carrier structure from “sticking” to the subsurface in the event of shocks (for example, due to electrostatic forces). The nub height may be easily varied by an adjustment of an etching depth.
In one further advantageous refinement of the method of the present invention, pillars are formed on the carrier structure oriented toward the substrate. As a result, an alternative support structure for the carrier structure is provided.
In one further advantageous refinement of the method of the present invention, the pillars are connected to the substrate or are formed spaced apart from the substrate. In the different ways of forming the pillars cited, it is possible to implement different support concepts for the carrier structure.
In one further advantageous refinement of the method of the present invention, a first polysilicon layer having a defined layer thickness is formed on the oxide sacrificial layers.
In one further advantageous refinement of the method of the present invention, a second, fast-growing polysilicon layer having a defined layer thickness is formed on a first polysilicon layer. As a result, a greater/higher total layer thickness for a carrier structure may be advantageously provided in a simple manner.
In one further advantageous refinement of the method of the present invention, an attachment area of the carrier structure is formed at least partially and/or in areas on the substrate in a monocrystalline manner. Circuit components may be advantageously formed in the monocrystalline areas.
In one further advantageous refinement of the method of the present invention, the fact that an attachment area of the carrier structure is formed on the substrate in a polycrystalline manner.
In one further advantageous refinement of the method of the present invention, electrical circuit components, which are attached with strip conductors at the sensing area, are formed in the attachment area. In this way, an electrical attachment of the circuit components at the sensing area may be implemented with strip conductors, which may be guided, for example, via spring structures.
The present invention is described in detail below including further features and advantages with reference to multiple figures. Identical or identically functioning elements have the same reference numerals. The figures are intended, in particular, to illustrate the main features of the present invention and are not necessarily implemented true to scale. For the sake of better clarity, it may be provided that not all reference numerals are marked in all figures.
A main feature of the present invention is, in particular, to provide in a simple manner a stress-decoupled micromechanical sensor or a sensing area of a micromechanical sensor.
A substrate 1 (Si substrate) is apparent, on which a first oxide sacrificial layer 2 (for example, an SiO2 sacrificial layer) is situated or deposited. Located on first oxide sacrificial layer 2 is a first polysilicon layer 3a (“polysilicon start layer”) including etching channels x1, which extend up to oxide layer 2, on which a second polysilicon layer 3b (epitaxial polysilicon, EPI polySi) has been deposited with the aid of a selective silicon deposition in an EPI reactor. The intended result of a selective silicon deposition is that no silicon grows on an oxide surface during a deposition of polysilicon in an EPI reactor.
As a variant thereto, widened etching channels x2 may optionally also be formed in sacrificial layer 2, as indicated in
In order to avoid this, a first oxide sacrificial layer 2 in one variant of the provided method as represented in
Depending on the spacing of the openings in first oxide sacrificial layer 2, larger as well as laterally expanded and cohesive, silicon-free areas may be produced below first oxide sacrificial layer 2 in the Si substrate when using an isotropic Si etching process. As a result, it is possible, for example, to be able to produce channel structures or trenches 1a with a larger channel cross section, as is apparent in
After removal of the silicon in the area of the openings of first oxide sacrificial layer 2, the closure of the openings takes place with the aid of a second oxide sacrificial layer 6 (for example, with an SiO2 sacrificial layer). If SiO2 is deposited in this case in the structures produced in substrate 1, the former is also removed in a later SiO2 sacrificial layer etching process, as a result of which advantageously no freely movable particles 5 are formed. The maximum width of the openings in first oxide sacrificial layer 2 is decisive in this case for the required minimum thickness of second oxide sacrificial layer 6, which is necessary for a secure closure of the openings in first oxide sacrificial layer 2. The smaller the maximum width of the openings in first oxide sacrificial layer 2 is, the smaller is the minimum required layer thickness of second oxide sacrificial layer 6 that may be selected. A first polysilicon layer 3a, on which a second polysilicon layer 3b may further be deposited, is subsequently deposited onto second oxide sacrificial layer 6, first polysilicon layer 3a being capable of being used as a start layer for growing the second polysilicon layer 3b in an EPI reactor. If the two oxide sacrificial layers 2, 6 are structured prior to the deposition of first and second polysilicon layers 3a, 3b, first polysilicon layer 3a and, optionally, second polysilicon layer 3b may also be deposited on substrate 1 (area A) and form here, for example, fastening points/fastening structures on substrate 1 for the sensing area to be released, as is represented in
If polysilicon layer 3a is structured together with the two oxide sacrificial layers 2, 6, polycrystalline and monocrystalline Si areas D may be simultaneously produced during the epitaxial Si deposition of subsequent silicon layer 3b. The polycrystalline silicon area are formed in this case on first polysilicon layer 3a and monocrystalline areas D on exposed monocrystalline substrate 1, as indicated in
A thickness of second polysilicon layer 3b in this case may be as much as approximately 100 μm and more and may be deposited/grown significantly faster in an EPI reactor than, for example, in an LPCVD process (low pressure chemical vapor deposition). As a result, a stable and torsion-resistant backplane in the form of the carrier structure including polysilicon layers 3a, 3b may thereby be provided for the micromechanical sensor.
A micromechanical component (for example, in the form of a capacitive pressure sensor) may now be produced on the Si-surface thus prepared. In this component, an area is structurally provided, in which monocrystalline silicon may grow epitaxially on the Si substrate (so-called EPI plug area). If this EPI plug area is now positioned in area B on the Si substrate, which has also been formed in a monocrystalline manner, as represented in
Further details regarding the procedural production of sensing area 20 on the carrier structure including polysilicon layers 3a, 3b are not further discussed here, since these process steps are conventional.
If in one of the last processing steps an etching access 8 is now produced within sensing area 20 from the surface into the “channel system” below oxide sacrificial layers 2, 6, a rapid etching over a large area of oxide sacrificial layers 2, 6 may take place below carrier structure 3a, 3b of sensing area 20 via this etching access, as a result of which a cavity 16 is formed below carrier structure 3a, 3b on which sensing area 20 is located.
This is visually represented in
As a result, sensing area 20 has essentially the same lateral dimensions as carrier structure 3a, 3b situated below. One variant, in which sensing area 20 may also have smaller lateral dimensions than carrier structure 3a, 3b located below, is not represented in the figures.
Nubs 9 may be made of polysilicon or from an electrical insulating material, which possess a high etching resistance to the oxide sacrificial layer etching medium and which has been deposited and optionally structured on second oxide sacrificial layer 6 prior to the deposition of polysilicon layer 3a.
The images a) and b) of
In image 12 b), the variant may be seen, in which nub 9 itself is made of an electrically insulating material, which possesses a high etching resistance to the sacrificial layer etching medium. As is apparent in
It is also possible to provide an etch-resistant and electrically insulating layer 4 on nub structures at the substrate surface, which may be produced by targeted structuring of first oxide sacrificial layer 2 and targeted etching of substrate 1, as is shown in image 12 a). In this case, the deposition and structuring of this layer would take place prior to the deposition of first oxide sacrificial layer 2.
In accordance with
After the etching of substrate 1 below carrier structure 3a, 3b on which sensing area 20 is located, the removal of the SiO2 protection and sacrificial layers subsequently takes place with the aid of a gas phase etching process (for example, HF gas phase etching process). So that no etching attack is able to take place here on SiO2 insulation layers between strip conductor planes of the sensing area, a layer made of, for example, silicon and/or silicon-rich silicon nitride, which is etch-resistant to a gas phase etching process, must also be present in an etching access channel 8 behind the walls made of a material 11 etch-resistant to XeF2 such as, for example, SiO2.
Other structures as well, which possess no etch resistance to the etch gas used (for example, HF vapor), should be protected with a corresponding protective layer, these other structures may also be electrical strip conductors, electrically insulated areas or electrical insulation layers. To be able to avoid electrical short circuits in these cases, the protective layer here must be made of an electrically non-conductive material such as, for example, silicon-rich silicon nitride.
The top view and the corresponding cross-sectional views of
It is further apparent that the production of the trench structure takes place in a polycrystalline Si-area C, which encloses carrier structure 3a, 3b and sensing area 20 which, in turn, is surrounded by monocrystalline silicon. Via the one-sided “fixation x5” of carried structure 3a, 3b and of sensing area 20 achieved thereby, it is further possible to feed electrical strip conductors 13 from sensing area 20 to the solid ground and to electrically connect these to integrated circuits and bond pads 14. In one further variant, the area enclosing carrier structure 31, 3b and sensing area 20 may be made completely of polycrystalline silicon or else from a circumferential polycrystalline Si area which, in turn, is surrounded by an area in which the same layer sequence is formed on oxide superficial layers 2, 6 as in carrier structure 3a, 3b and sensing area 20.
The top view of
Polysilicon layers 3a, 3b produced on oxide sacrificial layers 2, 6 serve essentially as a substructure or as a carrier structure for sensors or sensing areas, which are to be/required to be stress-decoupled by an at least partially circumferential trench and by removing oxide sacrificial layers 2, 6 from surrounding substrate 1 and/or from the surrounding layer system. The structure shown has the advantage that it enables both high SiO2 sacrificial oxide etching rates via etching channels in the silicon substrate as well as a stable, deformation-free subsurface and layer structure, which enables without limitations the use of standard semiconductor processes for producing the desired structures. The possibility of being able to provide areas at the chip surface, which are made of monocrystalline silicon, further allows integrated circuits to be able to be provided. In this way, an integrated OMM pressure sensor chip or inertial sensor chip, for example may be implemented, whose sensing area 20 is formed stress-decoupled to the surrounding substrate.
One further variant for manufacturing a micromechanical sensor 100 is explained in greater detail below with reference to
In this way, a trench structure 1b lined with SiO2 may be produced, which is closed at the substrate surface. The cavity thus produced is used for local stress decoupling and prevents the formation of undesirable cracks in substrate 1. The trench structures 1b in this case may have a bottle-like (
After deposition of first sacrificial oxide layer 2 into trench structures 1b and closure of trench structures 1b by first sacrificial oxide layer 2, openings x6 are etched into deposited first oxide sacrificial layer 2 outside filled or closed trench structures 1b, through which the underlying silicon is removed with the aid of an isotropic silicon etching process (for example, XeF2 or isotropic plasma etching step), as indicated in
The SiO2 structures produced in substrate 1 may, when suitably designed, also be used to produce lateral etch stop structures. This has the advantage that the lateral and vertical dimensions of the cavity below the area to be released may be selected or designed independently of one another.
After removal of the silicon through openings x6 in first oxide sacrificial layer 2, openings x6 in first oxide sacrificial layer 2 are closed with the aid of a second oxide sacrificial layer 6. After the closure of openings x6, a first polysilicon layer 3a may further be deposited, which is removed outside the stress decoupled area together with the previously deposited SiO2 layers, as is represented in
If a second silicon layer is now deposited/grown on the surface thus prepared in an epitaxial reactor (EPI reactor), as represented in
If, however, only sacrificial oxide layers 2, 6 are structured and first polysilicon layer 3a is deposited extensively on the entire wafer, as represented in
After implementation of all necessary process steps for implementing sensing area 20, etching accesses 8 may be implemented at one or multiple positions of the surface through the existing layer system to cavity 16, which is located below and pervaded with SiO2 structures. Since the SiO2 layers within cavity 16 are to be removed through these etching channels 8 with the aid of wet-chemical or gaseous etching with HF, it is advantageous to provide etching accesses 8 in regions, in which layers made of silicon and/or materials resistant to HF are located, in order to be able to avoid undesirable or uncontrolled etchings within the layer system, as indicated in
It is further possible to form etching accesses 8 in such a way that a defined separation may be achieved between the area that is to be stress-decoupled and the surrounding region/substrate. In this case, for example, spring-like suspensions or springs 15 may be implemented similarly to the representations in
It is further also possible to provide nubs 9 at the underside and thus the side of the stress-decoupled area or carrier structure 3a, 3b facing substrate 1 including sensing area 20, in order to be able to preferably avoid a potential sticking of this area at substrate 1. To produce the nubs, indentations x7 may be introduced into second oxide sacrificial layer 6 (closure oxide), as represented in
With both variations, it is possible in this way to implement nubs 9 made of polysilicon at the underside of the area to be stress-wise decoupled, as is apparent in
As is graphically indicated in the cross-sectional views of
It is equally possible, as represented in
It is further also possible that the stress-decoupled area is connected via pillar-like structures or pillars 12 of arbitrary shape to substrate 1. The pillar-like structures or pillars 12 are connected here directly to the underside of carrier structure 3a, 3b and to the upper side of substrate 1. The structure of pillar-like structures 12 is comparable to that of the nub structures or nubs 9. The number and position of the pillar-like structures in this case may, as also in the case of the nub structures, be arbitrarily selected and may be adapted to existing requirements. The material of the pillar structures may include silicon, silicon oxide, silicon nitride, silicon-rich silicon nitride, aluminum oxide, silicon carbide or a combination of the mentioned materials. When selecting the material or when selecting the material combinations, it should be noted, however, that the material that comes into contact with the etching medium for removing oxide sacrificial layer 2, 6 exhibits a high etching resistance to the etching medium.
Material of the pillar-like structures may also be located extensively on the underside of stress-decoupled sensing area 20 and, here in particular, on the underside of carrier structure 3a, 3b or may be structured in such a way that it is located only in the area of the pillar-like structures, as indicated in
Several examples of further possible pillar-like structures 12 are represented in
As is apparent in
Since insulating layer 40c as well as the lateral etch stop structures may be designed here to be etch-resistant to a silicon etching process, substrate 1 may be etched using an etching process on which no high demands must be placed, for example, with respect to the anisotropic etching behavior. In order to avoid an uncontrolled lateral etching of insulating layer 40b and thus an undercutting of silicon layer 40c during the later oxide sacrificial layer etching, insulating layer 40b may be structured prior to the deposition/application of silicon layer 40c in such a way that material of silicon layer 40c on monocrystalline silicon substrate 40a is deposited in openings of insulating layer 40b and may thus act as a lateral etch stop. After the deposition of silicon layer 40c, a planarization step may further be carried out for producing a planar surface.
In one alternative variant, an indentation is initially produced in silicon substrate 40a, which is filled with insulating layer 40b. The deposited layer thickness of insulating layer 40b in this case is advantageously selected to be greater than the stripped layer thickness in the indentation of silicon substrate 40a. The surface is subsequently stripped by a planarization step in such a way that insulating layer 40b is located only in the indentations in the silicon substrate and a planar surface is produced. In a subsequent deposition process, silicon layer 40c is deposited onto the planarized surface and islands laterally separated from one another are formed from the material of insulating layer 40c. Areas in which silicon layer 40c comes into contact with silicon substrate 40a may also be used here as a lateral etch boundary.
In one further variant, the islands made of insulating layer 40b separated from one another are formed with the aid of a LOCOS process. By using a planarization step with which the nitride mask may also be removed for producing the local SiO2 areas, it is also possible here to produce a planar surface with SiO2 areas separated from one another. All of the aforementioned examples are understood to be exemplary and may be modified and/or combined in a variety of ways. Furthermore, the elastic structures and the manner of suspension of the sensing area may be arbitrarily selected and adapted to the respective particular application.
The stress-decoupled variants shown are advantageously not limited only to pressure sensors, but may also be used in other, stress-sensitive sensors such as, for example, micromechanical inertial sensors or in temperature sensors. The present invention may advantageously be applied to all types of micromechanical sensors, in which a stress decoupling of the sensing area is to be implemented. By this means, influences on the sensor signal resulting from the assembly and packaging technology (APT) may be reduced or avoided and cost-intensive superstructures for reducing the stress input may be omitted or reduced.
Only rough process steps are cited above. Those skilled in the art may thus draw conclusions about necessary process details based on the disclosure herein and on his/her technical expertise. In or after the described sequences, additional CMP steps may, if necessary, further also be carried out in order to produce surfaces on which further process steps or process sequences are implementable using standard semiconductor methods.
In a step 200, an application of a first oxide-sacrificial layer 2 is carried out on a substrate 1.
In a step 210, a removal of material of substrate 1 through openings x3 in first oxide sacrificial layer 2 is carried out.
In a step 220, a closing of openings X3 in first oxide sacrificial layer 2 is carried out by applying a second oxide sacrificial layer 6.
In a step 230, a formation of a sensing area 20 on a carrier structure 3a, 3b is carried out, the sensing area 20 and carrier structure 3a, 3b being formed on oxide sacrificial layers 2, 6 and sensing area 20 and/or carrier structure 3a, 3b being connected to substrate 1 via at least one attachment area 30, which forms a flexible structure 15.
In a step 240, an at least partial removal of oxide sacrificial layers 2, 6 between carrier structure 3a, 3b and substrate 1 is carried out with the aid of an etching process.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2020 203 906.2 | Mar 2020 | DE | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/EP2021/057209 | 3/22/2021 | WO |
