The present invention relates to a method of fabricating semiconductor devices that involves removing a hard mask material from a semiconductor substrate before depositing an insulating material on it.
The manufacture of semiconductors typically involves fabricating trenches within a semiconductor substrate which electrically isolate various integrated circuits within a single chip or wafer. As the size of technology nodes continues to decrease, significant challenges continue to arise due to issues related to traditional semiconductor fabrication processing techniques, including issues related to lack of planarity or uniformity of isolation trenches between various integrated circuits and to eliminating gaps within insulating material placed within trenches.
In one embodiment, a method is provided. The method includes forming a mask on a surface of a semiconductor substrate; creating one or more isolation trenches within the substrate; removing the mask from the substrate; depositing an insulating material within the trenches that extends above the surface of the substrate; and planarizing the insulating material to form a planar surface that is substantially coplanar with the surface of the substrate.
In another embodiment, a method is provided. The method includes forming a silicon nitride mask on a surface of a semiconductor substrate; creating isolation trenches separated by fins in the substrate; removing the mask from the substrate; depositing an insulating material within and above the trenches and on the fins; planarizing the insulating material by chemical mechanical polishing and stopping on the fins to form a surface that is substantially coplanar with the surface of the fins; and cleaning the surface of the fins.
One or more aspects of the present invention are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings, which are not necessarily drawn to scale, in which:
Aspects of the present invention and certain features, advantages, and details thereof, are explained more fully below with reference to the non-limiting embodiments illustrated in the accompanying drawings. Descriptions of well-known materials, fabrication tools, processing techniques, etc., are omitted so as to not unnecessarily obscure the invention in detail. It should be understood, however, that the detailed description and the specific examples, while indicating embodiments of the invention, are given by way of illustration only, and are not by way of limitation. Various substitutions, modifications, additions and/or arrangements within the spirit and/or scope of the underlying inventive concepts will be apparent to those skilled in the art from this disclosure. Note also that reference is made below to the drawings, which are not drawn to scale for ease of understanding, wherein the same reference numbers used throughout different figures designate the same or similar components.
In one aspect, an early stage of semiconductor fabrication involves formation of isolation trenches within a semiconductor substrate that serve to electrically isolate multiple circuits within a single wafer or chip. For example, isolation trenches may be created in the surface of a semiconductor material, followed by placement of insulating material such as silicon oxide within the isolation trenches. Conventional processes for creating isolation trenches during semiconductor fabrication present several disadvantages. For example, uniformity between isolation trenches is desired but can be difficult to obtain by conventional methods. Furthermore, depositing insulating material in isolation trenches can be complicated by a problem known as gap fill, which may involve the formation of undesirable spaces or gaps within the insulating material deposited in isolation trenches.
Conventionally, recesses in a semiconductor substrate are first created in selected regions of a semiconductor substrate. For example, a hard mask may be directly or indirectly deposited on the semiconductor substrate and then a selective lithographic process may be used to form a pattern in the hard mask to distinguish between where isolation trenches will and will not be made in the underlying substrate. Isolation trenches created in this manner are thereby separated by fins that have hard mask material present on the upper surfaces.
By way of example,
One embodiment of an intermediate process structure 100 obtained during a conventional procedure for semiconductor device manufacture is depicted in
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Thus, following a first chemical-mechanical polish or an etch-back polish step, residual insulating material 114 is then removed from hard mask material 108, as depicted in
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Although not depicted, one skilled in the art would know that additional layers of material may be provided on or within the structure 100 depicted in
As further explained below, the methods disclosed herein in accordance with aspects of the invention address challenges in semiconductor fabrication processing and thereby enhance the use of isolation trenches in advanced technology nodes. In accordance with some aspects of the present invention, some conventional processing steps as described above, including planarization and deglazing, may be eliminated, while surprisingly superior isolation region uniformity results may be provided and complications associated with gap fill may be reduced.
Generally stated, disclosed herein, in one example, is a method which includes: patterning a semiconductor substrate to form a plurality of isolation trenches within the semiconductor substrate separated by fins, the patterning including leaving, at least in part, a protective hard mask atop fins; selectively removing the hard mask material; and providing an insulating material within the plurality of isolation trenches and above the plurality of isolation trenches and fins; and planarizing the insulating material to facilitate fabricating an isolation trench within the semiconductor substrate, and stopping the planarizing on the fins.
In one example, patterning the semiconductor substrate includes selectively etching through a portion of a protective hard mask and a portion of the semiconductor substrate to create at least one isolation trench within the semiconductor substrate, while leaving, at least in part, the protective hard mask above a portion of the semiconductor substrate. The protective mask may be fabricated of or includes a nitride material, and may have a thickness of between about 30 nanometers to about 60 nanometers, inclusively.
In one aspect, the protective hard mask is selectively removed from the semiconductor substrate, such as by using hot phosphoric acid. The height of an isolation trench after removal of hard mask material is defined as the distance from the base of the trench to a hypothetical plane that is coplanar with the surface of portions of the semiconductor substrate that were not etched to create an isolation trench. Insulating material, such as an oxide material, is next provided within and substantially above the top of at least one isolation trench and, optionally, may also be provided atop the surface of at least one other portion of the semiconductor substrate that was not etched to create an isolation trench. Exposed surface of insulating material is then selectively planarized to be substantially coplanar with the surface of portions of semiconductor substrate that were not etched to create an isolation trench, which serve as the planarization stop. In one example, providing insulating material may include leaving the portion of the insulating material over the at least one isolation trench having a thickness above the height of the isolation trench of about 200 nanometers to about 300 nanometers.
In one aspect, planarizing includes chemical-mechanical polishing or etch back polishing. Polishing may include use of a slurry, such as ceria slurry. Polishing may involve a process that is selective for insulating material over semiconductor substrate material. In another aspect, an exposed surface of semiconductor material may be cleaned following planarization. Cleaning may comprise use of dilute hydrofluoric acid or a standard cleaning solution known to one skilled in the art.
By way of example,
By way of example only, protective mask material 208 may have been deposited on semiconductor substrate 202, directly or indirectly, using conventional deposition processes, such as, for example, chemical vapor deposition (CVD), low-pressure CVD, or plasma-enhanced CVD (PE-CVD). In one example, protective mask material 208 may include or be fabricated of a material such as silicon nitride. In a specific example, silicon nitride may be deposited using process gases such as, for example, dichlorosilane (SiH2Cl2) and ammonia (NH3) and using known process conditions. In another example, silicon nitride may also or alternatively be deposited using halogen-free precursor such as, for example, bis (t-butylamino)silane (BTBAS) (SiC8N2H22) and ammonia (NH3) at about 550° C.
Isolation trenches 210 are also formed within the substrate 202. Although not depicted in figures, one skilled in the art would know that isolation trenches 210 may have been created by one or more lithographic steps, which involve patterning hard mask material 208. Lithographic steps may include, for example, providing patterned antireflective and photoresist layers over the hard mask to facilitate etching a pattern in the semiconductor substrate 202, and leaving a layer of hard mask 208 which may be several hundred angstroms thick atop fins 211. Any suitable conventional anisotropic dry etching processes, such as reactive ion etching processes, may be employed to anisotropically etch through semiconductor substrate 202 to create isolation trenches 210. In a specific example, the reactive ion etching may be performed using fluorine based chemistry and involving gases such as tetrafluoromethane (CF4), trifluoromethane (CHF3), difluoromethane (CH2F2), fluoromethane (CH3F), octofluoromethane (C4F8), hexafluoro-1,3-butadiene (C4F6), sulfur hexafluoride (SF6) and oxygen (O2).
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Although not depicted, an exposed surface of semiconductor material may be cleaned following planarization. Cleaning may comprise use of dilute hydrofluoric acid or a standard cleaning solution known to one skilled in the art. Also although not depicted, one skilled in the art would know that additional layers of material may be provided on or within the structure 200 depicted in
Advantages of aspects of the present invention are that difficulties pertaining to gap fill are reduced, removal of insulating material from above hard mask material and deglazing before hard mask material removal are not required, and uniformity of semiconductor device are enhanced.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise” (and any form of comprise, such as “comprises” and “comprising”), “have” (and any form of have, such as “has” and “having”), “include” (and any form of include, such as “includes” and “including”), and “contain” (and any form contain, such as “contains” and “containing”) are open-ended linking verbs. As a result, a method or device that “comprises”, “has”, “includes” or “contains” one or more steps or elements possesses those one or more steps or elements, but is not limited to possessing only those one or more steps or elements. Likewise, a step of a method or an element of a device that “comprises”, “has”, “includes” or “contains” one or more features possesses those one or more features, but is not limited to possessing only those one or more features. Furthermore, a device or structure that is configured in a certain way is configured in at least that way, but may also be configured in ways that are not listed.
The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain the principles of one or more aspects of the invention and the practical application, and to enable others of ordinary skill in the art to understand one or more aspects of the invention for various embodiments with various modifications as are suited to the particular use contemplated.