Claims
- 1. A method for manufacturing a semiconductor circuit incorporating:a semiconductor layer including a channel region, and source and drain regions arranged via said channel region over a substrate, a gate electrode arranged on said channel region via an insulating film, a source electrode electrically connected to said drain region, a drain electrode electrically connected to said drain region, said method including a step for selectively heightening a resistance of a partial region in said channel region of said semiconductor layer.
- 2. The method for manufacturing a semiconductor circuit according to claim 1, wherein said semiconductor layer is polysilicon crystallized from amorphous silicon.
- 3. The method for manufacturing a semiconductor circuit according to claim 2, wherein said semiconductor circuit is a thin film transistor constituting an analog switch for driving a signal line.
Priority Claims (2)
Number |
Date |
Country |
Kind |
1999-271221 |
Sep 1999 |
JP |
|
2000-281158 |
Sep 2000 |
JP |
|
CROSS REFERENCE TO RELATED APPLICATIONS
The subject application is related to subject matter disclosed in Japanese Patent Applications No. H11-271221 filed on Sep. 24, 1999, and No. H12-281158 filed on Sep. 18, 2000, in Japan to which the subject application claims priority under Paris Convention and which is incorporated herein by reference. This application is a divisional of 09/668,739 filed on Sep. 25, 2000, now U.S. Pat. No. 6,372,612 presently allowed.
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Number |
Date |
Country |
2746411 |
Feb 1998 |
JP |