Method for measuring effective gate channel length during C-V method

Abstract

The present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% compared with the real gate length form SEM. Furthermore, the calculating method of the present invention only uses simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present method provides a simple way to measure those parameters, which have become more and more important in the device.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention generally relates to a method for measuring an effective gate channel length, and more particularly relates to a method for measuring an effective channel length during the application of a capacitance-voltage (C-V) method.

2. Description of the Prior Art

Channel length is a key parameter in CMOS technology used for performance projection (circuit models), short-channel design, and process monitoring. It usually differs from the gate length by an amount depending on the gate lithography and the etch bias, as well as on the lateral source/drain diffusion.

In general, channel length is determined by using an I-V (current-voltage) method, which is determined from a series of linear (low-drain-bias) I-V curves of devices with different mask lengths. The channel lengths of MOSFET are becoming increasingly difficult to measure in the deep sub-micron region due to strong variation of mobility with gate voltage, more pronounced effects of graded source/drain doping profiles, and linewidth-dependent lithography bias near the optical resolution limit.

However, the general I-V method is derived for long-channel devices and is not strictly valid for short-channel devices, so an improved channel-length extraction algorithm, called the shift-and-ratio (S&R) method, is formed. The S&R method is complicated and can not calculate the length of the gate etch bias (L pb ) and the length of the gate to drain overlap (L overlap ).

Accordingly, it is obvious that the conventional method for measuring the channel length is defective and then an easy and mendable method is instantly required, especially in the scaling down of devices for measuring an effective gate channel length, a gate etch bias length, and a gate-to-drain overlap length.

SUMMARY OF THE INVENTION

An object of the invention is to use a C-V method to measure an effective gate channel length in a device.

Another object of the invention is to use a C-V method more accurately to measure a gate-to-drain overlap length and a gate etch bias length in a device.

In order to achieve the previous objects of the invention, the method of the present invention comprises the following essential steps. First, a first device is provided with a source/drain and a gate mounted on a substrate. The gate of the first device is in a predetermined length L 1 , a predetermined width W 1 , and a predetermined height H 1 , wherein the predetermined width being orthogonal to the predetermined length of the gate. Next, a negative fixed voltage is applied to the gate of the first device and then a first capacitance between the gate and the source/drain of the first device is measured at the negative fixed voltage. Thereafter, a positive fixed voltage is applied to the gate of the first device and then a second capacitance between the gate and the source/drain of the first device is measured at the positive fixed voltage. Then, a gate-to-drain overlap length of the first device is determined using the measured first capacitance. Next, a gate etch bias length of the first device is determined using the measured second capacitance. Last, the effective channel length is calculated from the gate-to-drain overlap length and the gate etch bias length.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects and many of the accompanying advantages of this invention will become more readily appreciated as the same becomes better understood by reference to the following detailed description, when taken in conjunction with the accompanying drawings, wherein:

FIG. 1 is a schematic diagram showing the definition and relationship among various notions of length in a MOS device;

FIG. 2 is a schematic diagram showing the different predetermined dimensions of the gate of the first device, the second device, and the third device;

FIG. 3 is a schematic diagram showing the split C-V measurement setup;

FIG. 4 is a schematic diagram showing the measured capacitance from gate to source/drain versus a voltage to a gate for a MOS device; and

FIG. 5 is a schematic diagram showing the measured capacitance per unit width from gate to source/drain versus a voltage to a gate for a MOS device.

DESCRIPTION OF THE PREFERRED EMBODIMENT

The semiconductor devices of the present invention are applicable to a broad range of semiconductor devices and can be fabricated from a variety of semiconductor materials. The following description discusses several presently preferred embodiments of the semiconductor devices of the present invention as implemented in silicon substrates, since the majority of currently available semiconductor devices are fabricated in silicon substrates and the most commonly encountered applications of the present invention will involve silicon substrates. Nevertheless, the present invention may also be advantageously employed in gallium arsenide, germanium, and other semiconductor materials. Accordingly, application of the present invention is not intended to be limited to those devices fabricated in silicon semiconductor materials, but will include those devices fabricated in one or more of the available semiconductor materials.

Further, although the embodiments illustrated herein are shown in two-dimensional views with various regions having width and depth, it should be clearly understood that these regions are illustrations of only a portion of a single cell of a device, which may include a plurality of such cells arranged in a three-dimensional structure. Accordingly, these regions will have three dimensions, including length, width and depth, when fabricated in an actual device.

FIG. 1 shows schematically how various notions of length in a MOS device are defined. L mask 62 is a design length on a gate etch mask 60 and is reproduced on a substrate 10 as L gate 42 of a gate 40 through lithography and etching processes. Depending on the lithography and etching biases, L gate 42 can be either longer or shorter than L mask 62 and L pb is defined as a length of gate etch bias, wherein the length 52 is half gate etch bias length (L pb /2). Although L gate 42 is an important parameter for process control and monitoring, there is no simple way of making a large number of measurements of it. Usually, L gate 42 is measured with a scanning electron microscope (SEM) and only sporadically across the wafer. With the trend of scaling down, a gate-to-drain overlap length L overlap 16 becomes more and more important to affect the operation and performance of a MOS device and L overlap depends on the extension of a source/drain 12 in the substrate 10 . L eff is defined as an effective gate channel length between the junction of the source/drain 12 and the parameter L eff 14 must be measured by some electrical characteristics of a MOS device. L gate and L eff can be expressed as equation (1) and equation (2)

L pb =L mask −L gate   (1)

L eff =L mask −L pb −2 *L overlap   (2)

where L pb is the length of gate etch bias, L mask is the design length on a gate etch mask, L gate is the length of the gate, and L overlap is the length of gate-to-drain overlap.

The method of the present invention comprises the following steps. First, a first device, a second device, and a third device are provided and each one of those devices is with a source/drain and a gate mounted on a substrate, as shown in FIG. 1 . FIG. 2 is a schematic diagram showing the different predetermined dimensions of the gate of those devices. The predetermined length, the predetermined width, and the predetermined height of gates 201 , 202 , and 203 of the first device, the second device, and the third device L 1 , W 1 , H 1 ; L 2 , W 2 , H 2 ; and L 3 , W 3 , H 3 are L, W, H; L/2, W, H; and L, W/2, H. The first device and the second are different only in the width of the gate. The first device and the third device are different only in the length of the gate. Those devices have an intrinsic capacitance per unit width C total between the gate and the source/drain at a fixed voltage to the gate, wherein C total can be expressed as equation (3):

C total =C gate +2 *C overlap +2 *C fringing +( C offset /W )  (3)

where C total is the intrinsic capacitance per unit width between the gate and the source/drain, C gate is an intrinsic gate-to-channel capacitance per unit width, C overlap is a gate-to-drain overlap capacitance per unit width, C fringing is a fringing capacitance per unit width, C offset is a deviation captacitance from a measuring apparatus, and W is the predetermined width of the gate. Furthermore, the fringing capacitance per unit width C fringing can be expressed as equation (4):

  C fringing =2*ε oxide /π*ln[ 1+( H gate /H gate oxide )]  (4)

where H gate is the predetermined high of the gate, H gate oxide is the height of the gate oxide layer 20 as shown in FIG. 1 , and ε oxide is the field of the gate oxide layer. In the present method, H gate , H gate oxide , and ε oxide are constants, so C fringing is also a constant.

Next, an electrical signal testing is performed to acquire some characteristics of those devices to measure the effective channel gate length. The electrical testing, which is shown in FIG. 4 , is performed in a C-V setup as shown in FIG. 3 . As the intrinsic capacitance per unit width C total , at a negative fixed voltage to the gate, C total , can be expressed as an accumulation capacitance per unit width C accumulation , which is expressed as equation (5):

C accumulation =2 *C overlap +2 *C fringing +( C offset /W )  (5)

where C accumulation is an accumulation capacitance per unit width at a negative fixed voltage to the gate. Referring FIG. 5 , the gate-to-drain overlap capacitance per unit width C overlap has very little difference at the accumulation region.

In another condition, when the intrinsic capacitance per unit width C total is at a positive fixed Voltage to the gate, C total can be expressed as an inversion capacitance per unit width C inversion , which is expressed as equation (6):

C inversion =C gate +2 *C fringing +( C offset /W )  (6)

where C inversion is an inversion capacitance per unit width at a positive fixed voltage to the gate.

Thereafter, the measuring the effective channel gate length comprises the following steps. First, a negative fixed voltage is applied to the gate of the first device and the second device. Then, a first capacitance between the gate and the source/drain of the first device C accumulation,measured,1 and a second capacitance between the gate and the source/drain of the second device C accumulation,measured,2 are measured at the negative fixed voltage. Next, C accumulation,measured, 1 and C accumulation,measured,2 are put in the equation (5) to become equation (5-1) and equation (5-2):

C accumulation,1 =2 *C overlap,1 *W 1 +2 *C fringing,1 *W 1 +C offset,1   (5-1)

C accumulation,measured2 =2 *C overlap,2 *W 2 +2 *C fringing,2 *W 2 +C offset,2   (5-2)

where W 1 and W 2 are known and C fringing,1 and C fringing,2 are constant. Because C overlap has a very small difference at the accumulation region, C overlap,1 and C overlap,2 can be meant equal. However, because C offset is produced from the measuring apparatus, C offset is a constant. Thus, solving the equation (5-1) and the equation (5-2) can acquire C overlap and C offset .

Furthermore, the gate-to-drain overlap length C overlap of the first device can be calculated according to equation (7):

L overlap =( H gate oxide *C overlap )/ε oxide   (7)

where H gate oxide is the height of the gate oxide layer 20 as shown in FIG. 1 , and ε oxide is the field of the gate oxide layer.

Next, a positive fixed voltage is applied to the gate of the first device and the third device. Then, a third capacitance between the gate and the source/drain of the first device C inversion,measured,1 and a fourth capacitance between the gate and the source/drain of the second device C inversion,measured,3 are measured at the negative fixed voltage. Next, C inversion,measured,1 and C inversion,measured,3 are put in the equation (6) to become equation (6-1) and equation (6-2):

C inversion,measured,1 =C gate,1 *W 1 +2 *C fringing,1 *W 1 +C offset,1   (6-1)

C inversion,measured,3 =C gate,3 *W 3 +2 *C fringing,3 *W 3 +C offset,3   (6-2)

where W 1 and W 3 are known and equal and C fringing,1 and C fringing,3 are constant. Thus, C gate,1 and C gate,2 can be acquired from the equation (6-1) and the equation (6-2). Furthermore, the length of the gate of the first device L gate cane be acquired from equation (8):

L gate =( C gate *W )*( L 1 −L 3 )/[( C gate1 −C gate,3 ) *W]   (8)

where L gate is the length of the gate of the first device; C gate is equal to C gate,1 ; and W is equal to W 1 and W 3 .

According to the following step, the gate etch bias length L pb can be calculated by the equation (1), where L pb =L mask −L gate . Finally, the effective channel length L eff of the first device can be calculated by the equation (2), where L eff =L mask −L pb −2*L overlap .

To sum up the foregoing the present invention provides a C-V method for measuring an effective channel length in a device, which can simultaneously measure a gate-to-drain overlap length and a gate etch bias length in the device. In the present method, the measured length of the gate by using the present method has a deviation below 5% compared with the real gate length form SEM. Furthermore, the calculating method of the present invention only uses simple simultaneous equations, which can be measured by a man or a mechanism. As the layout rule shrunk, the present invention provides a simple way to measure those parameters, which have become more and more important in the device.

Of course, it is to be understood that the invention need not be limited to these disclosed embodiments. Various modifications and similar changes are still possible within the spirit of this invention. In this way, the scope of this invention should be defined by the appended claims.

Claims

1. A method for measuring an effective channel length during a capacitance-voltage (C-V) method, said method comprising:providing a first device comprising a first gate electrode, a first source and a first drain, a second device comprising a second gate electrode, a second source and a second drain, wherein said first gate electrode has a gate length L and a gate width W1, said second gate electrode has a gate length L and a gate width W2; applying a negative fixed voltage to said first gate electrode and said second gate electrode; measuring an accumulation capacitance per unit width of said first device Cacc1 and an accumulation capacitance per unit width of said second device Cacc2, wherein said Cacc1 and said Cacc2 are expressed as a first equation and a second equation, Cacc1=2×Cov+2×Cf+(Coff/W1)  Cacc2=2×Cov+2×Cf+(Coff/W2)whereCov is a gate-to-drain overlap capacitance per unit width, Cf is a fringing capacitance per unit width, Coff is a deviation capacitance from a measuring apparatus; and solving said first equation and said second equation to obtain said Cov and said Coff.

2. The method according to claim 1, wherein a gate-to-drain overlap length Lov of said first device and said second device can be obtained by putting said Cov into a third equation,Lov=(Hox×Cov)/εoxide whereHox is a height of a gate oxide layer of said first device and said second device and εox is a field of said gate oxide of said first device and said second device.

3. A method for measuring an effective channel length during a capacitance-voltage (C-V) method, said method comprising:providing a first device comprising a first gate electrode, a first source and a first drain, a second device comprising a second gate electrode, a second source and a second drain, wherein said first gate electrode has a gate length L and a gate width W, said second gate electrode has a gate length L and a gate width W/2; applying a negative fixed voltage to said first gate electrode and said second gate electrode; measuring an accumulation capacitance per unit width of said first device Cacc1 and an accumulation capacitance per unit width of said second device Cacc2, wherein said Cacc1 and said Cacc2 are expressed as a first equation and a second equation, Cacc1=2×Cov+2×Cf+(Coff/W) Cacc2=2×Cov+2×Cf+(2Coff/W) whereCov is a gate-to-drain overlap capacitance per unit width, Cf is a fringing capacitance per unit width, Coff is a deviation capacitance from a measuring apparatus; solving said first equation and said second equation to obtain said Cov and said Coff; and calculating a gate-to-drain overlap length Lov of said first device and said second device by putting said Cov into a third equation, Lov=(Hox×Cov)/εoxide whereHox is a height of a gate oxide layer of said first device and said second device and εox is a field of said gate oxide of said first device and said second device.