Patent Grant
7037733
The present invention relates to a method for accurately measuring a temperature of an object such as a substrate by measuring the emissivity of the object, and more particularly, it relates to an annealing method in which an object is annealed at an accurate temperature on the basis of the emissivity of the object.
The annealing system 100 of
The annealing system 100 further includes a table 103 for placing a substrate 10 to be annealed and a support 104 for supporting and vertically moving the table 103. The substrate 10 can be held in an arbitrary position within the thermal region Rth by vertically moving the table 103, so that the substrate 10 can be annealed at a desired temperature.
The annealing system 100 further includes a cover 105 for housing the furnace 101, the coil 102 and the table 103, and a substrate inlet/outlet 106 provided on the cover 105. Specifically, the substrate 10 inserted into the cover 105 through the substrate inlet/outlet 106 is placed on the table 103 so as to be annealed at a desired temperature in the thermal region Rth. The end of the support 104 opposing the table 103 extends to the outside of the cover 105.
In order to find out the temperature of the substrate 10 being annealed, it is necessary to measure the emissivity (thermal emissivity) ε and the pyrometer intensity (radiance) I of the substrate 10 as described later. For this purpose, a photoirradiation section 107 for irradiating the reverse face of the substrate 10 placed on the table 103 with measuring light of a predetermined wavelength is provided on the bottom of the cover 105, and a measuring section 108 for measuring the emissivity ε and the pyrometer intensity I on the reverse face of the substrate 10 is provided outside the cover 105 below the support 104.
Now, the reason why the temperature T can be obtained on the basis of the emissivity ε and the pyrometer intensity I will be described. In general, the pyrometer intensity I of a blackbody is represented by the following formula I on the basis of Planck's formula of radiation:
I(T, λ)=2πC1/λ5·(exp((C2/(λT))−1)) Formula 1
As shown in formula 1, the pyrometer intensity I of a blackbody is a function of the temperature T of the blackbody and the wavelength λ of the measuring light. In other words, the pyrometer intensity I is varied in accordance with the temperature T and the wavelength λ. In formula 1, C1 and C2 are constants.
Also, the pyrometer intensity I of a general object (nonblackbody) is represented by the following formula 2 using the emissivity ε of the object:
I(T, λ)=ε(T, λ)·2πC1/λ5·(exp((C2/(λT))−1)) Formula 2
As shown in formula 2, the emissivity ε is also a function of the temperature T of the object and the wavelength λ of the measuring light. Accordingly, in the case where the wavelength λ has a specific value, the temperature T is a function of the emissivity ε and the pyrometer intensity I, which is represented by the following formula 3:
T=f(ε(emissivity), I (pyrometer intensity)) Formula 3
As shown in formula 3, the actual temperature T of an object being annealed can be obtained by measuring the emissivity ε and the pyrometer intensity I. In formula 3, f indicates a function (temperature measurement function) having variables ε and I. Also, in the case where the measuring light irradiating an object is entirely reflected by the object, the emissivity ε of the object is 0, and in the case where the measuring light irradiating an object is entirely absorbed by the object (namely, in the case where the object is a blackbody), the emissivity ε of the object is 1. In other words, when the reflectance of the measuring light is r, ε=1−r. Accordingly, instead of directly measuring the emissivity ε, the reflectance r can be measured so as to indirectly measure the emissivity ε by using the measured reflectance r.
As described above, in the annealing system 100 of
In consideration of the above, an aim of the invention is accurately measuring the temperature of an object being annealed, so that annealing can be performed on the object at an accurate temperature.
In order to achieve the object, the present inventors have performed comparative experiments for measuring the emissivities ε during annealing of a variety of experiment samples in each of which a plurality of films of various materials are stacked on a substrate.
a) shows the film structures (materials and thicknesses of the respective films) of the respective experiment samples (samples A, B and C), and
As shown in
Also, as shown in
Furthermore, as shown in
As shown in
a) shows the relationships between the annealing time (specifically, time elapsed from the start of annealing) and the emissivity ε obtained with respect to the samples A, B and C. In
Also in the sample C shown in
b) shows the relationships between the annealing time and the emissivity ε obtained with respect to a plurality of samples B (samples B1, B2, B3, B4 and B5) fabricated under the conditions shown in
Specifically, as a result of the comparative experiments made by the present inventors, it was found that different measured values of the emissivity ε may be obtained even in measuring the emissivity ε of the same object. Accordingly, it was found that in the case where a material that varies the emissivity ε with the annealing time, such as a DPS film, is included as in the samples A and B, the emissivity ε cannot be accurately measured unless the material is removed before measuring the emissivity ε. Also, not only in the case where the light used for measuring the emissivity ε (measuring light) directly irradiates the DPS film (the second DPS film 56) as in the sample A, namely, in the case where the DPS film is present in the uppermost portion, but also in the case where the DPS film (the first DPS film 54) is covered with the film of another material (the SiN film 55) as in the sample B, the emissivity ε is varied. Accordingly, it is necessary to remove, before measuring the emissivity ε, all DPS films formed on the principal plane of the substrate that is irradiated with the measuring light.
In each of the samples A and B, not all the films cause the variation in the emissivity ε with the annealing time but some films such as the SiO2 film and the SiN film are not concerned with the variation in the emissivity ε. Also, the reason why the emissivity ε is varied by a DPS film is presumed to be because the physical properties of the DPS film, such as the grain size, are changed through the annealing. Furthermore, the reason why the variation in the emissivity ε is different among the samples B1 through B5 fabricated under the same conditions is presumed to be because the grain size is changed differently among the samples.
As described so far, in order to accurately measure the emissivity ε of an object being annealed, it is necessary to previously remove a material that varies the emissivity ε. At this point, in an annealing system, such as the annealing system 100 of
ΔT=T2·λ·Δε/(C1·ε) Formula 4
As shown in formula 4, as the measurement error Δε of the emissivity ε is larger, the error ΔT in the temperature T is larger. Accordingly, in order to perform annealing on an object at an accurate temperature by using the annealing system as shown in
The present invention was devised on the basis of the aforementioned finding, and specifically, the first method for measuring emissivity of this invention includes a step of measuring emissivity ε of an object, while annealing the object having a first face and a second face, by irradiating the second face with measuring light of a given wavelength, and in the step of measuring emissivity ε, a film of a material that varies the emissivity ε is formed on the first face and no film of the material is formed on the second face.
In the first method for measuring emissivity, since the emissivity ε of an object is measured in a state where a film of a material causing variation in the emissivity ε is not present on the second face of the object corresponding to a face irradiated with the measuring light, and therefore, the emissivity ε of the object can be prevented from varying during the annealing, resulting in accurately measuring the emissivity ε.
In the first method for measuring emissivity, the step of measuring emissivity ε may include a step of measuring reflectance r on the second face of the object for measuring the emissivity ε by using the measured reflectance r.
The second method for measuring emissivity of this invention includes a step of measuring emissivity ε of an object, while annealing the object having a first face and a second face, by irradiating the second face with measuring light of a given wavelength, and in the step of measuring emissivity ε, doped polysilicon is formed on the first face and no doped polysilicon is formed on the second face.
In the second method for measuring emissivity, the emissivity ε of the object is measured in a state where doped polysilicon is not present on the second face of the object corresponding to a face irradiated with the measuring light, and therefore, the emissivity ε of the object can be prevented from varying during the annealing, resulting in accurately measuring the emissivity ε.
In the second method for measuring emissivity, the step of measuring emissivity ε may include a step of measuring reflectance r on the second face of the object for measuring the emissivity ε by using the measured reflectance r.
The first method for measuring a temperature of this invention includes the steps of measuring, while annealing an object having a first face and a second face, emissivity ε on the second face of the object; and calculating a temperature of the object being annealed on the basis of the measured emissivity ε, and in the step of measuring emissivity ε, a film of a material that varies the emissivity ε is formed on the first face and no film of the material is formed on the second face.
In the first method for measuring a temperature, the emissivity ε on the second face of the object is measured in a state where a film of a material causing variation in the emissivity ε is not present on the second face, and the temperature of the object being annealed is calculated on the basis of the measured emissivity ε. Therefore, the emissivity ε of the object can be prevented from varying during the annealing, so as to accurately measure the emissivity ε. As a result, on the basis of the measured emissivity ε, for example, by substituting the measured value of the emissivity ε in the temperature measurement function (see formula 3), the temperature of the object being annealed can be accurately obtained.
In the first method for measuring a temperature, the step of measuring emissivity ε may include a step of measuring reflectance r on the second face of the object for measuring the emissivity ε by using the measured reflectance r.
The second method for measuring a temperature of this invention includes the steps of measuring, while annealing an object having a first face and a second face, emissivity ε on the second face of the object; and calculating a temperature of the object being annealed on the basis of the measured emissivity ε, and in the step of measuring emissivity ε, doped polysilicon is formed on the first face and no doped polysilicon is formed on the second face.
In the second method for measuring a temperature, the emissivity ε on the second face of the object is measured in a state where doped polysilicon is not present on the second face, and the temperature of the object being annealed is calculated on the basis of the measured emissivity ε. Therefore, the emissivity ε of the object can be prevented from varying during the annealing, so as to accurately measure the emissivity ε. As a result, on the basis of the measured emissivity ε, for example, by substituting the measured value of the emissivity ε in the temperature measurement function (see formula 3), the temperature of the object being annealed can be accurately obtained.
In the second method for measuring a temperature, the step of measuring emissivity ε may include a step of measuring reflectance r on the second face of the object for measuring the emissivity ε by using the measured reflectance r.
The annealing method of this invention for performing annealing on a substrate by using an annealing system including a substrate placing section, a heating section for annealing the substrate placed on the substrate placing section and a measuring section for measuring emissivity ε of the substrate placed on the substrate placing section, includes the steps of measuring the emissivity ε on a reverse face of the substrate with the measuring section while placing the substrate on the substrate placing section in a state where a film of a material that varies the emissivity ε is formed on a top face of the substrate and where no film of the material is formed on the reverse face of the substrate and while annealing the substrate with the heating section; and performing the annealing on the substrate while controlling an annealing temperature for the substrate on the basis of the measured emissivity ε.
In the annealing method of this invention, the emissivity ε on the substrate reverse face is measured in a state where a film of a material causing the variation in the emissivity ε is not present on the substrate reverse face, and the annealing is performed on the substrate while controlling the annealing temperature on the basis of the measured emissivity ε. Therefore, the emissivity ε of the substrate can be prevented from varying during the annealing, so as to accurately measure the emissivity ε. As a result, the annealing can be performed on the substrate while accurately controlling the annealing temperature on the basis of the measured emissivity ε.
In the annealing method of this invention, the step of measuring emissivity ε may include a step of measuring reflectance r on the reverse face of the substrate for measuring the emissivity ε by using the measured reflectance r.
The annealing method of this invention preferably further includes, before the step of measuring the emissivity ε, a step of removing a film of the material having been formed on the reverse face of the substrate.
Thus, the annealing of the substrate can be performed at an accurately temperature by merely adding the step of removing the film of the material that varies the emissivity εhaving been formed on the reverse face of the substrate.
Also in this case, the annealing method may further include, before the step of removing a film of the material, a step of simultaneously forming the film of the material on the top face and the reverse face of the substrate.
In the annealing method of this invention, the heating section has a temperature gradient formed in a given region therein, and the step of performing the annealing on the substrate may include a step of controlling the annealing temperature for the substrate by controlling a position for holding the substrate within the given region with the substrate placing section.
The first method for fabricating a semiconductor device of this invention using an annealing system including a substrate placing section, a heating section for annealing a semiconductor substrate placed on the substrate placing section and a measuring section for measuring emissivity ε of the semiconductor substrate placed on the substrate placing section, includes the steps of forming a doped polysilicon film on at least a top face of the semiconductor substrate before placing the semiconductor substrate on the substrate placing section; measuring the emissivity ε on a reverse face of the semiconductor substrate with the measuring section while placing the semiconductor substrate on the substrate placing section in a state where no doped polysilicon film is formed on the reverse face of the semiconductor substrate and while annealing the semiconductor substrate with the heating section; and performing annealing on the semiconductor substrate while controlling an annealing temperature for the semiconductor substrate on the basis of the measured emissivity ε.
In the first method for fabricating a semiconductor device, after forming a polysilicon film doped with an impurity (hereinafter referred to as the DPS (Doped Poly-Silicon) film) at least on the top face of the semiconductor substrate, the emissivity εon the reverse face of the semiconductor substrate is measured in a state where a DPS film, namely, a film of a material that varies the emissivity ε, is not present on the reverse face of the semiconductor substrate. Then, the annealing is performed on the semiconductor substrate while controlling the annealing temperature on the basis of the measured emissivity ε. Therefore, the emissivity ε of the semiconductor substrate can be prevented from varying during the annealing, so as to accurately measure the emissivity ε. As a result, the annealing can be performed on the semiconductor substrate while accurately controlling the annealing temperature on the basis of the measured emissivity ε. Accordingly, a semiconductor device having a planned characteristic can be fabricated.
In the first method for fabricating a semiconductor device, the step of measuring the emissivity ε may include a step of measuring reflectance r on the reverse face of the semiconductor substrate for measuring the emissivity ε by using the measured reflectance r.
In the first method for fabricating a semiconductor device, the step of forming a polysilicon film preferably includes a step of simultaneously forming the polysilicon film on the top face and the reverse face of the semiconductor substrate, and the method for fabricating a semiconductor device preferably further includes, between the step of forming a polysilicon film and the step of measuring the emissivity ε, a step of removing a portion of the polysilicon film having been formed on the reverse face of the semiconductor substrate.
Thus, the annealing of the semiconductor substrate can be performed at an accurate temperature by merely adding the step of removing the DPS film having been formed on the reverse face of the semiconductor substrate, so that a semiconductor device having a planned characteristic can be fabricated.
In the first method for fabricating a semiconductor device, the heating section has a temperature gradient formed in a given region therein, and the step of performing annealing on the semiconductor substrate may include a step of controlling the annealing temperature for the semiconductor substrate by controlling a position for holding the semiconductor substrate within the given region with the substrate placing section.
The second method for fabricating a semiconductor device of this invention using an annealing system including a substrate placing section, a heating section for annealing a semiconductor substrate placed on the substrate placing section and a measuring section for measuring emissivity ε of the semiconductor substrate placed on the substrate placing section, includes the steps of forming a doped polysilicon film in at least a memory cell forming region on a top face of the semiconductor substrate before placing the semiconductor substrate on the substrate placing section; measuring the emissivity ε on a reverse face of the semiconductor substrate with the measuring section while placing the semiconductor substrate on the substrate placing section in a state where no doped polysilicon film is formed on the reverse face of the semiconductor substrate and while annealing the semiconductor substrate with the heating section; and performing annealing on the semiconductor substrate while controlling an annealing temperature for the semiconductor substrate on the basis of the measured emissivity ε.
In the second method for fabricating a semiconductor device, the emissivity ε on the reverse face of the semiconductor substrate is measured after forming a DPS film at least in a memory cell forming region on the top face of the semiconductor device, and in a state where a DPS film, namely, a film of a material that varies the emissivity ε, is not present on the reverse face of the semiconductor substrate. Then, the annealing is performed on the semiconductor substrate while controlling the annealing temperature on the basis of the measured emissivity ε. Therefore, the emissivity εof the semiconductor substrate can be prevented from varying during the annealing, so as to accurately measure the emissivity ε. As a result, the annealing can be performed on the semiconductor substrate while accurately controlling the annealing temperature on the basis of the measured emissivity ε. Accordingly, a memory-embedded type semiconductor device having a planned characteristic can be fabricated.
In the second method for fabricating a semiconductor device, the step of measuring the emissivity ε may include a step of measuring reflectance r on the reverse face of the semiconductor substrate for measuring the emissivity ε by using the measured reflectance r.
In the second method for fabricating a semiconductor device, the step of forming a polysilicon film preferably includes a step of simultaneously forming the polysilicon film entirely over the top face and the reverse face of the semiconductor substrate, and the method for fabricating a semiconductor device preferably further includes, between the step of forming a polysilicon film and the step of measuring the emissivity ε, a step of removing a portion of the polysilicon film formed in a region excluding the memory cell forming region on the top face of the semiconductor substrate and a portion of the polysilicon film formed on the reverse face of the semiconductor substrate.
Thus, the annealing of the semiconductor substrate can be performed at an accurate temperature merely by adding the step of removing the DPS film having been formed on the reverse face of the semiconductor substrate, so that a semiconductor device having a planned characteristic can be fabricated. When the step of removing the DPS film having been formed on the reverse face of the semiconductor substrate is performed simultaneously with a step of removing the portion of the DPS film formed in the region excluding the memory cell forming region on the top face of the semiconductor substrate, substantial increase of the number of procedures can be avoided.
In the second method for fabricating a semiconductor device, the heating section has a temperature gradient formed in a given region therein, and the step of performing annealing on the semiconductor substrate may include a step of controlling the annealing temperature for the semiconductor substrate by controlling a position for holding the semiconductor substrate within the given region with the substrate placing section.
a) through 1(c) are cross-sectional views for showing procedures in a method for fabricating a semiconductor device according to an embodiment of the invention.
a) through 2(c) are cross-sectional views for showing procedures in the method for fabricating a semiconductor device according to the embodiment of the invention.
a) through 3(c) are cross-sectional views for showing procedures in the method for fabricating a semiconductor device according to the embodiment of the invention.
a) and 4(b) are cross-sectional views for showing procedures in the method for fabricating a semiconductor device according to the embodiment of the invention.
a) and 5(b) are cross-sectional views for showing procedures in the method for fabricating a semiconductor device according to the embodiment of the invention.
a) and 8(b) are diagrams for schematically showing the inside states of an annealing system performing annealing in the method for fabricating a semiconductor device according to the embodiment of the invention.
a) is a table for showing the film structures (the materials and the thicknesses of respective films) of samples A, B and C used in comparative experiments performed by the present inventors for measuring the emissivity ε,
a) is a diagram for showing relationships between the annealing time and the emissivity ε obtained with respect to the samples A, B and C, and
Now, a method for fabricating a semiconductor device according to an embodiment of the invention will be described with reference to the drawings by exemplifying an embedded-DRAM type semiconductor device including a memory cell region and a logic region. In the following description, a principal plane of a substrate on which devices such as a transistor are formed is designated as a top face and a principal plane thereof on which devices are not formed is designated as a reverse face. In other words, devices are formed on the top face of the substrate but no devices are formed on the reverse face of the substrate.
a) through 1(c), 2(a) through 2(c), 3(a) through 3(c), 4(a), 4(b), 5(a) and 5(b) are cross-sectional views for showing procedures in the method for fabricating a semiconductor device according to this embodiment.
First, as shown in
Next, after the silicon substrate 10 is taken out from the CVD system, the polysilicon film 12 deposited on the substrate top face is etched, thereby forming gate electrodes 12A from the polysilicon film 12 and gate insulating films 11A from the silicon oxide film 11 respectively in the memory cell region R1 and the logic region R2 on the top face of the silicon substrate 10 as shown in
Next, the silicon substrate 10 is set in, for example, a CVD system similar to that of
Next, the silicon substrate 10 is set in a plasma CVD system for depositing a silicon oxide film, for example, as shown in
In the subsequent procedures, a memory cell is formed in the memory cell region R1 alone. In other words, no memory cell is formed in the logic region R2. Specifically, after taking out the silicon substrate 10 from the plasma CVD system, a contact hole 14a reaching a predetermined portion in the memory cell region R1 of the silicon substrate 10 (the source/drain region of the memory cell transistor) is first formed in the planarized film 14 as shown in
Next, the silicon substrate 10 is set in, for example, a CVD system similar to that of
Next, after taking out the silicon substrate 10 from the CVD system, a portion of the first DPS film 15 deposited on the substrate top face outside the contact hole 14a is removed by etching, thereby forming a plug 15A from the first DPS film 15 as shown in
Next, the silicon substrate 10 is set in, for example, a plasma CVD system similar to that of
Next, after taking out the silicon substrate 10 from the plasma CVD system, the silicon substrate 10 is set in, for example, a CVD system similar to that of
Next, after taking out the silicon substrate 10 from the CVD system, a resist film 18 is formed over the entire tope face of the silicon substrate 10 as shown in
Next, as shown in
Next, after taking out the silicon substrate 10 from the CVD system, the SiN film 19 and the third DPS film 20 deposited on the substrate top face are patterned by the etching as shown in
Through the aforementioned procedures, a memory cell provided with the transistor including the gate electrode 12A and the like and a capacitor including the capacitor lower electrode 17A, the capacitor dielectric film 19A and the capacitor upper electrode 20A is formed in the memory cell region R1 on the substrate top face, and the logic transistor including the gate electrode 12A and the like is formed in the logic region R2 on the substrate top face. Also, after completing the aforementioned procedures, the semiconductor device under fabrication has a film structure free from a DPS film present on the substrate reverse face (namely, the plane on which the emissivity ε is to be measured).
Next, the silicon substrate 10 in which the memory cell and the logic transistor have been formed (hereinafter simply referred to as the substrate 10) is subjected to annealing. Specifically, a general annealing system, such as the hot wall type annealing system 100 shown in
a) and 8(b) schematically show the inside states of the annealing system during the annealing performed in the method for fabricating a semiconductor device of this embodiment.
First, as shown in
Next, when the monitored temperature T is increased close to 1000° C., as shown in
After completing the annealing of the substrate 10, the substrate 10 is lowered by using the support 104 from the annealing hold position H2 to the initial position H0. Thereafter, the substrate 10 is naturally cooled, and then, the substrate 10 is taken out from the annealing system 100 through the substrate inlet/outlet 106.
The description of subsequent procedures of this embodiment is omitted, and this embodiment attains the following effects: In the annealing processing for the substrate 10 (specifically, the annealing processing for activating the impurity included in the source/drain regions of the transistors), when the emissivity ε on the reverse face of the substrate 10 is measured, the films made from materials that vary the emissivity ε, such as the first DPS film 15 used for forming the plug 15A, the second DPS film 17 used for forming the capacitor lower electrode 17A and the third DPS film 20 used for forming the capacitor upper electrode 20A, are formed on the top face of the substrate 10. On the other hand, a film that varies the emissivity ε, such as a DPS film, is not formed on the reverse face of the substrate 10. Therefore, the emissivity ε can be prevented from varying during the annealing of the substrate 10, and hence, the emissivity ε can be accurately measured. As a result, on the basis of the measured emissivity ε, for example, by substituting the measured value of the emissivity ε in the temperature measurement function (see formula 3), the temperature of the substrate 10 being annealed can be accurately obtained. Accordingly, the annealing can be performed on the substrate 10 while accurately controlling the annealing temperature for the substrate 10, and therefore, a semiconductor device including a transistor that exhibits a planned characteristic can be fabricated.
Also in this embodiment, each of the DPS films formed on the substrate reverse face respectively simultaneously with the first DPS film 15, the second DPS film 17 and the third DPS film 20 formed on the top face of the substrate 10 is removed every time it is formed. More specifically, the first DPS film 15 used for forming the plug 15A, the second DPS film 17 used for forming the capacitor lower electrode 17A and the third DPS film 20 used for forming the capacitor upper electrode 20A are first respectively formed in the memory cell region R1 on the top face of the substrate 10. Thereafter, the unnecessary portion of each DPS film formed on the substrate top face (i.e., each DPS film formed in a region other than the memory cell region R1 on the substrate top face) is removed and each DPS film formed on the substrate reverse face is removed, and thereafter, the annealing is performed on the substrate 10 while measuring the emissivity ε of the substrate 10. Specifically, the emissivity ε can be accurately measured merely by additionally performing the procedures for removing the DPS films formed on the reverse face of the substrate 10, so that the annealing can be performed on the substrate 10 at an accurate temperature. Therefore, an embedded-DRAM type semiconductor device with a planned characteristic can be fabricated.
Although merely the DPS films (the first DPS film 15, the second DPS film 17 and the third DPS film 20) formed on the reverse face of the substrate 10 are removed in this embodiment, the silicon oxide film 11, the polysilicon (nondoped) film 12, the TEOS oxide film 13 or the SiN film 19 may be removed from the substrate reverse face in addition to the DPS films. Also, each DPS film may be a polysilicon film doped with an impurity other than phosphorus.
Furthermore, in this embodiment, when the first DPS film 15, the second DPS film 17 and the third DPS film 20 are formed on the top face of the substrate 10, the respective DPS films are formed also on the substrate reverse face. Instead, a system similar to, for example, that of
Also in this embodiment, before forming the capacitor including the capacitor lower electrode 17A, the capacitor dielectric film 19A and the capacitor upper electrode 20A, the ion implantation is performed on the substrate 10 for forming the source/drain regions of the transistor including the gate electrode 12A and the like. Instead, the source/drain regions may be formed, after forming the capacitor, by performing the ion implantation on the substrate 10 with partly opening, for example, the planarized film 14.
Moreover, in this embodiment, the annealing for activating the impurity included in the source/drain regions is performed with the DPS films formed on the top face of the substrate 10 and with no DPS film formed on the reverse face of the substrate 10 that is irradiated with light for measuring the emissivity ε. This does not limit the invention but the same effects as those of this embodiment can be attained when any annealing is performed with a film made from a material that varies the emissivity ε formed on the top face of the substrate 10 and with no film made from a material that varies the emissivity ε formed on the reverse face of the substrate 10 corresponding to the plane irradiated with the measuring light.
Furthermore, the hot wall type annealing system as shown in
In addition, subjects of this embodiment are the annealing performed on a substrate during the fabrication of a semiconductor device and the measurement of the emissivity ε and the temperature T of the substrate during the annealing. However, this does not limit the invention but it goes without saying that the subject may be annealing performed on any of a variety of objects or the measurement of the emissivity ε or the temperature T of the object.
Moreover, although the emissivity ε on the reverse face of the substrate 10 is directly measured in this embodiment, the reflectance r on the reverse face of the substrate 10 may be measured instead so as to indirectly measure the emissivity ε by using the measured reflectance r. This is because the emissivity ε may be obtained on the basis of the relationship formula, ε=1−r.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2001-332217 | Oct 2001 | JP | national |
| Filing Document | Filing Date | Country | Kind | 371c Date |
|---|---|---|---|---|
| PCT/JP02/06655 | 7/1/2002 | WO | 00 | 2/4/2003 |
| Publishing Document | Publishing Date | Country | Kind |
|---|---|---|---|
| WO03/038384 | 5/8/2003 | WO | A |
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