Examples described herein are generally related to techniques for deterring the use of counterfeit non-volatile memories (NVMs) in computing platforms and solid-state storage devices (SSDs).
In recent years some electronic component supply chains have become polluted by counterfeit NVMs. The negative effect of counterfeit NVMs is not limited to loss of revenue by the legitimate manufacturers but also extends to damage to their reputation and brand images. Various tests may be conducted in an attempt to combat the use of counterfeit products. Common practices after introduction of the “Specification for Authentication of Semiconductors and Related Products S. T20-1109” (available from SEMI at www.semi.org) in 2009 include mechanisms based on generating unpredictable and/or random codes which are applied at the package level. Such mechanisms typically require on-line access to a secure infrastructure to enable the legitimate manufacturer to validate the authenticity of devices. Requiring on-line access to a secure infrastructure is problematic in many product usage scenarios.
As contemplated in the present disclosure, a non-volatile memory (NVM), such as a three-dimensional cross-point memory (e.g., a 3D XPoint™ memory commercially available from Intel Corporation), may be authenticated off-line using unique on-die characteristics. In embodiments of the present invention, authentication using intrinsic device-level characteristics may be applied, and a protocol for validating the authenticity of a NVM may be independent of any techniques for obfuscating NVM secret technology information. In an embodiment, the protocol is cost-effective and avoids extra hardware resources and/or on-line accessibility requirements. Embodiments of the present invention deter the unauthorized replacement of legitimate NVMs with counterfeit NVMs when used with legitimate memory controllers.
In some examples, memory device 102 may include non-volatile types of memory, whose state is determinate even if power is interrupted. In some examples, memory device 102 may include non-volatile types of memory that is block addressable, such as for NAND or NOR technologies. Thus, memory device 102 can also include a future generation of types of NVM, such as a 3-dimensional cross-point memory (commercially available by Intel Corporation as 3D XPoint™), or other byte addressable non-volatile types of memory. According to some examples, memory device 102 may include types of NVM that includes chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level Phase Change Memory (PCM), a resistive memory, nanowire memory, FeTRAM, MRAM that incorporates memristor technology, or STT-MRAM, or a combination of any of the above, or other memory.
However, examples are not limited in this manner, and in some instances memory device 102 may include volatile types of memory including, but not limited to, random access memory (RAM), D-RAM, DDR SDRAM, SRAM, T-RAM or Z-RAM. One example of volatile memory includes dynamic RAM (DRAM), or some variant such as SDRAM. A memory as described herein may be compatible with a number of memory technologies, such as HBM (HIGH BANDWIDTH MEMORY DRAM, JESD235, originally published by Joint Electron Device Engineering Council (JEDEC) Solid State Technology Association (JEDEC) in October 2013) and DDR5 (DDR version 5, currently in discussion by JEDEC), and/or others, and technologies based on derivatives, revisions, versions or extensions of such specifications.
Memory controller 104 may be arranged to control access to data at least temporarily stored at memory device 102. Although only one memory device is shown in the example of
Memory controller 104 may include a validation component 106. Validation component may determine if memory device 102 is authorized to be used with memory controller 104 according to the examples discussed below. In embodiments, the validation component may be implemented within a processor or in a system on a chip (SOC). In at least some examples, memory controller and memory device arrangement 100 uses a challenge response protocol. Memory controller 104 may issue a challenge 120 to memory device 102, which responds with a response 122. Validation component 106 may include a hash function 108 for performing a cryptographic hash of a selected value as is well known. Hash table 110 may store a plurality of hash values, each hash value being associated with a memory device. In an embodiment, some or all of response 122 may be hashed by hash function 108 as part of the challenge response protocol to produce hash values stored in hash table 110. Although hash function 108 and hash table 110 are shown in
From a security perspective, embodiments of the present invention may be examples of implementations of Physical Unclonable Functions (PUFs). A physical unclonable function, or PUF, is a “digital fingerprint” that serves as a unique identity for a semiconductor device such as memory device 102. PUFs are based on physical variations which occur naturally during semiconductor manufacturing, and which make it possible to differentiate between otherwise identical semiconductors. PUFs depend on the uniqueness of their physical microstructure. This microstructure depends on random physical factors introduced during manufacturing. These factors are unpredictable and uncontrollable, which makes it virtually impossible to duplicate or clone the structure. Rather than embodying a single cryptographic key, PUFs implement challenge-response authentication to evaluate this microstructure. When a physical stimulus is applied to the structure, it reacts in an unpredictable (but repeatable) way due to the complex interaction of the stimulus with the physical microstructure of the device. This exact microstructure depends on physical factors introduced during manufacture which are unpredictable. The applied stimulus is called the challenge, and the reaction of the PUF is called the response. A specific challenge and its corresponding response together form a challenge-response pair or CRP. The device's identity is established by the properties of the microstructure itself. As this structure is not directly revealed by the challenge-response mechanism, such a device is resistant to spoofing attacks. Using a key extractor, PUFs can also be used to extract a unique strong cryptographic key from the physical microstructure. The same unique key is reconstructed every time the PUF is evaluated. The challenge-response mechanism may then be implemented using known cryptographic methods.
In embodiments of the present invention, PUFs can be implemented with a very small hardware investment. Unlike a read only memory (ROM) containing a table of responses to all possible challenges, which would require hardware exponential in the number of challenge bits, a PUF can be constructed in hardware proportional to the number of challenge and response bits. A PUF's operation is initiated by a trusted entity (e.g., memory controller 104) sending out a challenge to another entity (e.g., memory device 102) that is subject to authenticity validation, and the response from the latter entity is compared against the results stored in trusted entity.
Unclonability means that each PUF device (i.e., a memory device) has a unique and unpredictable way of mapping challenges to responses, even if it was manufactured with the same process as a similar device, and it is infeasible to construct a PUF with the same challenge-response behavior as another given PUF because exact control over the manufacturing process is infeasible. Mathematical unclonability means that it should be very hard to compute an unknown response given the other CRPs or some of the properties of the random components from a PUF. This is because a response is created by a complex interaction of the challenge with many or all of the random components. In other words, given the design of the PUF system, without knowing all of the physical properties of the random components, the CRPs are highly unpredictable. The combination of physical and mathematical unclonability renders a PUF truly unclonable. Because of these properties PUB can be used as a unique and un-tamperable device identifier.
Embodiments of the present invention utilize these PUF concepts such that the memory controller (i.e., the trusted entity) utilizes the NVM die-specific characteristics which are gathered during a “Probe test” at a manufacturing facility. A Probe test is typically done at wafer level testing at a manufacturing facility, with the aim of detecting bad dies in a chip, and repairing the bad dies if possible with redundant elements. The memory controller executes the Probe test on-the-fly. If the memory device (i.e., the untrusted entity) has not been swapped since it was paired with the memory controller in a trusted environment (for example, as part of the manufacturing and/or testing process), the memory controller expects no differences between the results of the on-the-fly and the initial Probe tests; otherwise, the memory controller detects a NVM replacement.
In an embodiment, each NVM die in memory device 102 manufactured at a trusted manufacturing facility may get characterized by executing a Probe test and one or more of the die's parameters, for example a Demarcation Voltage (VDM), may be trimmed by die (“TBD”). TBD in this context refers to blowing unique fuse values based on a known “Shmoos” test to obtain a lower Raw Bit Error Rate (RBER) for the die by compensating for error variability. During a Shmoos test, a parameter is swept through an allowed span of values. These characteristics are unique per die and per fabrication process. In an embodiment, every die may contain approximately 20 TBD unique parameters.
Embodiments of the present invention modify one or more of these TBD parameters, and execute a Probe test flow “on-the-fly”. Embodiments of the present invention compare the results of “on-the-fly” Probe test flow with information previously gathered during the manufacturing process to validate the memory device. In one embodiment, computation of RBER may be used as an example of a manufacturing Probe test (i.e., the PUF), however in other embodiments, other Probe tests using other TBD parameters may be used.
Upon receiving the random bit string back from the memory device, the memory controller executes the Probe test at block 408 to determine the RBER (e.g., counts of the bit errors during the read operation without applying any Error Correction Code (ECC)). In an embodiment, the RBER comprises the Probe test results. In other embodiments, block 404 and 406 may be performed as part of the Probe test at block 408. The RBER will be calculated as it is shown on the y-axis of
Embodiments of the present invention use NVM die-specific information and the probe test flow to validate the authenticity of memory devices. An advantage of the presently disclosed embodiments is that it does not require any additional hardware resources, nor on-line communication capabilities. Embodiments utilize pre-existing memory device and memory controller hardware, and already available probe test results determined during the manufacturing process.
In embodiments, firmware in memory controller 104 may be sufficient for executing the challenge response protocol described herein and the associated validation. The amount of memory required for storing the post fabrication probe test results in the memory controller is insignificant. Further, embodiments of the present invention do not require any additional hardware and/or software resources to be added to the memory device.
According to some examples, as shown in
In some examples, storage controller 624 may include logic and/or features to receive a read or write transaction request to storage memory device(s) 622 at storage device 120. For these examples, the transactions may be initiated by or sourced from system software 617 that may, in some embodiments, utilize file system 613 to write data to storage device 620 through input/output (I/O) interfaces 603 and 623. In an embodiment, storage controller 624 may validate storage memory device(s) 622 as discussed with reference to
In some examples, storage memory device(s) 622 may be a device to store data from read and write transactions and/or read and write operations. Storage memory device(s) 622 may include one or more chips or dies having gates that may individually include one or more types of non-volatile memory to include, but not limited to, NAND flash memory, NOR flash memory, 3-D cross-point memory (3D XPoint™), ferroelectric memory, SONOS memory, ferroelectric polymer memory, FeTRAM, FeRAM, ovonic memory, nanowire, EEPROM, phase change memory, memristors or STT-MRAM. For these examples, storage device 620 may be arranged or configured as a solid-state drive (SSD). The data may be read and written in blocks and a mapping or location information for the blocks may be kept in memory 626.
According to some examples, communications between storage device driver 615 and storage controller 624 for data stored in storage memory devices(s) 622 and accessed via files 613-1 to 613-n may be routed through I/O interface 603 and I/O interface 623. I/O interfaces 603 and 623 may be arranged as a Serial Advanced Technology Attachment (SATA) interface to couple elements of host computing platform 610 to storage device 620. In another example, I/O interfaces 603 and 623 may be arranged as a Serial Attached Small Computer System Interface (SCSI) (or simply SAS) interface to couple elements of host computing platform 610 to storage device 620. In another example, I/O interfaces 603 and 623 may be arranged as a Peripheral Component Interconnect Express (PCIe) interface to couple elements of host computing platform 610 to storage device 620. In another example, I/O interfaces 603 and 623 may be arranged as a Non-Volatile Memory Express (NVMe) interface to couple elements of host computing platform 610 to storage device 620. For this other example, communication protocols may be utilized to communicate through I/O interfaces 603 and 623 as described in industry standards or specifications (including progenies or variants) such as the Peripheral Component Interconnect (PCI) Express Base Specification, revision 3.1, published in November 2014 (“PCI Express specification” or “PCIe specification”) or later revisions, and/or the Non-Volatile Memory Express (NVMe) Specification, revision 1.2, also published in November 2014 (“NVMe specification”) or later revisions.
In some examples, system memory device(s) 612 may store information and commands which may be used by circuitry 616 for processing information. Also, as shown in
In some examples, storage device driver 615 may include logic and/or features to forward commands associated with one or more read or write transactions and/or read or write operations originating from system software 617. For example, the storage device driver 615 may forward commands associated with write transactions such that data may be caused to be stored to storage memory device(s) 622 at storage device 620. More specifically, storage device driver 615 can enable communication of the write operations from system software 617 at computing platform 610 to controller 624.
System Memory device(s) 612 may include one or more chips or dies having volatile types of memory such RAM, D-RAM, DDR SDRAM, SRAM, T-RAM or Z-RAM. However, examples are not limited in this manner, and in some instances, system memory device(s) 612 may include non-volatile types of memory, including, but not limited to, NAND flash memory, NOR flash memory, 3-D cross-point memory (3D XPoint™), ferroelectric memory, SONOS memory, ferroelectric polymer memory, FeTRAM, FeRAM, ovonic memory, nanowire, EEPROM, phase change memory, memristors or STT-MRAM.
Persistent memory 619 may include one or more chips or dies having non-volatile types of memory, including, but not limited to, NAND flash memory, NOR flash memory, 3-D cross-point memory (3D XPoint™), ferroelectric memory, SONOS memory, ferroelectric polymer memory, FeTRAM, FeRAM, ovonic memory, nanowire, EEPROM, phase change memory, memristors or STT-MRAM.
According to some examples, host computing platform 610 may include, but is not limited to, a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, a personal computer, a tablet computer, a smart phone, multiprocessor systems, processor-based systems, or combination thereof.
Included herein is a set of logic flows representative of example methodologies for performing novel aspects of the disclosed architecture. While, for purposes of simplicity of explanation, the one or more methodologies shown herein are shown and described as a series of acts, those skilled in the art will understand and appreciate that the methodologies are not limited by the order of acts. Some acts may, in accordance therewith, occur in a different order and/or concurrently with other acts from that shown and described herein. For example, those skilled in the art will understand and appreciate that a methodology could alternatively be represented as a series of interrelated states or events, such as in a state diagram. Moreover, not all acts illustrated in a methodology may be required for a novel implementation.
A logic flow may be implemented in software, firmware, and/or hardware. In software and firmware embodiments, a logic flow may be implemented by computer executable instructions stored on at least one storage medium such as a non-transitory computer readable medium or machine readable medium, e.g., an optical, magnetic or semiconductor storage.
Examples of a computer readable or machine-readable storage medium may include any tangible media capable of storing electronic data, including volatile memory or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writeable or re-writeable memory, and so forth. Examples of computer executable instructions may include any suitable type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, visual code, and the like.
According to some examples, a component called circuitry 616 of
Host computing platform 610 may be part of a computing device that may be, for example, user equipment, a computer, a personal computer (PC), a desktop computer, a laptop computer, a notebook computer, a netbook computer, a tablet, a smart phone, embedded electronics, a gaming console, a server, a server array or server farm, a web server, a network server, an Internet server, a work station, a mini-computer, a main frame computer, a supercomputer, a network appliance, a web appliance, a distributed computing system, multiprocessor systems, processor-based systems, or combination thereof. Accordingly, functions and/or specific configurations of host computing platform 110 described herein, may be included or omitted in various embodiments of host computing platform 110, as suitably desired.
The components and features of host computing platform 610 may be implemented using any combination of discrete circuitry, ASICs, logic gates and/or single chip architectures. Further, the features of host computing platform 610 may be implemented using microcontrollers, programmable logic arrays and/or microprocessors or any combination of the foregoing where suitably appropriate. It is noted that hardware, firmware and/or software elements may be collectively or individually referred to herein as “logic”, “circuit” or “circuitry.”
Some examples may be described using the expression “in one example” or “an example” along with their derivatives. These terms mean that a particular feature, structure, or characteristic described in connection with the example is included in at least one example. The appearances of the phrase “in one example” in various places in the specification are not necessarily all referring to the same example.
Some examples may be described using the expression “coupled” and “connected” along with their derivatives. These terms are not necessarily intended as synonyms for each other. For example, descriptions using the terms “connected” and/or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. The term “coupled,” however, may also mean that two or more elements are not in direct contact with each other, but yet still co-operate or interact with each other.
It is emphasized that the Abstract of the Disclosure is provided to comply with 37 C.F.R. Section 1.72(b), requiring an abstract that will allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, in the foregoing Detailed Description, it can be seen that various features are grouped together in a single example for the purpose of streamlining the disclosure. This method of disclosure is not to be interpreted as reflecting an intention that the claimed examples require more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive subject matter lies in less than all features of a single disclosed example. Thus, the following claims are hereby incorporated into the Detailed Description, with each claim standing on its own as a separate example. In the appended claims, the terms “including” and “in which” are used as the plain-English equivalents of the respective terms “comprising” and “wherein,” respectively. Moreover, the terms “first,” “second,” “third,” and so forth, are used merely as labels, and are not intended to impose numerical requirements on their objects.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.