Claims
- 1. A method for patterning a layer overlying an oxide superconductor thin film, wherein said layer is etched by wet etching using a weak HF solution, a buffer solution that contains HF or a mixture that contains HF.
- 2. A method claimed in claim 1 wherein the HF concentration of the weak HF solution, the buffer solution including HF or the mixture including HF is 5 to 15 wt %.
- 3. A method for patterning an oxide superconductor thin film, comprising a step of forming a SiO.sub.2 layer on the oxide superconductor thin film, patterning the SiO.sub.2 layer so as to form the same pattern as that of the oxide superconductor thin film which will be patterned, etching the oxide superconductor thin film by using the patterned SiO.sub.2 layer as a mask, and removing the SiO.sub.2 layer by using a weak HF solution, a buffer solution including HF or a mixture including HF.
- 4. A method claimed in claim 3 wherein the SiO.sub.2 layer is patterned by using a weak HF solution, a buffer solution including HF or a mixture including HF.
- 5. A method of manufacturing a superconducting device, comprising the steps of forming on a principal surface of a substrate a non-superconducting oxide layer having a similar crystal structure to that of a c-axis oriented oxide superconductor thin film, forming a c-axis oriented oxide superconductor thin film having an extremely thin thickness on the non-superconducting oxide layer, forming an insulating layer on the c-axis oriented oxide superconductor thin film, forming a gate electrode of polycrystalline silicon on a center portion of the insulating layer, etching the insulating layer by using the gate electrode so as to form a gate insulating layer under the gate electrode and forming an a-axis oriented oxide superconductor thin film so as to embed the gate electrode and to form an insulating region by diffused silicon from the gate electrode, and etching back the a-axis oriented oxide superconductor thin film so that an upper surface of the a-axis oriented oxide superconductor thin film is planarized and the gate electrode is exposed at the planarized upper surface of the a-axis oriented oxide superconductor thin film and a superconducting source region and a superconducting drain region are formed at the both sides of the gate electrode.
- 6. A method claimed in claim 5 wherein the insulating layer is etched by using a weak HF solution, a buffer solution including HF or a mixture including HF.
Priority Claims (3)
Number |
Date |
Country |
Kind |
3-352196 |
Dec 1991 |
JPX |
|
3-352198 |
Dec 1991 |
JPX |
|
4-352660 |
Dec 1992 |
JPX |
|
Parent Case Info
This application is a division of application Ser. No. 07/990,836, filed Dec. 14, 1992, now U.S. Pat. No. 5,413,982.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4933318 |
Heijman |
Jun 1990 |
|
5219830 |
Jeong et al. |
Jun 1993 |
|
Foreign Referenced Citations (2)
Number |
Date |
Country |
0 506 570 |
Sep 1992 |
EPX |
2 661 557 |
Oct 1991 |
FRX |
Non-Patent Literature Citations (1)
Entry |
Eidelloth, W., et al., "Wet Etch Process for Patterning Insulators Suitable for Epitaxial High T.sub.c Superconducting Thin Film Multilevel Electronic Circuits", Applied Physics Letters, vol. 59, No. 10, pp. 1257-1259, Sep. 1991. |
Divisions (1)
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Number |
Date |
Country |
Parent |
990836 |
Dec 1992 |
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