Patent Application
20080070483
With the inventive method the local planarity achieved after the first polishing step, particularly in the edge region, can be preserved in the second polishing step and the global planarity can be improved, which leads overall to a planarity that satisfies the requirements of the component generation with a 32 nm line width. This is a surprising result, since the method described in the aforementioned DE 199 56 250 C1 and the method described in the aforementioned WO 00/47369 are not capable of doing this. Although in the case of DE 199 56 250 C1 the local planarity set up in the first polishing step is preserved after the second polishing step, the global planarity achieved in the first polishing step is however reduced in the second polishing step. In the case of WO 00/47369 the local planarity achieved by the first polishing step, particularly in the edge region, is reduced by the second polishing step.
A silicon semiconductor wafer produced by the method according to the invention has a planarity which could not previously be achieved. The invention therefore also relates to a silicon semiconductor wafer having a polished front side and a polished rear side with a front side global planarity expressed by an SBIRmax value of less than 100 nm, and with a front side local planarity expressed by a PSFQR value of 35 nm or less in an edge region, an edge exclusion of 2 mm being considered in each case. The SBIRmax value is furthermore related to a measurement field area of 26×33 mm and an arrangement of the measurement field grid with offsets of 13 and 16.5 mm in the x and y directions. The SBIRmax value describes the SBIR value of the measurement field with the greatest value among all the measurement fields. The specification of the PSFQR value relates to a measurement field area of 20×20 mm and an arrangement of the measurement field grid with an offset of 10 mm in both the x and y directions. The PSQR value is given by the sum of the PSFQR values of the partial sites divided by their number.
The starting product of the method is preferably a semiconductor wafer cut from a crystal, in particular from a silicon single crystal, which has been mechanically processed by lapping and/or grinding the side surfaces i.e. the front and rear sides of the semiconductor wafer. The front side refers to the side surface which is intended to form the surface for providing structured electronic components. The edge of the semiconductor wafer may already be rounded, in order to make it less sensitive to impact damage. Superficial damage due to the previous mechanical processing has furthermore been substantially removed by etching in an acidic and/or alkaline etchant. Furthermore, the semiconductor wafer may already have been subjected to further processing steps, in particular cleaning steps or polishing the edge. According to the claimed method the semiconductor wafer is polished simultaneously on both sides in a first polishing step, in which case in order to increase the productivity, DSP polishing is preferably carried out as multi-wafer polishing in which a plurality of carriers are used, each with a plurality of recesses for semiconductor wafers. A particular feature of the first DSP polishing is that a negative overhang is achieved, the overhang being the difference D1W-D1L between a thickness D1W of the semiconductor wafer after polishing has been concluded and a thickness D1L of the carrier used for polishing the semiconductor wafer. The overhang is preferably less than 0 μm to −4 μm, more preferably −0.5 to −4 μm, and preferably from 15 μm to 30 μm of material is abraded from the side surfaces overall. The effect of the first polishing step is that the semiconductor wafer is curved concavely in a horizontally symmetrical way, so that the SBIR values lie in an unfavorably regarded range of more than 100 nm, and the SFQR values describing the local planarity, particularly the PSFQR values of the semiconductor wafer already lie in a favorably regarded range of 35 nm or less. The aim of the second polishing step, which is likewise carried out as DSP polishing, is to improve the global planarity and to preserve or likewise improve the local planarity already achieved, especially that in the edge region. A particular feature of the second DSP polishing is that the desired effect is achieved by polishing less than 1 μm of material overall from the two sides of the semiconductor wafer. The averaged material abrasion lies in the range of less than 1 μm, preferably in a range of from 0.2 μm to less than 1 μm. The indicated upper limit should not be exceeded because this would detrimentally affect the global planarity of the semiconductor wafer. It is furthermore preferable to achieve an overhang which is ≧0 μm, the overhang being the difference D2W-D2L between a thickness D2W of the semiconductor wafer after the polishing has been concluded and a thickness of the carrier D2L used for polishing the semiconductor wafer. The overhang is more preferably from 0 to 2 μm. The effect of the second polishing step is that the SBIR values lie in a favorably regarded range of less than 100 nm, and that the SFQR values describing the local planarity, and in particular the PSFQR values, lie in a favorably regarded range of 35 nm or less.
After the first polishing step, according to a preferred embodiment of the invention, the semiconductor wafer's concavity thereby achieved is determined, for example by measuring the GBIR value. The measured value is used as an input value for calculating the duration of the second polishing step, via which the material abrasion to be achieved by the second polishing step is in turn established. In this way, the planarity of the semiconductor wafer is further optimized. The optimal duration D of the second polishing step is preferably calculated according to the formula: D=(GBIR:RT)+Offset, where RT is the typical abrasion rate in μm/min of the polishing machine being used and Offset is a correction value which depends on the polishing process being used and therefore needs to be determined empirically.
The invention will be explained in more detail below with the aid of figures and comparative examples.
The different effects of the first and second polishing steps are represented in
Silicon semiconductor wafers having a diameter of 300 mm were cut from a single crystal and respectively pretreated in the same way by mechanical processing and etching. They were subsequently polished in a type AC 2000 double-sided polishing machine from Peter Wolters AG, until a negative overhang (underhang) had been reached (Example E and comparative example C2) or until a positive overhang (comparative example C1) had been reached. Some of the semiconductor wafers (C1) were subsequently subjected to a second DSP polishing, which was concluded with a positive overhang and material abrasion of more than 1 μm. Other semiconductor wafers (C2) were subjected to CMP polishing, which was concluded with material abrasion of less than 1 μm. The rest of the semiconductor wafers (E) were likewise subjected to a second DSP polishing, which was concluded with material abrasion of less than 1 μm. The results of planarity measurements, which were carried out with a type AFS contactlessly measuring meter from ADE Corp. after the polishing steps, are collated in the following table.
While embodiments of the invention have been illustrated and described, it is not intended that these embodiments illustrate and describe all possible forms of the invention. Rather, the words used in the specification are words of description rather than limitation, and it is understood that various changes may be made without departing from the spirit and scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2006 044 367.5 | Sep 2006 | DE | national |
