Patent Application
20050086616
This invention relates in general to the field of electronics and more specifically to a method for optimizing printed circuit board panelization.
A major factor in determining the cost of an individual Printed Circuit Board (PCB) is the configuration and orientation of multiple PCBs onto a factory array, and the configuration and orientation of multiple factory arrays onto a PCB panel such as a PCB vendor's panel. This process of fitting PCBs into arrays and arrays into panels is typically referred to as panelization. The factory array refers to the connected array of individual PCBs that pass through an electronic manufacturing line during electronic component placement (e.g., surface mount technology placement, etc.). The panel refers to a connected matrix of factory arrays that are built in a single sheet by a PCB vendor.
Although most electronic device manufacturers receive factory arrays from their PCB vendors, it is important to consider the vendor's panel design in any optimization efforts in order to insure that the lowest cost configuration is achieved. Efficient usage of panels leads to lower costs for the individual PCBs since less material is wasted. The goal of any PCB panelization effort is to find the optimal configuration of PCBs in arrays, and arrays in panels which maximize the overall utilization of the vendor's panels. This insures minimal wasted materials and therefore minimal costs. However, finding the optimal configuration is a non-trivial task for some of the following enumerated reasons:
Historically, designing a PCB panelization solution has involved repetitively simulating many potential panelization solutions. Typically a person wanting to perform a panelization optimization has to run a different analysis for each of the possible vendor panel sizes and for each of the vendor manufacturing capability specifications. Because of all of the possible combinations, this approach can be very time consuming and the user may never achieve an optimal solution. Given the above, a need exists in the art for a method of panelization that can minimize some of the short comings found in the prior art.
The features of the present invention, which are believed to be novel, are set forth with particularity in the appended claims. The invention may best be understood by reference to the following description, taken in conjunction with the accompanying drawings, in the several figures of which like reference numerals identify like elements, and in which:
While the specification concludes with claims defining the features of the invention that are regarded as novel, it is believed that the invention will be better understood from a consideration of the following description in conjunction with the drawing figures.
In one embodiment of the present invention, a PCB panel optimization method comprises a web based software tool that finds the optimal configuration of PCBs on arrays and arrays on panels which maximizes the panel utilization while at the same time enforcing all required design specifications from both the panel vendor and product manufacturer standpoints. Although this embodiment will be discussed in relation to a web based software tool, the present invention can also be utilized in stand-alone, networked computer systems, or other hardware devices that can execute the panelization tool (panelization method).
The panelization method can be used to optimize the panel dimension and array size selections and find the optimal solution that makes the cost per PCB minimum. In other words, the selected panel and array dimensions are selected to obtain the highest panel utilization, or that achieves the highest Panel Efficiency Factor (PEF), which is defined as:
PEF=(Area of PCB*number of PCBs in Array*number of Arrays in Panel÷Area of Panel
Referring now to
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Computerized linkage to PCB vendor manufacturing requirements as well as to the user's own panelization specifications can also be included in accordance with an embodiment of the invention. For example, vendor panel specifications can be downloaded from the vendor's computer system and the specifications can be used as inputs to the panelization analysis.
In step 404, the panel dimension is selected from a group of potential panel sizes, for example, those available from a particular PCB vendor. In decision step 406, the routine determines if the panel search is completed. If the panel search is not completed, the routine moves to step 408, where the array length is initialized. For example, the array length variable is cleared (e.g., set to zero). If in decision step 406, the routine determines that the panel search has been completed, the routine moves to step 424, wherein the results for all panel utilization results are compared and the one with the best efficiency factor is selected as the optimized solution. The optimization process will provide the panel dimensions and array sizes, spacing, border and all other dimensional information relating to the utilization result or results that yielded the best efficiency factor.
Alternatively, in another embodiment, the optimization routine can provide a number of utilization results (e.g., top 5 utilization results based on the efficiency factors) and their corresponding efficiency factors and dimensional information. This alternative approach would allow the person performing the utilization study to select from a number of available panalization solutions with information on their corresponding efficiency factors. It may be that a person may be willing to give up a bit of efficiency for some reason, and this multiple solution approach would allow the user to make such a cost-benefit analysis.
In step 410, the array length is indexed or increased by a predetermined amount, and in decision step 412 it is determined if the array length search is complete. Decision step 412 may determine that the array length search is complete, if for example, the maximum array length is reached. If the array length search is not complete, the process moves to step 414 wherein the array width is initialized (array width variable cleared). If in step 412, it is determined that the array length search is complete, the routine returns to step 404. In step 416, the array width is indexed or increased by a predetermined amount.
In decision step 418, it is determined if the array width search is complete, for example by determining if the array width dimension has been increased to the maximum array width previously entered as an input in step 402. If in step 418, it is determined that the array width search is complete (maximum width reached) the routine moves back to step 410 where the array length is indexed or increased by a predetermined amount. If the array width search is determined not to be complete, in step 420, the PCB is panelized in an array and the array is panelized in the panel applying the spacing and border specifications. In step 422, the total efficiency factor for a particular array width and length is computed and stored. After step 422, the routine loops back to step 416 wherein the array width is indexed or increased in value by a predetermined amount (e.g., one millimeter, etc.).
If in step 406 it is determined that the panel search is completed, the routine moves to step 424, wherein the results are compared and the best panel efficiency factor is determined and its panel dimension and optimized array size and spacing information results are provided.
The optimal panel search algorithm discussed in relation to
For every selected panel dimension and array size, as many as possible arrays are populated on the panel while applying the array spacing and panel border specifications provided. For every selected array size, as many as possible PCBs are populated on the array while applying PCB spacing and array border specifications provided. The total panel efficiency factor or cost per PCB is determined for every case and all of the above results are compared and the best solution or solutions are selected and reported to the user. The best solution has the highest total efficiency factor or lowest cost per PCB. The dimensions of the optimal panel and array sizes are reported to the user. Also, the layouts of the optimal arrays on the optimal panel and the layout of PCBs on the optimal array are generated.
In one embodiment of the invention, the ability to execute many panelization simulations is enabled by using a high speed rectangle nesting algorithm. In cases where complex polygon nesting is employed, the nested board set is modeled by its bounding rectangle in order to employ the high speed rectangle nesting algorithm. This approach enables true board outline polygon nesting (typically a much slower calculation) while still allowing for the use of the high speed nesting approach in order to find the optimal panelizaiton solution within a reasonable period of time (e.g., 4 minutes).
In a typical panelization optimization using the method described herein, it is not uncommon to perform 50,000 panelization simulations, with the panel utilization results calculated and saved for later analysis. Preferably, the PCB outline description is imported using Computer Aided Design (CAD) files and non-overhanging parts located on the PCB are filtered out prior to commencing the optimization analysis.
Once all simulations are completed, the solution set is complete and ready to be used to find the optimal solution, as well as perform sensitivity analysis solutions that may provide superior results. For example, the routine may inform the person performing the analysis that if the panel could be increased by a certain amount, the efficiency factor could be increased by a predetermined amount more. It would be then up to the person performing the analysis if it is worthwhile to make such an adjustment.
On occasions, there may be cases where multiple solutions yield the same panel utilization results (e.g., have equal efficiency factors), in these cases, while all of the optimal solutions are provided to the user in order for a choice to be made, the typically recommended optimal solution is the solution which yields the highest panel utilization while at the same time maintaining the largest array size. This is the preferred solution since it gives the PCB designer the most flexibility for adding larger support ribs on the factory array and for adapting to potential board size increases in later design revisions. A graphical drawing (see for example item 812 in
The dimensional specifications mentioned above and other specifications that can be selected as inputs to the panelization algorithm can be entered using a Graphical User Interface (GUI) such as that shown in
The next input block is the PCB panel size specification block 504 which highlights the different panel sizes the result will be selected from. The next block in the GUI is the PCB factory array size specification block 506, which lets the user select a fixed array size having a predetermined length and width, or allow the user to have the panelization software make an optimization determination using maximum and minimum information for both the array length and the array width. The user can also select if he/she wants the panelization algorithm to determine the maximum arrays that can be placed in a panel for optimal layout.
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Referring now to
A unique feature of the panelization routine is its ability to import a component file generated by a board layout software tool in order to include any components that are overhanging from the board outline into the simulation. The optimization routine can analyze all parts in the bill of materials for a particular PCB in order to include any components that are overhanging from the board outline into the simulation. Simulations have shown that the panel optimization routine leads to an approximately 5% to 10% improvement in panel utilization which translates into a 5-10% reduction in PCB cost.
While the preferred embodiments of the invention have been illustrated and described, it will be clear that the invention is not so limited. Numerous modifications, changes, variations, substitutions and equivalents will occur to those skilled in the art without departing from the present invention as defined by the appended claims.
