1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to a method for process integration of non-volatile memory (NVM) cell transistors with transistors of another type.
2. Related Art
Many semiconductor devices include, or embed, non-volatile memory transistors with other transistor types on the same integrated circuit (IC). The manufacturing processes for the different transistor types may not be the same, requiring that the processes be integrated. For example, to integrate NVM with, for example, CMOS (complementary metal oxide semiconductor), the CMOS process may be modified to include the process steps necessary to fabricate the NVM memory cell and the supporting devices such as peripheral high voltage (HV) transistors and low voltage (LV) transistors.
In most embedded NVMs, information is stored as charge on a “floating gate” which is completely surrounded by insulators, and which affects the threshold voltage of a transistor such that one bit of information corresponds to its on- and off-state. Charge is moved into and out of the floating gate by physical mechanisms such as hot-carrier injection or tunneling. Either method requires voltages higher than the core supply voltage. Using contemporary technology, a potential of approximately ±9 volts is required. To support these elevated voltages, the peripheral HV transistors are built with thicker-than-nominal gate oxides, and charge pump circuits are employed to generate the high voltages from the chip supply voltage.
Flash NVM is commonly embedded in, for example, system-on-a-chip (SoC) integrated circuits having both HV and LV transistors. In a semiconductor fabrication process for forming the embedded flash memory on an IC with HV transistors using two polysilicon layers, a first polysilicon layer may be used to form the non-volatile memory cell floating gates and the HV transistor gates. Or the first polysilicon layer may be used to form the memory cell floating gates while a second polysilicon layer is patterned to produce HV transistor gates. Additionally, the second polysilicon layer may also be used to form the LV transistor gates. The flash NVM may have an ONO (oxide-nitride-oxide) insulating layer between the floating gate and the control gate. The ONO layer is removed from the HV transistor gates. However, in some semiconductor fabrication processes undesirable ONO sidewall spacers may be formed on the sides of the HV transistor gates that are not easily removed. The presence of the ONO spacers may cause reliability issues with the HV transistors because charge traps in the nitride may cause unstable operation. An additional isotropic dry etch or an isotropic wet BOE (buffered oxide etchant) etch can be used to remove the ONO spacers. However, using an etch process to remove the ONO spacers adds additional process steps that increase manufacturing time and expense. Also, the unwanted ONO spacers on the sidewall can lift off during further processing, raising the level of contamination and defectivity for the semiconductor device.
The present invention is illustrated by way of example and is not limited by the accompanying figures, in which like references indicate similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.
Generally, in one embodiment, the present invention provides a method for making a semiconductor device having non-volatile memory cell transistors, high voltage CMOS transistors, low voltage CMOS transistors, and having two polysilicon layers, where the non-volatile memory cell floating gates and the HV transistors are formed on a substrate using a first, or lower, polysilicon layer, and the LV transistors are formed using a second, or upper, polysilicon layer. The method includes forming a gate dielectric layer on the HV and LV regions. A tunnel oxide layer is formed under the substrate in the NVM region and over the gate dielectric in the HV and LV regions. A first polysilicon layer is formed over the tunnel dielectric layer and gate dielectric layer. The first polysilicon layer is patterned to form NVM floating gates. An ONO layer is formed over the first polysilicon layer. A single etch removal step is used to form one or more gates for the HV transistors from the first polysilicon layer while completely removing the first polysilicon layer in the LV region. By forming the ONO layer before patterning the HV region gates, unwanted ONO sidewall spacers are not formed, thus eliminating the need for an additional etch process step and reducing the possibility of unstable HV transistors. Also, removing the unwanted ONO spacers eliminates the problem with ONO spacers on the sidewall lifting off during further processing.
By now it should be appreciated that there has been provided, a process integration that results in low voltage transistors using the second polysilicon layer, high voltage transistors using the first polysilicon layer, and in which the high voltage transistors sidewalls have not been exposed to ONO deposition, preserving their integrity.
Moreover, the terms “front,” “back,” “top,” “bottom,” “over,” “under” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.
Although the invention is described herein with reference to specific embodiments, various modifications and changes can be made without departing from the scope of the present invention as set forth in the claims below. Accordingly, the specification and figures are to be regarded in an illustrative rather than a restrictive sense, and all such modifications are intended to be included within the scope of the present invention. Any benefits, advantages, or solutions to problems that are described herein with regard to specific embodiments are not intended to be construed as a critical, required, or essential feature or element of any or all the claims.
Furthermore, the terms “a” or “an,” as used herein, are defined as one or more than one. Also, the use of introductory phrases such as “at least one” and “one or more” in the claims should not be construed to imply that the introduction of another claim element by the indefinite articles “a” or “an” limits any particular claim containing such introduced claim element to inventions containing only one such element, even when the same claim includes the introductory phrases “one or more” or “at least one” and indefinite articles such as “a” or “an.” The same holds true for the use of definite articles.
Unless stated otherwise, terms such as “first” and “second” are used to arbitrarily distinguish between the elements such terms describe. Thus, these terms are not necessarily intended to indicate temporal or other prioritization of such elements.
Number | Name | Date | Kind |
---|---|---|---|
4651406 | Shimizu et al. | Mar 1987 | A |
RE34535 | Paterson et al. | Feb 1994 | E |
5620920 | Wilmsmeyer | Apr 1997 | A |
5723355 | Chang et al. | Mar 1998 | A |
5888869 | Cho et al. | Mar 1999 | A |
6159799 | Yu | Dec 2000 | A |
6162683 | Chen | Dec 2000 | A |
6165846 | Carns et al. | Dec 2000 | A |
6399443 | Chwa et al. | Jun 2002 | B1 |
6455374 | Lee et al. | Sep 2002 | B1 |
6483749 | Choi et al. | Nov 2002 | B1 |
6503800 | Toda et al. | Jan 2003 | B2 |
6534363 | Kim | Mar 2003 | B2 |
6569742 | Taniguchi et al. | May 2003 | B1 |
6689653 | Seah et al. | Feb 2004 | B1 |
6900097 | Chen et al. | May 2005 | B2 |
7179709 | Kim et al. | Feb 2007 | B2 |
7241662 | Wolstenholme et al. | Jul 2007 | B2 |
7262102 | Wolstenholme et al. | Aug 2007 | B2 |
20010045590 | Kobayashi | Nov 2001 | A1 |
20030032244 | Peschiaroli et al. | Feb 2003 | A1 |
20040169250 | Kobayashi | Sep 2004 | A1 |
20050079662 | Miki | Apr 2005 | A1 |
20050221558 | Lee | Oct 2005 | A1 |
20050230741 | Tsunoda et al. | Oct 2005 | A1 |
20060019446 | Yang | Jan 2006 | A1 |
20060035432 | Kim et al. | Feb 2006 | A1 |
20060110942 | Lee | May 2006 | A1 |
20070184606 | You et al. | Aug 2007 | A1 |
20070290252 | Koo et al. | Dec 2007 | A1 |
20080014701 | Tsunoda et al. | Jan 2008 | A1 |
20080036008 | Hirase et al. | Feb 2008 | A1 |