Method for Processing Digital Signals, and Transmission/Reception System Implementing Said Method

Abstract

The present invention relates to a method for processing digital signals and to a transmission/reception system implementing said method; the present invention is based on the use of LDPC codes, in particular the LDPC code of the DVB-S2 standard, in combination with a QAM modulation, in particular the 1024QAM and 4096QAM modulations; in transmission, a bit permutation (Demux) is carried out prior to the QAM constellation mapping function; in reception, the bit permutation is carried out after the QAM constellation demapping function.

Description

The present invention relates to a method for processing digital signals and to a transmission/reception system that implements said method.

The invention is intended mainly, but not exclusively, for receiving and transmitting digital audio and video signals, in particular those involved in the broadcasting of second-generation digital television signals over cable networks.

In order to protect the signals from the distortions of the transmission channel, the second-generation system for broadband satellite broadcasting (DVB-S2) utilizes the LDPC (Low Density Parity Check) encoding associated with the QPSK, 8PSK, 16APSK and 32APSK modulations, respectively shown in sequence in FIG. 1 from top to bottom and from left to right, which are suitable for transmission over a non-linear channel such as the satellite one. A description of the DVB-S2 standard and LDPC codes can be found, for example, in A. Morello, V. Mignone, “DVB-S2: The Second Generation Standard for Satellite Broad-band Services”, Proceedings of the IEEE, Volume 94, Issue 1, Jan. 2006, pages 210-227.

For the purpose of better exploiting the potentiality of the codes, the DVB-S2 standard provides that an interleaver is interposed between the LDPC encoder and the 8PSK, 16APSK and 32APSK constellation mapper in order to achieve an improved association between the bits of the encoded word and the bits carried by the constellation points.

In the interleaver defined in the DVB-S2 standard, shown in FIG. 2, the encoded packet outputted by the LDPC encoder (formed by a number of bits equal to 16,200 or 64,800, which number is generally referred to with the symbol “N_FRAME”) is written by columns in a matrix having N columns, where N is the number of bits carried by the constellation (N is 3 for 8PSK, 4 for 16APSK, 5 for 32APSK), and N_FRAME/N rows, and is read by rows; reading takes place from left to right for all code rates provided by the standard, with the exception of the ⅗ rate, where reading takes place from right to left in the case of 8PSK modulation. The association with the constellation points or coordinates takes place as shown in FIG. 1.

Following the current trend in the broadcasting of second-generation digital terrestrial television signals, it has recently been thought of using the same encoding scheme as that employed in the DVB-S2 standard, i.e. the same LDPC codes, also for the reception and transmission of numerical audio and video signals involved in the broadcasting of second-generation digital television signals over cable networks, however associated with QAM (Quadrature Amplitude Modulation) modulations; in particular, cable network broadcasting utilizes the 1024QAM and 4096QAM modulations (FIG. 3b).

The Applicant has realised that, with QAM modulations, the performance offered by the LDPC codes of the DVB-S2 standard are good but not wholly satisfactory as to the signal-to-noise ratio (SNR) required for reaching the QEF (Quasi Error Free) condition; as known, such a condition corresponds to the case wherein less than one error is received per hour of received program.

The general object of the present invention is to solve the above-mentioned problem and, in particular, to improve the association between the bits outputted by the LDPC encoder and the constellation coordinates of QAM modulations; more in particular, the present invention deals with the LDPC encoding according to the DVB-S2 standard and with the 1024QAM and 4096QAM modulations.

Said objects are achieved through the method for processing digital signals and the transmission/reception system having the features set out in the appended claims, which are intended as an integral part of the present description.

The invention will now be described in detail in some of its preferred embodiments, which are provided herein by way of non-limiting example, by referring to the annexed drawings, wherein:

FIG. 1 is a schematic representation of the QPSK, 8PSK, 16APSK and 32APSK constellations included, among others, in the DVB-S2 standard;

FIG. 2 is an explanatory diagram of an interleaver provided by the DVB-S2 standard, with reference to 8PSK modulation;

FIG. 3 is a schematic representation of the QPSK, 16QAM, 64QAM and 256QAM constellations applicable to the reception and transmission of audio and video signals involved in the broadcasting of second-generation digital television signals over cable networks;

FIG. 3 b is a schematic representation of the 1024QAM and 4096QAM constellations applicable to the reception and transmission of audio and video signals involved in the broadcasting of second-generation digital television signals over cable networks;

FIG. 4 is a much simplified block diagram of a system for processing a modulating digital signal according to the present invention;

FIG. 5 is an explanatory general diagram of the interleaver of FIG. 4;

FIGS. 6 a to 6d schematically show the function carried out by the “Demux” block of FIG. 4 according to four preferred embodiments of the present invention relating to 1024QAM modulation;

FIGS. 7 a to 7d schematically show the function carried out by the “Demux” block of FIG. 4 according to four preferred embodiments of the present invention relating to 4096QAM modulation;

FIGS. 8 a to 8d show the method used for obtaining the function carried out by the “Demux” block of FIG. 4 according to the diagram shown in FIG. 6a;

FIGS. 9 a to 9d show the method used for obtaining the function carried out by the “Demux” block of FIG. 4 according to the diagram shown in FIG. 7a;

FIGS. 10 a to 10m show the mapping of the real and imaginary portions of the points of the QPSK, 16QAM, 64QAM, 256QAM, 1024QAM and 4096QAM constellations applicable to the reception and transmission of audio and video signals involved in the broadcasting of second-generation digital television signals over cable networks, wherein z_q designates the vector that identifies the constellation point in the complex plane, with a real portion Re(z_q) and an imaginary portion Im(z_q), whereas y_i,q designates the i^th bit of the group of N bits which is mapped to the constellation point identified by z_q (for 4096QAM, for example, N=12 and i=0, 1, 2, . . . , 10, 11).

Referring now to FIG. 4, there is shown a much simplified block diagram of a system for processing a modulating digital signal, wherein an “Encoder” block receives a modulating information stream and outputs an encoded information stream organised in packets consisting of N_FRAME bits, which may be either 64,800 or 16,200; the code employed is the LDPC code of the DVB-S2 standard.

In an “Interleaver” block, said packets are written into an interleaving matrix having a total size N_FRAME; said matrix is constituted by m×N columns and N_FRAME/m×N rows.

A “Demux” block carries out a permutation of the bits received from the “Interleaver” block; such bits are received by the interleaving matrix in groups of m×N bits at a time, where N is the number of bits carried by the constellation (N=10 for 1024QAM, N=12 for 4096QAM), and “m” is an integer greater than or equal to 1. The “Demux” block associates them in m groups of N bits and permutes them according to predetermined schemes by taking into account the type of modulation (i.e. the QAM level), the code and the type of transmission channel, and then it outputs them.

A “Mapper” block associates the N-ples of bits outputted by the “Demux” block with the points or coordinates of the constellation, e.g. as shown in FIGS. 3a and 3b and in FIGS. 10a to 10m for QAM modulations.

It is worth pointing out that the blocks shown in FIG. 4 are only those which are essential for understanding the present invention; it should not therefore be excluded the presence of intermediate blocks, e.g. located between the “Demux” block and the “Mapper” block, adapted to perform specific signal processing functions.

The present invention proposes particular permutation schemes which may be adopted for the QAM modulations and LDPC codes having different code rates provided, for example, by the DVB-S2 standard in association with different types of interleaving.

The preferred embodiment of the present invention refers to the 1024QAM and 4096QAM modulations and to the LDPC code of the DVB-S2 standard.

The preferred embodiment of the present invention employs an interleaver which is equal or similar to the one of the DVB-S2 standard as shown in FIG. 2, with a number of bits/columns dependent on the QAM modulation level type.

The present invention provides for using a matrix interleaver in the form of a matrix having 2×N columns and N_FRAME/(2×N) rows, written by columns from top to bottom and read by rows from left to right. In this case, the “Demux” block operates with m equal to 2.

For 1024QAM modulation, the 2×N bits inputted to the “Demux” block are permuted as specified in any of FIGS. 6a to 6d, and are associated with 2 consecutive symbols of 1024QAM modulation.

Given the 2×N bits b0 to b19, the 2×N bits carried by the 1024QAM constellation y0 to y19 are determined by applying the method described in detail below.

A first symbol consists of the bits b0, b2, b4, b6, b8, b10, b12, b14, b16, b18, and a second symbol consists of the bits b1, b3, b5, b7, b9, b11, b13, b15, b17, b19. Each symbol is mapped individually by arranging the bits first on the in-phase portion (I) from the least significant bit (LSB) to the most significant bit (MSB), and subsequently on the quadrature portion (Q) from the MSB to the LSB, as shown in FIG. 8a. I_b,1 and Q_b,1 respectively designate the arrays of bits associated with the bits I_y1 carried by the in-phase component and with the bits Q_y1 carried by the quadrature component of the first symbol; I_b2, Q_b2, I_y2, Q_y2 have the same meaning for the second symbol.

As an alternative, the bits may be associated with the QAM symbols as follows: I_y,1=I_b,2, Q_y,1=Q_b,2, I_y,2=I_b,1, Q_y,2=Q_b,1.

The bits belonging to the pairs (b1,b3) and (b11,b19) are then exchanged; FIG. 8b will thus be obtained from the example shown in FIG. 8a.

The two symbols are then interlaced in terms of in-phase and quadrature portions, e.g. as shown in FIG. 8c, which is obtained from the example of FIG. 8b.

As an alternative, the bits may be associated with the QAM symbols as follows: I_y,1=I_b,2, Q_y,1=Q_b,1, I_y,2=I_b,1, Q_y,2=Q_b,2.

Afterwards, the bits associated with the even locations y2, y6, y10, y14, y18 or odd locations y0, y4, y8, y12, y16 on the in-phase portion are respectively exchanged with those associated with the even locations y3, y7, y11, y15, y19 or odd locations y1, y5, y9, y13, y17 on the quadrature portion. FIG. 8d will thus be obtained from the example shown in FIG. 8c.

A first preferred embodiment relating to the 1024QAM constellation is the one listed in FIG. 8d and illustrated in FIG. 6a, according to which, given the 2×N bits b0 to b19, the 2×N bits carried by the 1024QAM constellation y0 to y19 are determined as follows:

y0=b8, y1=b19, y2=b13, y3=b6, y4=b4, y5=b15, y6=b17, y7=b2, y8=b0, y9=b11, y10=b10, y11=b9, y12=b7, y13=b12, y14=b14, y15=b5, y16=b1, y17=b16, y18=b18, y19=b3where b0 and y0 are the most significant bits [MSB], and b19 and y19 are the least significant bits [LSB].

In particular, the “Mapper” block receives the bits y0 to y9 first, followed by the bits y10 to y19.

By using the above-mentioned alternatives, three more preferred embodiments can be obtained.

The second preferred embodiment is the one shown in FIG. 6b, wherein the bits y0 to y19 are determined as follows:

y0=b19, y1=b8, y2=b6, y3=b13, y4=b15, y5=b4, y6=b2, y7=b17, y8=b11, y9=b0, y10=b9, y11=b10, y12=b12, y13=b7, y14=b5, y15=b14, y16=b16, y17=b1, y18=b3, y19=b18.

The third preferred embodiment is the one shown in FIG. 6c, wherein the bits y0 to y19 are determined as follows:

y0=b9, y1=b10, y2=b12, y3=b7, y4=b5, y5=b14, y6=b16, y7=b1, y8=b3, y9=b18, y10=b19, y11=b8, y12=b6, y13=b13, y14=b15, y15=b4, y16=b2, y17=b17, y18=b11, y19=b0.

The fourth preferred embodiment is the one shown in FIG. 6d, wherein the bits y0 to y19 are determined as follows:

y0=b10, y1=b9, y2=b7, y3=b12, y4=b14, y5=b5, y6=b1, y7=b16, y8=b18, y9=b3, y10=b8, y11=b19, y12=b13, y13=b6, y14=b4, y15=b15, y16=b17, y17=b2, y18=b0, y19=b11.

Still referring to the case wherein the “Demux” block operates with m equal to 2, there are some permutations which have proven to be advantageous for the 4096QAM constellation; the 2×N bits inputted to the “Demux” block are permuted as specified in any of FIGS. 7a to 7d, for 4096QAM modulation encoded according to the LDPC code of the DVB-S2 standard, and are associated with two consecutive symbols of 4096QAM modulation. The method for obtaining the configurations shown in FIGS. 7a to 7d will now be described in detail.

Given the 2×N bits b0 to b23, a first symbol consists of the bits b0, b2, b4, b6, b8, b10, b12, b14, b16, b18, b20, b22, and a second symbol consists of the bits b1, b3, b5, b7, b9, b11, b13, b15, b17, b19, b21, b23. Each symbol is mapped individually by arranging the bits first on the in-phase portion (I) from the LSB to the MSB, and subsequently on the quadrature portion (Q) from the MSB to the LSB, as shown in FIG. 9a.

As an alternative, the bits may be associated with the QAM symbols as follows: I_y,1=I_b,2, Q_y,1=Q_b,2, I_y,2=I_b,1, Q_y,2=Q_b,1.

The bits belonging to the pairs b1,b3 and b13,b23 are then exchanged; FIG. 9b will thus be obtained from the example shown in FIG. 9a.

The two symbols are then interlaced in terms of in-phase and quadrature portions; for example, the table of FIG. 9c will thus be obtained from FIG. 9b.

As an alternative, the bits may be associated with the QAM symbols as follows: I_y,1=I_b,2, Q_y,1=Q_b,1, I_y,2=I_b,1, Q_y,2=Q_b,2.

Afterwards, the bits associated with the even locations y2, y6, y10, y14, y18, y22 or odd locations y0, y4, y8, y12, y16, y20 on the in-phase portion are respectively exchanged with those associated with the even locations y3, y7, y11, y15, y19, y23 or odd locations y1, y5, y9, y13, y17, y21 on the quadrature portion. For example, the table of FIG. 9d will thus be obtained from FIG. 9c.

A first preferred embodiment relating to the 4096QAM constellation is the one listed in FIG. 9d and illustrated in FIG. 7a, according to which, given the 2×N bits b0 to b23, the 2×N bits carried by the 4096QAM constellation y0 to y23 are determined as follows:

y0=b10, y1=b23, y2=b15, y3=b8, y4=b6, y5=b17, y6=b19, y7=b4, y8=b2, y9=b21, y10=b13, y11=b0, y12=b11, y13=b12, y14=b14, y15=b9, y16=b7, y17=b16, y18=b18, y19=b5, y20=b1, y21=b20, y22=b22, y23=b3

By using the above-mentioned alternatives, three more preferred embodiments can be obtained. The second preferred embodiment is the one shown in FIG. 7b, wherein the bits y0 to y23 are determined as follows:

y0=b23, y1=b10, y2=b8, y3=b15, y4=b17, y5=b6, y6=b4, y7=b19, y8=b21, y9=b2, y10=b0, y11=b13, y12=b12, y13=b11, y14=b9, y15=b14, y16=b16, y17=b7, y18=b5, y19=b18, y20=b20, y21=b1, y22=b3, y23=b22

The third preferred embodiment is the one shown in FIG. 7c, wherein the bits y0 to y23 are determined as follows:

y0=b11, y1=b12, y2=b14, y3=b9, y4=b7, y5=b16, y6=b18, y7=b5, y8=b1, y9=b20, y10=b22, y11=b3, y12=b10, y13=b23, y14=b15, y15=b8, y16=b6, y17=b17, y18=b19, y19=b4, y20=b2, y21=b21, y22=b13, y23=b0

The fourth preferred embodiment is the one shown in FIG. 7d, wherein the bits y0 to y23 are determined as follows:

y0=b12, y1=b11, y2=b9, y3=b14, y4=b16, y5=b7, y6=b5, y7=b18, y8=b20, y9=b1, y10=b3, y11=b22, y12=b23, y13=b10, y14=b8, y15=b15, y16=b17, y17=b6, y18=b4, y19=b19, y20=b21, y21=b2, y22=b0, y23=b13

The above-described methods may be used to advantage in a system for transmitting digital signals based on a 1024QAM or 4096QAM modulator, and particularly in an audio/video digital signal transmitter for broadcasting digital television signals over cable networks.

As is apparent to those skilled in the art, if the above-described method is applied in transmission, a reverse method will have to be applied in reception.

As known, the transmission of television signals is carried out by radio frequency transmitters, while the reception of television signals occurs through television receivers typically installed in the television service users' homes.

Claims

1. Method for processing digital signals to be sent to a QAM modulator, said signals being encoded according to an LDPC code, characterized in that a bit permutation is carried out prior to the constellation mapping function.

2. Method according to claim 1, wherein said digital signals are audio and video signals, wherein said modulator is of the 1024QAM type, wherein said signals are encoded according to the LDPC code, in particular the one of the DVB-S2 standard, and wherein said bit permutation is carried out on words having a length of 20 bits or further multiples of 10 bits.

3. Method according to claim 1 or 2, wherein said permutation is carried out on 20-bit words and consists in generating a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19, in this order, starting from a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y19 and b19 being respectively the least significant bits of the words Y and B, and wherein:

4. Method according to claim 1 or 2, wherein said permutation is carried out on 20-bit words and consists in generating a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19, in this order, starting from a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y19 and b19 being respectively the least significant bits of the words Y and B, and wherein:

5. Method according to claim 1 or 2, wherein said permutation is carried out on 20-bit words and consists in generating a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19, in this order, starting from a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y19 and b19 being respectively the least significant bits of the words Y and B, and wherein:

6. Method according to claim 1 or 2, wherein said permutation is carried out on 20-bit words and consists in generating a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19, in this order, starting from a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y19 and b19 being respectively the least significant bits of the words Y and B, and wherein:

7. Method according to claim 1, wherein said digital signals are audio and video signals, wherein said modulator is of the 4096QAM type, wherein said signals are encoded according to the LDPC code, in particular the one of the DVB-S2 standard, and wherein said bit permutation is carried out on words having a length of 24 bits or further multiples of 12 bits.

8. Method according to claim 1 or 7, wherein said permutation is carried out on 24-bit words and consists in generating a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23, in this order, starting from a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y23 and b23 being respectively the least significant bits of the words Y and B, and wherein:

9. Method according to claim 1 or 7, wherein said permutation is carried out on 24-bit words and consists in generating a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23, in this order, starting from a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y23 and b23 being respectively the least significant bits of the words Y and B, and wherein:

10. Method according to claim 1 or 7, wherein said permutation is carried out on 24-bit words and consists in generating a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23, in this order, starting from a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y23 and b23 being respectively the least significant bits of the words Y and B, and wherein:

11. Method according to claim 1 or 7, wherein said permutation is carried out on 24-bit words and consists in generating a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23, in this order, starting from a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y23 and b23 being respectively the least significant bits of the words Y and B, and wherein:

12. System for transmitting digital signals comprising a QAM modulator, characterized in that it implements the method according to any of claims 1 to 11.

13. Method for processing digital signals received by a QAM demodulator, said signals being encoded according to an LDPC code, characterized in that a bit permutation is carried out after the constellation demapping function.

14. Method according to claim 13, wherein said digital signals are audio and video signals, wherein said demodulator is of the 1024QAM type, wherein said signals are encoded according to the LDPC code, in particular the one of the DVB-S2 standard, and wherein said bit permutation is carried out on words having a length of 20 bits or further multiples of 10 bits.

15. Method according to claim 13 or 14, wherein said permutation is carried out on 20-bit words and consists in generating a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19, in this order, starting from a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y11 and b11 being respectively the least significant bits of the words Y and B, wherein:

16. Method according to claim 13 or 14, wherein said permutation is carried out on 20-bit words and consists in generating a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19, in this order, starting from a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y11 and b11 being respectively the least significant bits of the words Y and B, wherein:

17. Method according to claim 13 or 14, wherein said permutation is carried out on 20-bit words and consists in generating a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19, in this order, starting from a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y11 and b11 being respectively the least significant bits of the words Y and B, wherein:

18. Method according to claim 13 or 17, wherein said permutation is carried out on 20-bit words and consists in generating a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19, in this order, starting from a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y11 and b11 being respectively the least significant bits of the words Y and B, wherein:

19. Method according to claim 13, wherein said digital signals are audio and video signals, wherein said demodulator is of the 4096QAM type, wherein said signals are encoded according to the LDPC code, in particular the one of the DVB-S2 standard, and wherein said bit permutation is carried out on words having a length of 24 bits or further multiples of 12 bits.

20. Method according to claim 13 or 19, wherein said permutation is carried out on 24-bit words and consists in generating a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23, in this order, starting from a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y11 and b11 being respectively the least significant bits of the words Y and B, wherein:

21. Method according to claim 13 or 19, wherein said permutation is carried out on 24-bit words and consists in generating a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23, in this order, starting from a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y11 and b11 being respectively the least significant bits of the words Y and B, wherein:

22. Method according to claim 13 or 19, wherein said permutation is carried out on 24-bit words and consists in generating a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23, in this order, starting from a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y′7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y11 and b11 being respectively the least significant bits of the words Y and B, wherein:

23. Method according to claim 13 or 19, wherein said permutation is carried out on 24-bit words and consists in generating a word B comprising the bits b0 b1 b2 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 b18 b19 b20 b21 b22 b23, in this order, starting from a word Y comprising the bits y0 y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13 y14 y15 y16 y17 y18 y19 y20 y21 y22 y23, in this order, the bits y0 and b0 being respectively the most significant bits of the words Y and B, and the bits y11 and b11 being respectively the least significant bits of the words Y and B, wherein:

24. System for receiving digital signals comprising a QAM demodulator, characterized in that it implements the method according to any of claims 13 to 23.