Claims
- 1. A method for producing an active matrix substrate which uses a thin transistor layer having a semiconductor layer having a contact region and a channel region, a gate insulating layer, a gate electrode formed on a substrate in this sequence, a source electrode and a drain electrode each kept in contact with the contact region, the source electrode and the drain electrode partly overlapping with end portions of the semiconductor layer which end portions are wider than the gate insulating layer and the gate electrode, the gate insulating layer having declined sides wherein the sides thereof adjacent the gate electrode form a narrower top surface than a bottom surface thereof toward the substrate, and wherein ions are implanted into the semiconductor layer from the gate electrode such that a contact layer is formed in a portion of the semiconductor layer overlapping with at least part of the declining sides of the gate insulating layer and part of the semiconductor layer extending beyond the gate insulating layer.
- 2. A method according to claim 1, wherein the source electrode and the drain electrode overlap at least part of the declining sides of the gate insulating layer.
- 3. A method according to claim 2, wherein end portions of the gate electrode coincide with end portions of the narrower top surface of the gate insulting layer.
- 4. A method according to claim 3, wherein one of the declining sides of the gate insulating layer is declined at 10.degree. to 70.degree. with respect to the bottom surface of the gate insulating layer.
- 5. A method for producing an active matrix substrate comprising the steps of:
- forming a semiconductor layer on a transparent insulating substrate;
- forming a gate insulating layer on the semiconductor layer, the gate insulating layer having declining sides, wherein the sides thereof form a narrower top surface than a bottom surface thereof toward the transparent insulating substrate;
- forming a gate electrode on the narrower top surface of the gate insulating layer;
- forming a contact region in a portion of the semiconductor layer by an ion implanting method, the contact region overlapping at least part of the declining sides of the gate insulating layer and part of the semiconductor layer extending beyond the gate insulating layer, and
- wherein end portions of the gate electrode coincide with end portions of the narrower top surface of the gate insulating layer.
- 6. A method according to claim 5, wherein the method further includes the step of:
- forming an electrode on the contact region, the electrode overlapping at least part of the declining sides of the gate insulating layer.
- 7. A method according to claim 5, wherein one of the declining sides of the gate insulating layer is declined at 10.degree. to 70.degree. with respect to the bottom surface of the gate insulating layer.
Priority Claims (9)
Number |
Date |
Country |
Kind |
2-408959 |
Dec 1990 |
JPX |
|
3-4575 |
Jan 1991 |
JPX |
|
3-12004 |
Feb 1991 |
JPX |
|
3-30511 |
Feb 1991 |
JPX |
|
3-144914 |
Jun 1991 |
JPX |
|
3-213939 |
Aug 1991 |
JPX |
|
3-213950 |
Aug 1991 |
JPX |
|
3-213953 |
Aug 1991 |
JPX |
|
3-215561 |
Aug 1991 |
JPX |
|
Parent Case Info
This is a divisional of application Ser. No. 07/813,385, filed Dec. 26, 1991, now U.S. Pat. No. 5,286,659.
US Referenced Citations (4)
Foreign Referenced Citations (6)
Number |
Date |
Country |
0071244 |
Feb 1983 |
EPX |
0076587 |
Apr 1983 |
EPX |
0338766 |
Oct 1989 |
EPX |
0354372 |
Feb 1990 |
EPX |
3237539 |
Aug 1983 |
DEX |
123097 |
Dec 1991 |
JPX |
Non-Patent Literature Citations (2)
Entry |
Wolf, Silicon Processing for the VLSI Era, vol. 2--Process Integration, Lattice Press, 1990, pp. 66-67. |
"Leakage Current of Amorphous Silicon Thin-Film-Transistor (TFT)" by Wu et al, Electronics Research and Service Organization, Industrial Technology Research Institute, Chutung, Hsinchu, Taiway, R.O.C., pp. 513-517. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
813385 |
Dec 1991 |
|