Claims
- 1. A multi-layered chip inductor comprising:a coil-shaped internal conductor inside a ceramic laminate, said coil-shaped internal conductor being spiralled around an axial line in a laminating direction of said ceramic laminate, wherein said coil-shaped internal conductor is formed by a plurality of internal conductor patterns laminated on a plurality of ceramic laminate pieces, the ceramic laminate pieces and the internal conductor patterns being laminated on top of one another in the laminating direction to form a ceramic laminate having two laminating direction surfaces, the plurality of internal conductor patterns being connected through via holes in the ceramic laminate pieces; and external electrodes disposed on an entirety of both laminating-direction surfaces of said ceramic laminate, said external electrodes being electrically connected to respective ends of said coil-shaped internal conductor, wherein peripheral shapes of the external electrodes are identical to peripheral shapes of said laminating-direction surfaces.
- 2. The multi-layered chip inductor of claim 1, wherein said external electrodes being electrically connected respectively to both ends of said coil-shaped internal conductor via said two opposing laminating-direction surfaces.
- 3. The multi-layered chip inductor of claim 1, wherein the external electrode is a fired electrode paste.
Priority Claims (1)
Number |
Date |
Country |
Kind |
8-245008 |
Sep 1996 |
JP |
|
Parent Case Info
This application is a divisional, of application Ser. No. 08/931,884, filed Sep. 17, 1997, now U.S. Pat. No. 6,189,200.
This application is based on Japanese Patent Application No. 8-245008, filed on Sep. 17, 1996, which is incorporated herein in its entirety by reference.
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