Patent Application
20250227856
The present invention relates to a method for producing a printed wiring board with built-in capacitor and a multilayer printed wiring board.
Printed wiring boards are widely used in electronic communication devices such as portable electronic devices. In particular, as portable electronic communication devices and other devices have become lighter, thinner, shorter, smaller, and more highly functional in recent years, reducing noise in printed wiring boards has become an issue, for example. Capacitors are important for enabling noise reduction, but in order to realize high functionality, it is desirable for capacitors to be small enough and thin enough to be incorporated into the inner layers of printed wiring boards.
Various methods have been proposed for producing multilayer printed wiring boards including built-in capacitor circuits. For example, Patent Literature 1 (WO2006/016586) discloses a method for producing a multilayer printed wiring board, the method including providing a dielectric layer and a first conductive metal layer on the surface having a base electrode of a core material, processing the first conductive metal layer into top electrodes, removing the exposed dielectric layer, filling the gaps among the top electrodes and providing an insulating layer and a second conductive metal layer on the top electrodes, and processing the second conductive metal layer into outer layer circuits. Also, Patent Literature 2 (WO2017/086418) discloses a method for producing a printed wiring board that has a dielectric layer with a thickness of 30 μm or less, the method including providing a pair of metal clad laminated plates having the configuration of first carrier/release layer/first metal foil/dielectric layer/second metal foil/release layer/second carrier, laminating the metal clad laminated plates onto each side of a resin substrate on the first carrier side, peeling off the second carrier from the laminated body obtained, etching the second metal foil exposed to form a conductor pattern, laminating an insulating layer onto the conductor pattern and laminating a metal layer onto the insulating layer, and separating the laminated body between the first carrier and the first metal foil.
Double-sided copper clad laminates for the production of printed wiring boards with built-in capacitor have also been proposed. For example, Patent Literature 3 (WO2021/251288) discloses a double-sided copper clad laminate including an adhesive layer and a copper foil in the order presented, on each of both sides of a resin film, and describes that the resin film is in a cured state at 25° C., and in both copper foils, the maximum peak height Sp measured in accordance with ISO 25178 on the surface on the side in contact with the adhesive layer is 0.05 μm or more and 3.3 μm or less.
Currently, for example, printed wiring boards with built-in capacitor using double-sided copper clad laminates are manufactured according to the procedures as shown in
Incidentally, as mentioned above, in order to realize high functionality, it is desirable for capacitors to be small enough and thin enough to be incorporated into the inner layers of printed wiring boards. From such a viewpoint, double-sided copper clad laminates with a thin thickness (for example, the thickness of the resin layer is 30 μm or less, 20 μm or less, or 10 μm or less) are used. However, in the case where such thin copper clad laminates are used in the current construction method described above, there is a risk that the resin layer is broken due to the folding of the substrate. For example, when forming the circuit 118 in
Furthermore, when pressing the copper clad laminate 120 in
The inventors have recently found that, by laminating a pre-formed embedded circuit board on a resin-coated copper foil containing a predetermined resin in a semi-cured state and curing the resin, a printed wiring board with built-in capacitor that is excellent in adhesion between a circuit and a dielectric layer can be produced by a method that allows easy control of the thickness of the dielectric layer and high productivity while reducing the risk of breakage of the resin layer.
Accordingly, an object of the present invention is to produce a printed wiring board with built-in capacitor that is excellent in adhesion between a circuit and a dielectric layer by a method that allows easy control of the thickness of the dielectric layer and high productivity while reducing the risk of breakage of the resin layer.
The present invention provides the following aspects:
A method for producing a printed wiring board with built-in capacitor that has a dielectric layer with a thickness of 30 μm or less, the method comprising the steps of:
The method for producing a printed wiring board with built-in capacitor according to aspect 1, wherein the maximum value of logarithmic decrement is 0.2 or more and 2.0 or less.
The method for producing a printed wiring board with built-in capacitor according to aspect 1 or 2, wherein in the embedded circuit board obtained in the step (e), a maximum value of height difference between a surface of the second resin substrate and a surface of the circuit embedded in the second resin substrate is 0.5 μm or less.
The method for producing a printed wiring board with built-in capacitor according to any one of aspects 1 to 3, wherein a thickness variation in the dielectric layer is ±15% or less.
A method for producing a multilayer printed wiring board, comprising the step of laminating a plurality of built-in capacitor circuits produced by the method according to any one of aspects 1 to 4.
The present invention relates to a method for producing a printed wiring board with built-in capacitor. The printed wiring board with built-in capacitor has a dielectric layer with a thickness of 30 μm or less.
As mentioned above, in the current construction method, there is a risk that the resin layer is broken due to the folding of the substrate. For example, when forming the circuit 118 in
(a) Lamination of Carrier-Attached Copper Foil onto First Resin Substrate
As shown in
For the first resin substrate 10, any known resin substrate may be used, and there is no particular limitation. The first resin substrate 10 may be a prepreg. The prepreg is a generic term for composite materials in which a substrate such as synthetic resin plate, glass plate, glass woven fabric, glass non-woven fabric, or paper is impregnated with a synthetic resin. Preferred examples of the insulating resin with which the prepreg is impregnated include an epoxy resin, a cyanate resin, a bismaleimide triazine resin (BT resin), a polyphenylene ether resin, and a phenolic resin. The thickness of the first resin substrate 10 is preferably 10 μm or more and 1000 μm or less, more preferably 20 μm or more and 400 μm or less, and still more preferably 40 μm or more and 250 μm or less.
For the carrier-attached copper foil 12, any known material may be used, and there is no particular limitation. A typical aspect of each layer will be described below.
The carrier 14 is a support for supporting the first copper layer 18 to improve its handleability, and a typical carrier contains a metal layer. Examples of such a carrier include an aluminum foil, a copper foil, a stainless steel (SUS) foil, and a resin film or glass with its surface metal-coated with copper or other metals, and it is preferably a copper foil. The copper foil may be either a rolled copper foil or an electrodeposited copper foil, but is preferably an electrodeposited copper foil. The thickness of the carrier is typically 250 μm or less, preferably 7 μm or more and 200 μm or less.
The release layer 16 is a layer that functions to weaken the release strength of the carrier, to ensure the stability of that strength, and further to suppress possible interdiffusion between the carrier and the copper foil during pressing at high temperature. The release layer is generally formed on one side of the carrier, but may be formed on both sides. The release layer may be either an organic release layer or an inorganic release layer. Examples of the organic components used in the organic release layer include a nitrogen-containing organic compound, a sulfur-containing organic compound, and a carboxylic acid. Examples of the nitrogen-containing organic compound include a triazole compound and an imidazole compound, and among them, a triazole compound is preferable since releasability is likely to be stabilized. Examples of the triazole compound include 1,2,3-benzotriazole, carboxybenzotriazole, N′,N′-bis(benzotriazolylmethyl)urea, 1H-1,2,4-triazole, and 3-amino-1H-1,2,4-triazole. Examples of the sulfur-containing organic compound include mercaptobenzothiazole, thiocyanuric acid, and 2-benzimidazolethiol. Examples of the carboxylic acid include a monocarboxylic acid and a dicarboxylic acid. Meanwhile, examples of the inorganic components used in the inorganic release layer include Ni, Mo, Co, Cr, Fe, Ti, W, P, Zn, and a chromate-treated film. Note that formation of the release layer may be performed by bringing a release layer component-containing solution into contact with at least one surface of the carrier and fixing the release layer components to the surface of the carrier, or by other means. In the case where the carrier is brought into contact with the release layer component-containing solution, this contact may be performed by immersion in the release layer component-containing solution, spraying of the release layer component-containing solution, or flowing down of the release layer component-containing solution. In addition, methods in which the release layer components are formed into a film by the gas-phase method such as vapor deposition or sputtering can also be employed. Also, the fixation of the release layer components to the carrier surface may be performed by adsorption or drying of the release layer component-containing solution, electrodeposition of the release layer components in the release layer component-containing solution, or other means. The thickness of the release layer is typically 1 nm or more and 1 μm or less, preferably 5 nm or more and 500 nm or less.
If desired, other functional layers may be provided between the release layer 16 and the carrier 14 and/or the first copper layer 18. Examples of such other functional layers include an auxiliary metal layer. The auxiliary metal layer is preferably composed of nickel and/or cobalt. By forming such an auxiliary metal layer on the surface side of the carrier 14 and/or on the surface side of the first copper layer 18, the possible interdiffusion between the carrier 14 and the first copper layer 18 during hot pressing at high temperature or for a long time can be suppressed and the stability of the release strength of the carrier can be ensured. The thickness of the auxiliary metal layer is preferably set to 0.001 μm or more and 3 μm or less.
The first copper layer 18 is preferably a roughened copper foil. The roughened copper foil has a roughened surface on at least one side. That is, the roughened copper foil may have roughened surfaces on both sides or may have a roughened surface on only one side. The roughened surface includes a plurality of roughened particles, and each of these plurality of roughened particles is preferably composed of a copper particle. The copper particle may be composed of metallic copper or may be composed of a copper alloy. The roughened copper foil preferably further includes a rustproof layer and/or a silane coupling agent layer on the roughened surface, and more preferably includes both a rustproof layer and a silane coupling agent layer. The rustproof layer and the silane coupling agent layer may be formed not only on the roughened surface side of the roughened copper foil, but also on the side where the roughened surface is not formed.
Although the thickness of the first copper layer 18 is not particularly limited, it is preferably 0.1 μm or more and 35 μm or less, more preferably 0.5 μm or more and 5.0 μm or less, and still more preferably 1.0 μm or more and 3.0 μm or less.
As shown in
As shown in
As shown in
As shown in
(f) Lamination of Embedded Circuit Board onto Resin-Coated Copper Foil
As shown in
Although the thickness of the copper layer 36 is not particularly limited and may be determined as appropriate depending on the specific application of the resin-coated copper foil, it is preferably 0.1 μm or more and 100 μm or less, more preferably 0.5 μm or more and 70 μm or less, still more preferably 2 μm or more and 70 μm or less, particularly preferably 10 μm or more and 70 μm or less, and most preferably 10 μm or more and 35 μm or less. When the thickness is within these ranges, the modified semi-additive process (MSAP), semi-additive process (SAP), subtractive process, and other construction methods, which are common methods for forming wiring patterns on printed wiring boards, can be employed. Also, in the case where the thickness of the copper layer 36 is very thin (for example, 10 μm or less), the resin-coated copper foil 32 used in the present invention may be a carrier-attached copper foil including a release layer and a carrier for improved handleability, with the resin layer 34 formed on the copper foil surface thereof.
The surface of the copper layer 36 in contact with the resin layer 34 preferably has a low roughness from the viewpoint of easy control of the thickness of the resin layer 34. From this viewpoint, when the surface roughness of the copper layer 36 on the side in contact with the resin layer 34 is represented as the ten-point average roughness, Rzjis, as measured in accordance with JIS B0601-2001, the Rzjis is preferably 2.0 μm or less, more preferably 1.5 μm or less, still more preferably 1.0 μm or less, and particularly preferably 0.5 μm or less. As a result of this, it becomes easier to form the resin composition layer thinly and uniformly. Although the lower limit value of the ten-point average roughness, Rzjis, of the surface facing the resin composition layer in the metal foil is not particularly limited, the Rzjis is preferably 0.005 μm or more, more preferably 0.01 μm or more, and still more preferably 0.05 μm or more, from the viewpoint of improving the adhesion to the resin composition layer.
The maximum height Sz on the surface of the copper layer 36 on the side in contact with the resin layer 34 is preferably 6.8 μm or less, more preferably 0.15 μm or more and 6.8 μm or less, still more preferably 0.25 μm or more and 5.0 μm or less, and particularly preferably 0.3 μm or more and 3.0 μm or less. Within such ranges, high capacitor capacitance and high voltage endurance can be demonstrated while ensuring sufficient adhesion to the resin layer 34. Note that, as used herein, the “maximum height Sz” is a parameter that represents the distance from the highest point to the lowest point of the surface, as measured in accordance with ISO 25178.
The kurtosis Sku on the surface of the copper layer 36 on the side in contact with the resin layer 34 is preferably 2.0 or more and 4.0 or less, more preferably 2.2 or more and 3.8 or less, and still more preferably 2.4 or more and 3.5 or less. Within such ranges, variation in capacitor capacitance can be reduced. Note that the “kurtosis Sku” in the present invention is a parameter that represents the sharpness of the height distribution, as measured in accordance with ISO 25178, and is also referred to as the degree of peakedness. Sku=3 means that the height distribution is a normal distribution, Sku>3 means that the surface has many sharp peaks and valleys, and Sku<3 means that the surface is flat.
The maximum peak height Sp on the surface of the copper layer 36 on the side in contact with the resin layer 34 is preferably 3.3 μm or less, more preferably 0.06 μm or more and 3.1 μm or less, still more preferably 0.06 μm or more and 3.0 μm or less, and particularly preferably 0.07 μm or more and 2.9 μm or less. Within such ranges, high capacitor capacitance and high voltage endurance can be demonstrated while ensuring sufficient adhesion to the resin layer 34. Note that, as used herein, the “maximum peak height Sp” is a three-dimensional parameter that represents the maximum value of the height from the average surface of the surface, as measured in accordance with ISO 25178.
The root mean square gradient Sdq on the surface of the copper layer 36 on the side in contact with the resin layer 34 is preferably 0.01 or more and 2.3 or less, more preferably 0.02 or more and 2.0 or less, and still more preferably 0.04 or more and 1.8 or less. Within such ranges, transmission loss can be desirably reduced while ensuring sufficient adhesion to the resin layer 34. High capacitor capacitance and high voltage endurance can be demonstrated. Note that, as used herein, the “root mean square gradient Sdq” is a parameter calculated from the root mean square of the gradient at all points in the defined region, as measured in accordance with ISO 25178. That is, it is a three-dimensional parameter that evaluates the magnitude of the local slope angle, and thus can numericize the steepness of the surface irregularities. For example, the Sdq on a perfectly flat surface is 0, and if the surface is sloped, the Sdq becomes larger. The Sdq of a plane composed of a 45 degree sloped component is 1.
The above-mentioned maximum height Sz, kurtosis Sku, maximum peak height Sp, and root mean square gradient Sdq can be calculated by measuring the surface profile of a predetermined measurement area (for example, a region of 10000 μm2) on the copper foil surface with a commercially available laser microscope.
The thickness of the resin layer 34 may be determined so as to realize the thickness of the dielectric layer 38, which will be described later. Accordingly, the preferred range with respect to the thickness of the dielectric layer 38, which will be described later, applies directly to the resin layer 34.
The resin in a semi-cured state constituting the resin layer 34 preferably contains a thermoplastic component and/or a thermosetting resin component. Specifically, it preferably contains at least one selected from the group consisting of epoxy resins, polyethylene terephthalate resins, polyethylene naphthalate resins, polyvinylcarbazole resins, polyphenylene sulfide resins, polyamide resins, aromatic polyamide resins, polyamideimide resins, polyimide resins, polyethersulfone resins, polyethernitrile resins, polyether ether ketone resins, polytetrafluoroethylene resins, urethane resins, isocyanate resins, active ester resins, phenolic resins, and diamine compounds, and more preferably contains at least one selected from the group consisting of epoxy resins, polyimide resins, aromatic polyamide resins, active ester resins, phenolic resins, and diamine compounds.
The resin in a semi-cured state constituting the resin layer 34 may further contain a dielectric filler. The dielectric filler is preferably a composite metal oxide containing at least two selected from the group consisting of Ba, Ti, Sr, Pb, Zr, La, Ta, Ca, and Bi. This composite metal oxide more preferably contains at least two selected from the group consisting of Ba, Ti, and Sr. The composite metal oxide preferably contains at least one selected from the group consisting of BaTiO3, SrTiO3, BaTi4O9, Pb(Zr, Ti)O3, PbLaTiO3, PbLaZrO, and SrBi2Ta2O9, and more preferably contains at least one selected from the group consisting of BaTiO3 and SrTiO3. Note that Pb(Zr, Ti)O3 means Pb(ZrxTi1-x)O3, wherein 0≤x≤1, typically 0<x<1. It is preferable to use a dielectric filler that is a composite metal oxide. In the case where a dielectric filler is used, the dielectric filler is preferably contained in an amount of 0 parts by weight or more and 90 parts by weight or less, more preferably in an amount of 15 parts by weight or more and 85 parts by weight or less, and still more preferably in an amount of 25 parts by weight or more and 80 parts by weight or less, relative to 100 parts by weight of the solid content of the resin composition. Note that, although the resin composition is in a semi-cured state in the step (f), the “solid content of the resin composition” referred to here shall mean the components (resin components, dielectric filler, and others) that constitute the solid content in the resin composition after curing. Although the particle size of the dielectric filler that is a composite metal oxide is not particularly limited, from the viewpoint of maintaining the adhesion between the adhesive layer and the copper foil, the average particle size D50 as measured by laser diffraction scattering particle size distribution measurement is preferably 0.001 μm or more and 2.0 μm or less, more preferably 0.01 μm or more and 1.8 μm or less, and still more preferably 0.03 μm or more and 1.6 μm or less.
The resin composition may further contain a filler dispersant. By further containing a filler dispersant, the dispersibility of the dielectric filler can be improved when the resin varnish and the dielectric filler are mixed together. As the filler dispersant, any usable known filler dispersant can be used as appropriate, and there is no particular limitation. Preferred examples of the filler dispersant include an ionic dispersant such as phosphonic acid, cationic, carboxylic acid, and anionic dispersants, as well as a nonionic dispersant such as ether, ester, sorbitan ester, diester, monoglyceride, ethylene oxide adduct, ethylene diamine-based, and phenolic dispersants. In addition, examples thereof include a coupling agent such as a silane coupling agent, a titanate coupling agent, and an aluminate coupling agent.
A curing accelerator may be added to the resin composition in order to accelerate the curing of the resin components. Preferred examples of the curing accelerator include an imidazole-based curing accelerator and an amine-based curing accelerator. From the viewpoint of storage stability of the resin components contained in the resin composition and efficiency of curing, the content of the curing accelerator is preferably 0.01 parts by weight or more and 3.0 parts by weight or less, more preferably 0.1 parts by weight or more and 2.0 parts by weight or less, relative to 100 parts by weight of the non-volatile components in the resin composition.
As shown in
The thickness of the dielectric layer 38 is 30 μm or less, preferably 16 μm or less, more preferably 12 μm or less, still more preferably 10 μm or less, and particularly preferably 5 μm or less, from the viewpoint of realizing high capacitance of the capacitor. Although the lower limit value of the thickness of the dielectric layer 38 is not particularly limited as long as the thickness does not allow a short circuit between the circuit 20 and the copper layer 36 facing each other via the dielectric layer 38, it is preferably 0.1 μm or more, more preferably 0.5 μm or more.
The thickness variation in the dielectric layer 38 is preferably ±15% or less, more preferably ±10% or less, and still more preferably ±8% or less. This small thickness variation in the dielectric layer 38 prevents variation in the capacitance of the capacitor from occurring. The thickness variation in the dielectric layer 38 is a value defined as follows: measure a total of at least 10 points by magnifying (for example, magnify at least 500 times) the cross-section of the center of the dielectric layer 38 and its edges (for example, the four corners if the dielectric layer 38 is rectangular) in the thickness direction; find the maximum value, minimum value, and average value of them; and use the larger numerical value among the numerical values (unit: %) represented by the following formulas (1) and (2) as the thickness variation.
The dielectric layer 38 preferably has a relative permittivity of 2.5 or more, more preferably 10 or more, and still more preferably 20 or more. With such a high relative permittivity, the capacitance can be easily increased while making the dielectric layer 38 thinner. Since a higher relative permittivity of the dielectric layer 38 is desirable, the upper limit value is not particularly limited, but it is preferably 300 or less, more preferably 200 or less, and still more preferably 100 or less, from the viewpoint of adhesion to the metal foil and the strength of the dielectric layer. As used herein, the relative permittivity shall mean the value measured by the split post dielectric resonance method (frequency used: 1 GHZ).
The adhesion strength between the dielectric layer 38 and the circuit 20 can be indirectly evaluated by measuring the adhesion strength between the copper layer 36 and the dielectric layer 38. The adhesion strength between the dielectric layer 38 and the circuit 20 and the adhesion strength between the copper layer 36 and the dielectric layer 38 are preferably 0.3 kN/m or more, more preferably 0.4 kN/m or more, and still more preferably 0.5 kN/m or more.
By laminating a plurality of built-in capacitor circuits produced by the method of the present invention, a multilayer printed wiring board can be produced. That is, according to a preferred aspect of the present invention, there is provided a method for producing a multilayer printed wiring board, including the step of laminating a plurality of built-in capacitor circuits produced by the method of the present invention.
The present invention will be described more specifically by the following examples.
Two sheets of prepreg (manufactured by Panasonic Corporation, R-1661, thickness: 100 μm) were stacked to provide a first resin substrate as a dummy core. On this first resin substrate, a carrier-attached copper foil (manufactured by Mitsui Mining & Smelting Co., Ltd., carrier thickness: 18 μm, first copper layer (ultra-thin copper layer) thickness: 3 μm, organic release layer) was laminated such that the carrier and the first resin substrate are in contact with each other. This lamination was performed by performing vacuum pressing at 190° C. for 90 minutes. On the first copper layer of the laminated body obtained, a circuit with L/S=15 μm/15 μm was formed by the modified semi-additive process (MSAP).
Subsequently, a sheet of prepreg (manufactured by Panasonic Corporation, R-1661, thickness: 100 μm) was laminated onto the laminated body as a second resin substrate such that the circuit of the above laminated body was embedded, and on this second resin substrate, a copper foil (manufactured by Mitsui Mining & Smelting Co., Ltd., thickness: 18 μm, surface roughness Rzjis=0.5 μm) was laminated as a second copper layer. In this way, a copper clad laminate with a configuration in which the circuit is embedded in the second resin substrate was obtained.
The first resin substrate and the carrier were separated and removed from the first copper layer via the release layer. The first copper layer present on the surface of the remaining laminated body was etched away to expose the circuit embedded in the second resin substrate on the surface. At this time, the etching was finished when the circuit embedded in the second resin substrate was exposed on the surface, so that no difference in height between the surface of the second resin substrate and the surface of the embedded circuit would be generated. In this way, an embedded circuit board was obtained.
A resin-coated copper foil containing a resin layer composed of a resin varnish A in a semi-cured state and a copper layer was fabricated and evaluated according to the following procedure. Note that the surface property parameters of the copper foil described later were measured by the following procedure.
By surface roughness analysis using a laser microscope (manufactured by Olympus Corporation, OLS5000), the surface of the copper layer on the side in contact with the resin layer was measured in accordance with ISO 25178. Specifically, the surface profile of a region with an area of 16384 μm2 on the surface of the copper layer on the side in contact with the resin layer was measured using the above laser microscope using a 100 times lens with a numerical aperture (N.A.) of 0.95. Noise removal and primary linear surface inclination correction were performed on the obtained surface profile, and then measurements of the maximum height Sz, kurtosis Sku, maximum peak height Sp, and root mean square gradient Sdq were performed by surface property analysis. In all cases, the measurements were performed with the cutoff wavelength by the S filter set to 0.55 μm and the cutoff wavelength by the L filter set to 10 μm.
The resin components and imidazole-based curing accelerator shown below were provided as raw material components for resin varnish.
The raw material components for resin varnish were weighed. Thereafter, a cyclopentanone solvent was weighed, and the raw material components for resin varnish and the cyclopentanone solvent were put into a flask and stirred at 60° C. After confirming that there was no undissolved residue of raw materials in the resin varnish and that the resin varnish was clear, the resin varnish A was collected.
The obtained resin varnish A was applied to the surface of a copper foil (manufactured by Mitsui Mining & Smelting Co., Ltd., thickness 18 μm, surface roughness Rzjis=0.6 μm, maximum height Sz=0.14, kurtosis Sku=3.50, maximum peak height Sp=0.085, and root mean square gradient Sdq=0.053) using a bar coater such that the thickness of the resin layer after drying was about 5 μm, and then dried in an oven heated to 150° C. for 3 minutes to make the resin layer in a semi-cured state.
The obtained resin-coated copper foil was cut into a size of 150 mm×150 mm, and set on the heating stage of a rigid-body pendulum type physical properties testing instrument (manufactured by A&D Co., Ltd., RPT-3000 W). Measurement of the logarithmic decrement was performed in the temperature range of 30° C. to 220° C., setting the temperature increase rate of the heating stage to 5° C./minute, and the maximum value of the logarithmic decrement measured was confirmed. This measurement was performed in accordance with ISO12013-1 or ISO12013-2.
The embedded circuit board obtained in the above (1) was placed with the embedded circuit side facing up, and the resin-coated copper foil obtained in the above (2) was superimposed on top of it with the resin layer facing down. Thereafter, vacuum pressing was performed at 180° C. for 120 minutes to make the resin layer in a cured state, thereby obtaining a built-in capacitor circuit board.
The obtained built-in capacitor circuit board was cut into a size of about 8 mm in width and 5 mm in length, and then cut out in the thickness direction of the built-in capacitor circuit board using a microtome (Leica Biosystems, RM2265, fully automatic universal rotary microtome) to expose the embedded circuit cross-section. That cross-section was observed with an optical microscope (Leica Microsystems, Leica DM LM) and FE-SEM to evaluate the presence or absence of defects (for example, locations of incomplete adhesion) on the adhesion surface between the embedded circuit and the resin-coated copper foil.
Also, the circuit adhesion strength was measured as follows. After fabricating a straight-line circuit with a width of 3 mm by etching the surface on the resin-coated copper foil side of the obtained built-in capacitor circuit board, the circuit was peeled off using Autograph at a peeling speed of 50 mm/minute and its peel strength was measured at normal temperature (for example, 25° C.). This measurement was performed in accordance with IPC-TM-650 2.4.8. As a result, the adhesion between the embedded circuit and the resin-coated copper foil was indirectly evaluated.
Based on the evaluation results obtained, the adhesion between the embedded circuit and the resin-coated copper foil was rated according to the following criteria.
The following evaluation was performed on the dielectric layer in the built-in capacitor circuit board obtained in the above (3).
In the same manner as in the above (4), the obtained built-in capacitor circuit board was cut into a size of about 8 mm in width and 5 mm in length, and then cut out in the thickness direction of the built-in capacitor circuit board using a microtome (Leica Biosystems, RM2265, fully automatic universal rotary microtome) to expose the embedded circuit cross-section. That cross-section was observed with an optical microscope (Leica Microsystems, Leica DM LM), and the thickness of the dielectric layer was measured at 10 points.
The maximum value, minimum value, and average value of the thickness of the dielectric layer at the 10 points measured were determined, and the larger numerical value among the numerical values (unit: %) calculated by the following formulas (1) and (2) was employed as the value of thickness variation.
Fabrication and evaluation of a built-in capacitor circuit board was performed in the same manner as in Example 1, except that a resin composition in which a dielectric filler was dispersed in a resin varnish B prepared as described below was used instead of the resin varnish A.
(2a′) Preparation of Resin Composition
The resin components and imidazole-based curing accelerator shown below were provided as raw material components for resin varnish.
At first, the raw material components for resin varnish were weighed. Thereafter, a cyclopentanone solvent was weighed, and the raw material components for resin varnish and the cyclopentanone solvent were put into a flask and stirred at 60° C. After confirming that there was no undissolved residue of raw materials in the resin varnish and that the resin varnish was clear, the resin varnish B was collected.
Next, the dielectric filler and dispersant shown below were provided.
Thereafter, a cyclopentanone solvent, the dielectric filler, and the dispersant were each weighed. The weighed solvent, dielectric filler, and dispersant were made into a slurry with a dispersing machine. After this slurrification was confirmed, the resin varnish B was weighed such that the final compounding proportion of the dielectric filler was 79 parts by weight relative to 100 parts by weight of the solid content of the resin composition to be finally obtained, and was mixed together with the dielectric filler-containing slurry in a dispersing machine. After mixing, the dielectric filler was confirmed not to be agglomerated, and the resin varnish B in which the dielectric filler was then dispersed was collected.
Fabrication and evaluation of a built-in capacitor circuit board was performed in the same manner as in Example 2, except that the drying after applying the resin varnish B to the copper foil was performed at 130° C.
Fabrication and evaluation of a built-in capacitor circuit board was performed in the same manner as in Example 2, except that the drying after applying the resin varnish B to the copper foil was performed at 180° C.
Fabrication and evaluation of a built-in capacitor circuit board was performed in the same manner as in Example 2, except that the drying after applying the resin varnish B to the copper foil was performed at 200° C.
Fabrication and evaluation of a built-in capacitor circuit board was performed in the same manner as in Example 1, except that the etching removal of the first copper layer was performed by not only exposing the circuit embedded in the second resin substrate on the surface, but also by over-etching until the maximum value of height difference between the surface of the second resin substrate and the surface of the embedded circuit was about 0.2 μm.
The evaluation results of Examples 1 to 6 were as shown in Table 1.
| Number | Date | Country | Kind |
|---|---|---|---|
| 2022-054344 | Mar 2022 | JP | national |
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2023/008661 | 3/7/2023 | WO |
