Claims
- 1. A method for producing an electrostatically-driven ink jet head, comprising the steps of:
- (A) etching a first surface of a silicon substrate to define an ink ejection chamber therein, the ink ejection chamber including a deformable diaphragm interposing the first and an opposing second surface of the silicon substrate;
- (B) patterning a gap-spacing section of a substantially uniform thickness on the second surface of the silicon substrate circumscribing the diaphragm;
- (C) bonding a first insulating substrate to the first surface of the silicon substrate;
- (D) forming an electrode on a surface of a second insulating substrate;
- (E) aligning the silicon substrate and the second insulating substrate such that the gap-spacing section disposed on the second surface of the silicon substrate and the surface of the second insulating substrate are juxtaposed with the diaphragm and the electrode substantially overlapping; and
- (F) anodically bonding the silicon substrate and the second insulating substrate together to form a multilayered structure having the diaphragm and electrode separated by a distance including the thickness of the gap-spacing section.
- 2. The method of claim 1 wherein said step (A) further comprises etching the first surface of the silicon substrate to define a nozzle channel in communication with the ink ejection chamber.
- 3. The method of claim 1 wherein
- a nozzle opening is formed in the first insulating substrate; and
- wherein said bonding step (C) comprises bonding the first insulating substrate to the first surface of the silicon substrate thereby communicating the ejection chamber to the nozzle opening.
- 4. The method of claim 1, further comprising the step of:
- (G) etching a portion of the second surface of the silicon substrate adjacent the diaphragm to form a cavity proximate the diaphragm at one end and extending to an outlet port positioned at an edge of the silicon substrate.
- 5. The method of claim 4, wherein
- said aligning step (E) comprises aligning the silicon substrate and the second insulating substrate such that the gap-spacing section disposed on the second surface of the silicon substrate and the surface of the second insulating substrate are juxtaposed with the diaphragm and cavity of the silicon substrate substantially overlapping the electrode of the second insulating substrate; and
- wherein said bonding step (F) comprises anodically bonding the silicon substrate and the second insulating substrate together to form a multilayered structure including a vibration chamber in communication with the outlet port interposing the diaphragm and cavity of the silicon substrate and the electrode of the second insulating substrate.
- 6. The method of claim 5, further comprising the step of:
- (H) applying a viscous epoxy to the outlet port to seal-off the vibration chamber.
- 7. The method of claim 1, wherein said patterning step (B) further comprises etching the second surface of the silicon substrate to form a concave portion of substantially uniform depth surrounding the diaphragm.
- 8. The method of claim 1, wherein said patterning step (B) comprises patterning a gap-spacing section of SiO.sub.2 via one of a spattering process, a CVD process, a vapor deposition process, an ion-implanting process, a sol-gel process, a thermal oxidation process, and an organic silicon composition sintering process.
- 9. The method of claim 1, wherein said patterning step (B) comprises patterning a gap-spacing section of boro-silicated glass via a spattering process.
- 10. The method of claim 1 wherein the second insulating substrate is a substantially pure silicon substrate, and further comprising the step of:
- (I) doping the electrode of the second insulating substrate with a first type impurity; and
- (J) doping the diaphragm of the silicon substrate with a second type impurity.
- 11. The method of claim 1, wherein said bonding step (F) comprises the steps of:
- (F1) gradually heating the silicon substrate and the second insulating substrate;
- (F2) applying a voltage across the heated silicon substrate and the heated second insulating substrate for a preselected time period; and
- (F3) detecting and minimizing an electrostatic charge differential between the diaphragm and the electrode during the preselected time period to reduce electrostatic damage to the electrode.
- 12. A method for producing an electrostatically-driven ink jet head, comprising the steps of:
- (A) etching a first surface of a silicon substrate to define an ink ejection chamber therein, the ink ejection chamber including a deformable diaphragm interposing the first and an opposing second surface of the silicon substrate;
- (B) bonding a first insulating substrate to the first surface of the silicon substrate;
- (C) forming an electrode on a surface of a second insulating substrate;
- (D) patterning a gap-spacing section of substantially uniform thickness on the surface of the second insulating substrate circumscribing the electrode;
- (E) aligning the silicon substrate and the second insulating substrate such that the gap-spacing section disposed on the surface of the second insulating substrate and the second surface of the silicon substrate are juxtaposed with the diaphragm and the electrode substantially overlapping; and
- (F) anodically bonding the silicon substrate and the second insulating substrate together to form a multilayered structure having the diaphragm and electrode separated by a distance including the thickness of the gap-spacing section.
- 13. The method of claim 12 wherein said step (A) further comprises etching the first surface of the silicon substrate to define a nozzle channel in communication with the ink ejection chamber.
- 14. The method of claim 12 wherein;
- a nozzle opening is formed in the first insulating substrate; and
- said bonding step (C) comprises bonding the first insulating substrate to the first surface of the silicon substrate thereby communicating the ejection chamber to the nozzle opening.
- 15. The method of claim 12, further comprising the step of:
- (G) forming a terminal to supply a power voltage to the electrode on a portion of the surface of the second insulating substrate,
- (H) etching a portion of the surface of the second insulating substrate adjacent the electrode to form a cavity proximate the electrode at one end and extending to an outlet port positioned at a distal end of the terminal, and (I) forming a lead electrically connecting the terminal to the electrode within the cavity.
- 16. The method of claim 15, wherein said bonding step (F) comprises anodically bonding the silicon substrate and the second insulating substrate together to form a multilayered structure including a vibration chamber in communication with the outlet port, the vibration chamber interposing the diaphragm of the silicon substrate and the electrode of the second insulating substrate.
- 17. The method of claim 15, further comprising the step of (I) applying a viscous epoxy to the outlet port to seal-off the vibration chamber.
- 18. The method of claim 12, wherein
- said patterning step (D) further comprises etching the second insulating substrate to form a concave portion of substantially uniform depth on the surface of the second insulating substrate; and
- wherein said forming step (C) comprises forming the electrode within the concave portion of the second insulating substrate.
- 19. The method of claim 12, wherein said patterning step (D) further comprises patterning a gap-spacing section of SiO.sub.2 via one of a spattering process, a CVD process, a vapor deposition process, an ion-implanting process, a sol-gel process, a thermal oxidation process, and an organic silicon composition sintering process.
- 20. The method of claim 12, wherein said patterning step (D) comprises patterning a gap-spacing section of boro-silicated glass via a spattering process.
- 21. The method of claim 12, wherein the second insulating substrate is a substantially pure silicon substrate, and further comprising the step of:
- (J) doping the electrode of the second insulating substrate with a first type impurity; and
- (K) doping the diaphragm of the silicon substrate with a second type impurity.
- 22. The method of claim 12, wherein said bonding step (F) comprises the steps of:
- (F1) gradually heating the silicon substrate and the second insulating substrate;
- (F2) applying a voltage across the heated silicon substrate and the heated second insulating substrate for a preselected time period; and
- (F3) detecting and minimizing an electrostatic charge differential between the diaphragm and the electrode during the preselected time period to reduce electrostatic damage to the electrode.
- 23. A method for producing an electrostatically-driven ink jet head, comprising the steps of:
- (A) etching a first surface of a first silicon substrate to define an ink ejection chamber therein, the ink ejection chamber including a diaphragm extending to an opposing second surface of the first silicon substrate;
- (B) patterning an SiO.sub.2 membrane on the second surface of the first silicon substrate circumscribing the diaphragm;
- (C) forming an electrode on a surface of a second silicon substrate;
- (D) patterning an SiO.sub.2 membrane on the surface of the second silicon substrate circumscribing the electrode;
- (E) aligning the first and second silicon substrates such that their respective SiO.sub.2 membranes are juxtaposed with the diaphragm and the electrode substantially overlapping; and
- (F) bonding the first and second silicon substrates together at their respective SiO.sub.2 membranes via a direct Si--Si bonding process to form a multilayered structure having the diaphragm and electrode separated by a precise gap distance.
- 24. The method of claim 23, wherein said patterning steps (B) and (D) each comprise patterning an SiO.sub.2 membrane via one of a spattering process, a CVD process, a vapor deposition process, an ion-implanting process, a sol-gel process, a thermal oxidation process, and an organic silicon composition sintering process.
- 25. The method of claim 23, further comprising the step of:
- (G) doping the electrode of the second silicon substrate with a first type impurity; and
- (H) doping the diaphragm of the first silicon substrate with a second type impurity.
- 26. A method for producing an electrostatically-driven ink jet head, comprising the steps of:
- (A) etching a first surface of a silicon substrate to define an ink ejection chamber therein, the ink ejection chamber including a deformable diaphragm interposing the first and an opposing second surface of the silicon substrate;
- (B) etching a portion of the second surface of the silicon substrate adjacent the diaphragm to form a cavity proximate the diaphragm at one end and extending to an outlet port positioned at an edge of the silicon substrate;
- (C) forming an electrode on a surface of an insulating substrate;
- (D) aligning the silicon and insulating silicon substrates such that the second surface of the silicon substrate and the surface of the insulating substrate are juxtaposed with the diaphragm and cavity of the silicon substrate substantially overlapping the electrode of the insulating substrate;
- (E) anodically bonding the silicon and insulating substrates together to form a multilayered structure including a vibration chamber in communication with the outlet port, the vibration chamber separating the diaphragm and cavity of the silicon substrate from the electrode of the insulating substrate; and
- (F) applying a viscous epoxy to the outlet port to seal-off the vibration chamber.
- 27. The method of claim 26, wherein the viscous epoxy comprises a thermal plastic resin.
- 28. The method of claim 26, further comprising the step of:
- (F) doping the electrode of the insulating substrate with a first type impurity; and
- (G) doping the diaphragm of the silicon substrate with a second type impurity.
- 29. The method of claim 26, wherein said bonding step (E) comprises the steps of:
- (E1) gradually heating the silicon and insulating substrates;
- (E2) applying a voltage across the heated silicon and insulating substrates for a preselected time period; and
- (E3) detecting and minimizing an electrostatic charge differential between the diaphragm and the electrode during the preselected time period to reduce electrostatic damage to the electrode.
- 30. The method of claim 29, wherein said detecting and minimizing step (E3) comprises eliminating the detected charge differential between the diaphragm and electrode by electrically shunting the diaphragm to the electrode during the preselected time period.
- 31. A method for producing an ink jet head, comprising the steps of:
- (A) selectively etching a first surface of a silicon substrate to define a plurality of substantially concave ink ejection chambers;
- (B) etching portions of the second surface of the silicon substrate beneath each ink ejection chamber to form a corresponding plurality of thin diaphragms, each diaphragm interposing a corresponding ink ejection chamber and the second surface of the fsilicon substrate;
- (C) bonding a first insulating substrate to the first surface of the silicon substrate;
- (D) forming a corresponding plurality of electrodes on a surface of a second insulating substrate;
- (E) aligning the silicon and second insulating substrates such that the second surface of the silicon substrate and the surface of the insulating substrate are juxtaposed with each silicon substrate diaphragm in facing relation with a corresponding electrode of the second insulating substrate; and
- (F) bonding the silicon and second insulating substrates together to form a multilayered structure which separates each diaphragm from its corresponding electrode by a predetermined gap distance.
- 32. A method for producing an ink jet head, comprising the steps of:
- (A) selectively etching a first surface of a silicon substrate to define a plurality of substantially concave ink ejection chambers;
- (B) bonding a first insulating substrate to the first surface of the silicon substrate;
- (C) forming a corresponding plurality of electrodes on a surface of a second insulating substrate;
- (D) patterning a gap-spacing section of substantially uniform thickness on the surface of the second insulating substrate circumscribing each electrode;
- (E) aligning the silicon and second insulating substrates such that the second surface of the silicon substrate and the surface of the insulating substrate are juxtaposed with each silicon substrate diaphragm in facing relation with a corresponding electrode of the second insulating substrate; and
- (F) bonding the silicon and second insulating substrates together to form a multilayered structure which separates each diaphragm from its corresponding electrode by a predetermined gap distance.
Priority Claims (8)
Number |
Date |
Country |
Kind |
2-252252 |
Sep 1990 |
JPX |
|
2-307855 |
Nov 1990 |
JPX |
|
2-309335 |
Nov 1990 |
JPX |
|
3-140009 |
Jun 1991 |
JPX |
|
4-145764 |
Jun 1992 |
JPX |
|
4-153808 |
Jun 1992 |
JPX |
|
4-181233 |
Jul 1992 |
JPX |
|
4-181240 |
Jul 1992 |
JPX |
|
CROSS REFERENCE TO RELATED APPLICATIONS
This is a Divisional of pending prior application Ser. No. 08/477,681 filed on Jun. 7, 1995 which is a continuation-in-part of Ser. No. 07/757,691, filed on Sep. 11, 1991, now U.S. Pat. No. 5,534,900, and Ser. No. 08/069,198 filed on May 28, 1993, which is now abandoned, the contents of which are incorporated herein by reference.
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Non-Patent Literature Citations (1)
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Patent Abstract of Japan, Oct. 29, 1998, vol. 18, No. 66. |
Divisions (1)
|
Number |
Date |
Country |
Parent |
477681 |
Jun 1995 |
|
Continuation in Parts (2)
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Number |
Date |
Country |
Parent |
757691 |
Sep 1991 |
|
Parent |
069198 |
May 1993 |
|