Claims
- 1. A method of erasing a non-volatile memory cell with a nitride tunneling layer, comprising:providing a non-volatile memory cell comprising a substrate, a nitride tunneling layer disposed on the substrate, a charge trapping layer having hot electrons and disposed on the nitride tunneling layer, a dielectric layer disposed on the charge-trapping layer, a gate conductive layer disposed on the dielectric layer, a source region and a drain region disposed in the substrate adjacent to the nitride tunneling layer; applying a first positive bias to the drain region; applying a second positive bias to the gate conductive layer; and grounding the source region and the substrate; wherein the first positive bias and the second positive bias are both sufficient to inject hot electron holes into the charge-trapping layer through the nitride tunneling layer to combine with hot electrons in the charge-trapping layer for erasing the non-volatile memory cell.
- 2. The method of claim 1, wherein the first positive bias ranges from about 2V to about 5V.
- 3. The method of claim 1, wherein the second positive bias ranges from about 2.5V to about 5V.
- 4. A method of erasing a non-volatile memory cell with a nitride tunneling layer, comprising:providing a non-volatile memory cell comprising a substrate, a nitride tunneling layer disposed on the substrate, a charge-trapping layer having hot electrons and disposed on and in direct contact with the nitride tunneling layer, a dielectric layer disposed on the charge-trapping layer, a gate conductive layer disposed on the dielectric layer, a source region and a drain region disposed in the substrate adjacent to the nitride tunneling layer; applying a first positive bias to the drain region; applying a second positive bias to the gate conductive layer; and grounding the source region and the substrate; wherein the first positive bias and the second positive bias are both sufficient to inject hot electron holes into the charge-trapping layer through the nitride tunneling layer to combine with hot electrons in the charge-trapping layer for erasing the non-volatile memory cell.
- 5. The method of claim 4, wherein the first positive bias ranges from about 2V to about 5V.
- 6. The method of claim 4, wherein the second positive bias ranges from about 2.5V to about 5V.
Priority Claims (1)
Number |
Date |
Country |
Kind |
90129931 A |
Dec 2001 |
TW |
|
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90129931, filed Dec. 4, 2001.
US Referenced Citations (17)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2001229683 |
Aug 2001 |
JP |