Embodiments of the present invention relate generally to a semiconductor device fabrication process. In particular, an embodiment of the present invention relates to a semiconductor device fabrication process that provides short channel effect control.
Many conventional semiconductor device fabrication processes produce semiconductor devices that exhibit short channel effects. Consequently, the development of processes that yield devices where the short channel effect is controlled in the devices that are produced is one of the biggest challenges confronting device manufacturers. The primary impact of the short channel effect is to cause an increase in the leakage or “off” current that is exhibited by a device when the device is in the off state. This leakage impacts the capacity of the device to perform ideally as a switch. A conventional process that illustrates this problem is shown in
A first layer of polysilicon 120 is then deposited on the surface of the remaining material (e.g., see
As is shown in
Problematic short channel effects result from the heavy VCI implantation 123 needed to form conductive lines that have low resistance. It should be appreciated that the effective channel length (e.g., Leff) of the fabricated device is decreased as a result of the lateral diffusion of the source junction caused by such heavy VCI implantation 123. This lateral diffusion may significantly degrade the performance of the device.
Accordingly, a need exists for a method that provides short channel effect control by using a shallow source implant. The present invention provides a method that accomplishes this need.
For instance, one embodiment of the present invention includes a method for fabricating a semiconductor device having improved short channel effects. The method includes operations such as, forming a hard mask layer on the surface of a semiconductor substrate, printing a photoresist mask above the hard mask layer, performing an etch of trenches in the semiconductor substrate and removing the hard mask layer and the photoresist mask. Moreover, the method includes forming a first polysilicon layer, etching the first polysilicon layer, forming a spacer layer and forming a second polysilicon layer. In addition, the method includes performing a stacked gate etch on the second polysilicon layer, performing an SAS etch, performing a shallow source implant and forming a spacer between the first polysilicon layer and the second polysilicon layer. A silicide line is subsequently deposited to connect device source regions.
These and other advantages of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiments which are illustrated in the drawing figures.
The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
Reference will now be made in detail to the preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. While the invention will be described in conjunction with the preferred embodiments, it will be understood that they are not intended to limit the invention to these embodiments. On the contrary, the invention is intended to cover alternatives, modifications and equivalents, which may be included within the spirit and scope of the invention as defined by the appended claims. Furthermore, in the following detailed description of the present invention, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, and components have not been described in detail as not to unnecessarily obscure aspects of the present invention.
According to one embodiment, the short circuiting together of the first and second polysilicon layers (e.g., 209 and 211 respectively) may be prevented by forming a spacer layer between the two polysilicon layers. According to this embodiment, the spacer layer may be formed by using a deposited ONO spacer layer 207. It should be appreciated that the stacked gate structure shown in
At step 401, a hard mask layer is formed on the surface of a semiconductor substrate and a photoresist mask is printed above the hard mask layer. At step 403, an etch of trenches is performed in the semiconductor substrate and the hard mask layer and the photoresist mask are removed.
At step 405, a first polysilicon layer is formed and etched and a spacer layer deposited thereon. At step 407, a second polysilicon layer is deposited, a stacked gate etch of the second polysilicon layer is performed and an SAS etch is performed.
At step 409, a shallow source implant is performed and a spacer layer is formed between said first polysilicon layer and said second polysilicon layer. And, at step 411 a silicide line to connect the semiconductor device source regions is formed.
Thus, a method for fabricating a semiconductor device having improved short channel effects is disclosed. The method includes operations such as, forming a hard mask layer on the surface of a semiconductor substrate, printing a photoresist mask above the hard mask layer, performing an etch of trenches in the semiconductor substrate and removing the hard mask layer and the photoresist mask. Moreover, the method includes forming a first polysilicon layer 209, etching the first polysilicon layer, depositing an ONO layer 207 and depositing a second polysilicon layer 211. In addition, the method includes performing a stacked gate etch on the second polysilicon layer, performing an SAS etch, performing a shallow source implant 203 and forming a spacer 207 between the first polysilicon layer 209 and the second polysilicon layer 211. A silicide line 301 (e.g., VSS) is subsequently deposited to connect device source regions.
The foregoing descriptions of specific embodiments of the present invention have been presented for purposes of illustration and description. They are not intended to be exhaustive or to limit the invention to the precise forms disclosed, and obviously many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the Claims appended hereto and their equivalents.
Number | Name | Date | Kind |
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6171939 | Lin | Jan 2001 | B1 |
6268247 | Cremonesi et al. | Jul 2001 | B1 |