Patent Application
20090094564
The embodiments of the invention generally relate to a method for quickly tracing minimum-length return paths through any electronic structure, such as multi-layer circuit packages.
In electronic circuits, currents flow in closed loops. Typically, signal currents flow on dedicated conductive signal wires and vias, and return currents (which complete each current loop) flow on conductive power-supply networks that fill the space around signal wires and vias with geometrically complicated 3-dimensional structures. Return currents diffuse through the power-supply structures under the impetus of voltage gradients.
Typically, there are many conductive paths that a given return current can follow. Achieving good signal integrity requires that continuous conductive return paths closely follow each signal path. The first step in determining whether a particular electronic design achieves this goal within acceptable margins is identifying, for each signal path, the return path that most closely follows the signal path among a plurality of possible conductive return paths.
The invention comprises a method for quickly tracing minimum-length conductive return paths through multi-layered circuit packages (this method works for chips, packages, boards, or any electronic structure). It utilizes a raster based (cellular) memory model comprising individual grids for each package layer. Each grid comprises a reduced resolution N×M cell representation of the conductive structures on that layer. Cellular methodologies are then used to determine, for each signal net, the shortest return path. This information can then be used for various purposes, including determining if the return path is sufficient to ensure adequate signal integrity.
Some advantages of this method are simplicity and speed. The cellular nature of the methodology allows for a decomposition of the problem into a series of relatively straightforward steps, each of which can be made to execute very efficiently. On a typical workstation, return paths can be traced at the rate of 50-100 per second.
These and other aspects of the embodiments of the invention will be better appreciated and understood when considered in conjunction with the following description and the accompanying drawings. It should be understood, however, that the following descriptions, while indicating embodiments of the invention and numerous specific details thereof, are given by way of illustration and not of limitation. Many changes and modifications may be made within the scope of the embodiments of the invention without departing from the spirit thereof, and the embodiments of the invention include all such modifications.
The embodiments of the invention will be better understood from the following detailed description with reference to the drawings, in which:
The embodiments of the invention and the various features and advantageous details thereof are explained more fully with reference to the non-limiting embodiments that are illustrated in the accompanying drawings and detailed in the following description. It should be noted that the features illustrated in the drawings are not necessarily drawn to scale. Descriptions of well-known components and processing techniques are omitted so as to not unnecessarily obscure the embodiments of the invention. The examples used herein are intended merely to facilitate an understanding of ways in which the embodiments of the invention may be practiced and to further enable those of skill in the art to practice the embodiments of the invention. Accordingly, the examples should not be construed as limiting the scope of the embodiments of the invention.
As mentioned above, the invention comprises a method for quickly tracing minimum-length electrically conductive return paths through multi-layered circuit packages (this method works for chips, packages, boards, or any electronic structure). The methods herein utilize a raster based (cellular) memory model comprising individual grids for each package layer. The methods disclosed herein provide a simple and efficient solution to a conceptually difficult problem which would otherwise require net simulation. If an acceptable return path does not exist, this method discovers that fact quickly. The cellular nature of the method allows for a decomposition of the problem into a series of relatively straightforward steps.
As shown in flowchart form in
Most signal layers are positioned between power or ground layers or planes, and a portion of a net is considered well-referenced if the adjacent power or ground layer has matching conductors in the region directly above or below that portion of the net. Therefore, in “well-referenced” portions of nets, the power or ground conductors directly above or below that portion of the net match the signal wires in that portion of the net, making the return path match the signal path. However, such is not always the case and many of the portions of each of the nets will not be well-reference.
In item 104, for each unreferenced portion of the net, the invention traces the shortest path or sub-path (through the reference metal) from its starting point to it's ending point. To the contrary, each well-referenced portion of a net cannot be improved upon because it already is as short as possible, and such well-referenced portions of nets will be used to the fullest extent that they are available as sub-paths of the overall shortest return path that is arrived upon by the invention. In other words, for each portion of each net that is well-referenced, the method identifies the matching conductors in the ground or power plane as the shortest return path.
Thus, each return path will have multiple sub-paths, alternating between well-referenced sections of the signal net, and the unreferenced “excursions” from the signal net traced in item 104. Each sub-path may comprise multiple horizontal and vertical segments. Each sub-path of an unreferenced or not well-referenced section (called an “excursion”), can be determined, for example, through a stepwise cellular expansion process (cell-by-cell process) that is discussed in greater detail below with respect to
More specifically, the processing in item 100 is shown in greater detail in flowchart form in
As shown in
A cell's neighbors are the eight cells immediately adjacent to it. For vertical structures (vias, pins, etc.), the cells above and below are also neighbors. In item 404, if a neighbor cell is the searched-for ending point, the process is complete, otherwise processing proceeds to item 406. The shortest sub-path can be determined by retracing the cells that led to it by using the directional information stored in each cell. The method takes the next cell from the frontier, and repeats the process beginning with item 402 as shown by the arrow from 406 to 402. This process continues, removing cells from one end of the frontier, and adding them to the other, until either the ending point is reached, or the frontier becomes empty (meaning that no path exists), as shown by item 406. The search process can be thought of as a uniformly expanding bubble that will eventually make contact with the searched-for ending point. This first contact indicates the shortest path from starting point to ending point.
The foregoing expansion from neighbor cell to neighbor cell is three-dimensional, because via cells allow cells in neighboring layers to be added to the fringe. Because expansion is restricted to metal of the reference net, paths can be traced around obstacles (including voids), and from layer to layer through vias until the ending point is found.
The embodiments of the invention can take the form of a computer program product accessible from a computer-usable or computer-readable medium providing program code for use by or in connection with a computer or any instruction execution system. For the purposes of this description, a computer-usable or computer readable medium can be any apparatus that can comprise, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device.
The foregoing description of the specific embodiments will so fully reveal the general nature of the invention that others can, by applying current knowledge, readily modify and/or adapt for various applications such specific embodiments without departing from the generic concept, and, therefore, such adaptations and modifications should and are intended to be comprehended within the meaning and range of equivalents of the disclosed embodiments. It is to be understood that the phraseology or terminology employed herein is for the purpose of description and not of limitation. Therefore, while the embodiments of the invention have been described in terms of embodiments, those skilled in the art will recognize that the embodiments of the invention can be practiced with modification within the spirit and scope of the appended claims.
