Patent Application
20240274049
This U.S. non-provisional patent application claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0017606, filed on Feb. 9, 2023, the entire contents of which are hereby incorporated by reference.
The present disclosure herein relates to a method for repairing a display panel and a display panel repaired by using the same.
Display devices such as televisions, mobile phones, tablets, navigation system units, and game consoles provide images to users through a display screen and include a display panel including a plurality of pixels. Each of the pixels may include a light emitting element for generating light and a circuit unit for controlling the amount of current flowing through the light emitting element. However, when a leakage current is generated in the circuit unit of any one pixel among the pixels, it affects circuit units of adjacent pixels, so that the display quality of the display panel may be degraded.
The present disclosure provides a method for repairing a display panel for preventing a problem in which the voltage of adjacent pixels rises due to the circuit unit of a damaged pixel. The present disclosure also provides a display panel repaired by the repair method of the inventive concept, thereby being prevented from having degraded display quality.
An embodiment of the inventive concept provides a method for repairing a display panel, the method including inspecting a display panel including pixels arranging along a first direction and a second direction crossing the first direction to detect a defective pixel among the pixels, and cutting an initialization voltage line disposed between the defective pixel detected in the detecting of a defective pixel and pixels disposed adjacent to the defective pixel to isolate the defective pixel from the initialization voltage line.
In an embodiment, the display panel may include an initialization voltage line electrically connected to the pixels to apply the initialization voltage, and each of the pixels may include a circuit unit including transistors and a capacitor, and a light emitting element electrically connected to the circuit unit. In an embodiment, among the transistors, an initialization transistor may include a semiconductor pattern connected to the initialization voltage line.
In an embodiment, the initialization voltage line may include a first initialization voltage line portion formed as a single body with the semiconductor pattern of the initialization transistor, and a second initialization voltage line portion intersecting the first initialization voltage line portion in a plan view and electrically connected to the first initialization voltage line portion. In an embodiment, the cut portion may be formed such that a portion connected to the semiconductor pattern of the initialization transistor of the defective pixel from the first initialization voltage line portion is cut.
In an embodiment, the semiconductor pattern of the initialization transistor of the defective pixel may extend from the initialization voltage line, and the cut portion may be formed such that a portion of the semiconductor pattern of the defective pixel is cut.
In an embodiment of the inventive concept, a display panel includes pixel units each including at least one pixel, and arranged along a first direction and a second direction intersecting the first direction, and an initialization voltage line electrically connected to the pixels of the pixel units to apply an initialization voltage. In an embodiment, in a first pixel among the pixels, the initialization voltage line connected to the first pixel includes a cut portion.
In an embodiment, the initialization voltage line may include first initialization voltage line portions extending in the first direction and arranged in the second direction, and second initialization voltage line portions extending in the second direction and arranged in the first direction and electrically connected to the first initialization voltage line portions.
In an embodiment, the first initialization voltage line portions and the second initialization voltage line portions may be disposed on different layers, respectively.
In an embodiment, the first initialization voltage line portions and the second initialization voltage line portions may include different materials.
In an embodiment, the electrical conductivity of the second initialization voltage line portions may be greater than the electrical conductivity of the first initialization voltage line portions.
In an embodiment, each of the pixels may include a circuit unit including transistors and a capacitor, and a light emitting element electrically connected to the circuit unit, wherein an initialization transistor among the transistors may include a semiconductor pattern connected to a corresponding first initialization voltage line portion among the first initialization voltage line portions.
In an embodiment, the corresponding first initialization voltage line portion and the semiconductor pattern of the initialization transistor may be formed as a single body on the same layer.
In an embodiment, the pixel units may include pixel rows defined by pixel units arranged along the first direction among the pixel units, and the first initialization voltage line portions may be respectively disposed in the pixel rows.
In an embodiment, the pixel units may include pixel columns arranged along the second direction among the pixel units, and the second initialization voltage line portions may be respectively disposed in n number of pixel columns, where the n may be a natural number of 1 or greater.
In an embodiment, any one first initialization voltage line portion among the first initialization voltage line portions may be connected to a pixel row including the first pixel among the pixel rows, and the cut portion may be formed in the any one first initialization voltage line portion.
In an embodiment, the cut portion may include a first cut portion and a second cut portion which are formed by cutting a portion of the any one first initialization voltage line portion, and a line portion positioned between the first cut portion and the second cut portion may be connected to the first pixel.
In an embodiment, the first pixel may be electrically insulated from the any one first initialization voltage line portion by the first cut portion and the second cut portion.
In an embodiment, the initialization transistor of the first pixel may include a semiconductor pattern extending from any one first initialization voltage line portion among the first initialization voltage line portions, and the cut portion may be formed in a portion of the semiconductor pattern of the first pixel. In an embodiment, the first pixel may be electrically insulated from the any one first initialization voltage line portion by the cut portion.
In an embodiment, each of the circuit units of the pixels of the pixel units may include a semiconductor pattern layer including the first initialization voltage line portions, and a conductive pattern layer disposed on the semiconductor pattern layer and including the second initialization voltage line portions, wherein the cut portion may be disposed not to overlap the conductive pattern layer in a plan view.
In an embodiment, the display panel may further include a driving voltage line extending in the second direction and electrically connected to the pixels of the pixel units to apply a driving voltage, wherein the driving voltage line and the second initialization voltage line portions may be disposed on the same layer.
In an embodiment, the driving voltage line may be arranged spaced apart from the second initialization voltage line portions in the first direction.
The accompanying drawings are included to provide a further understanding of the inventive concept, and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the inventive concept and, together with the description, serve to explain principles of the inventive concept. In the drawings:
The inventive concept may be modified in many alternate forms, and thus specific embodiments will be exemplified in the drawings and described in detail. It should be understood, however, that it is not intended to limit the inventive concept to the particular forms disclosed, but rather, is intended to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the inventive concept.
In the present disclosure, when an element (or a region, a layer, a portion, etc.) is referred to as being “on,” “connected to,” or “coupled to” another element, it means that the element may be directly disposed on/connected to/coupled to the other element, or that a third element may be disposed therebetween.
Like reference numerals refer to like elements. Also, in the drawings, the thickness, the ratio, and the dimensions of elements are exaggerated for an effective description of technical contents. The term “and/or” includes any and all combinations of one or more of which associated elements may define.
It will be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and a second element may also be referred to as a first element in a similar manner without departing the scope of rights of the present invention. The terms of a singular form may include plural forms unless the context clearly indicates otherwise.
In addition, terms such as “below,” “lower,” “above,” “upper,” and the like are used to describe the relationship of the elements shown in the drawings. The terms are used as a relative concept and are described with reference to the direction indicated in the drawings.
It should be understood that the term “comprise,” or “have” is intended to specify the presence of stated features, integers, steps, operations, elements, components, or combinations thereof in the disclosure, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention pertains. It is also to be understood that terms such as terms defined in commonly used dictionaries should be interpreted as having meanings consistent with the meanings in the context of the related art, and should not be interpreted in too ideal a sense or an overly formal sense unless explicitly defined herein.
Hereinafter, a pixel and a display panel according to an embodiment of the inventive concept will be described with reference to the accompanying drawings.
The display device DD may be a device which is activated in response to an electrical signal and displays images. For example, the display device DD may be a large-sized device such as a television and an external billboard as well as a small-and-medium-sized device such as a monitor, a mobile phone, a tablet, a navigation system unit, and a game console. However, the above-described embodiments of the display device DD are only exemplary, and the inventive concept is not limited to any one embodiment as long as the embodiments do not depart from the inventive concept.
Referring to
The driving controller 100 may receive an image input signal RGB and a control signal CTRL. The image input signal RGB and the control signal CTRL may be provided from a main controller (or a graphic processor).
The driving controller 100 may generate an image data signal DATA obtained by converting data format of the image input signal RGB to meet interface specifications of the data driving circuit 200. The driving controller 100 may output a scan control signal SCS, a data control signal DCS, and an emission control signal ECS.
The data driving circuit 200 may receive the data control signal DCS and the image data signal DATA from the driving controller 100. The data driving circuit 200 may convert the image data signal DATA into data signals, and may output the data signals to a plurality of data lines DL1 to DLm. The data signals may be analog voltages corresponding to gray scale values of the image data signal DATA.
The voltage generator 300 may generate voltages necessary for the operation of the display panel DP. In an embodiment, the voltage generator 300 may generate driving voltages DV. The driving voltages DV may include a plurality of voltages which have different voltage levels from each other. For example, the driving voltages DV may include a first driving voltage ELVDD (see
The display panel DP according to an embodiment of the inventive concept may be a light emitting type display panel, but is not particularly limited thereto. For example, the display panel DP may be an organic light emitting display panel, an inorganic light emitting display panel, or a quantum dot light emitting display panel. A light emitting layer of the organic light emitting display panel may include an organic light emitting material, and a light emitting layer of the inorganic light emitting display panel may include an inorganic light emitting material. A light emitting layer of the quantum dot light emitting display panel may include a quantum dot, a quantum load, and the like. Hereinafter, the display panel DP will be described as an organic light emitting display panel.
The display panel DP may include first scan lines GIL0 to GILn, second scan lines GWL1 to GWLn, emission control lines EML1 to EMLn, data lines DL1 to DLm, and pixels PX. The display panel DP may include a scan driving circuit SDC and an emission driving circuit EDC which are directly formed in the display panel DP. However, the embodiment of the inventive concept is not limited thereto and at least one of the scan driving circuit SDC or the emission driving circuit EDC may be provided in the form of a driving chip and electrically connected to the display panel DP.
In an embodiment illustrated in
The first scan lines GIL0 to GILn and the second scan lines GWL1 to GWLn may extend along a first direction DR1 and electrically connected to the scan driving circuit SDC. The emission control lines EML1 to EMLn may extend along the first direction DR1 and electrically connected to the emission driving circuit EDC. The first scan lines GIL0 to GILn, the second scan lines GWL1 to GWLn, and the emission control lines EML1 to EMLn may be arranged spaced apart from each other in a second direction DR2.
The data lines DL1 to DLm may extend along the second direction DR2 and connected to the data driving circuit 200. The data lines DL1 to DLm may be arranged spaced apart from each other in the first direction DR1.
The pixels PX may each be electrically connected to corresponding signal lines among the first scan lines GIL0 to GILn, the second scan lines GWL1 to GWLn, the emission control lines EML1 to EMLn, and the data lines DL1 to DLm. However, the embodiment of the pixels PX illustrated in
The scan driving circuit SDC may receive the scan control signal SCS from the driving controller 100. In response to the scan control signal SCS, the scan driving circuit SDC may output first scan signals to the first scan lines GIL0 to GILn, and may output second scan signals to the second scan lines GWL1 to GWLn.
The emission driving circuit EDC may receive the emission control signal ECS from the driving controller 100. In response to the emission control signal ECS, the emission driving circuit EDC may output emission signals to the emission control lines EML1 to EMLn.
Each of the pixels PX constituting the display panel DP may include a light emitting element ED (see
The pixels PX may be provided with data voltages in response to scan signals. The pixels PX may display an image by emitting light of luminance corresponding to the data voltages in response to emission signals. The emission duration of the pixels PX may be controlled by the emission signals. As a result, the display panel DP may output an image through the pixels PX.
The pixels PX may include pixels emitting light of different colors from each other. For example, the pixels PX may include red pixels configured to output red light, green pixels configured to output green light, and blue pixels configured to output blue light, and each of the pixel units may include a red pixel, a green pixel, and a blue pixel. Light emitting layers of a light emitting element of the red pixel, a light emitting element of the green pixel, and a light emitting element of the blue pixel may be respectively formed of different materials. However, the embodiment of the inventive concept is not necessarily limited thereto.
Referring to
The circuit unit PXC may include first to eighth transistors T1 to T8 and at least one capacitor, and
The j-th first scan line GILj, the j-th second scan line GWLj, the j-th third scan line GCLj, and the j-th fourth scan line GBLj may respectively transmit a j-th first scan signal GIj, a j-th second scan signal GWj, a j-th third scan signal GCj, and a j-th fourth scan signal GBj. The j-th emission control line EMLj may transmit an emission signal EMj, and the i-th data line DLi may transmit a data signal Di. The data signal Di may have a voltage level corresponding to the image input signal RGB (see
First to fifth voltage lines VL1, VL2, VL3, VL4, and VL5 may respectively transmit the first driving voltage ELVDD, the second driving voltage ELVSS, a first initialization voltage VINT, a second initialization voltage AINT, and a bias voltage Vbias. In the present embodiment, the first and second voltage lines VL1 and VL2 may be respectively defined as first and second driving voltage lines, and the third and fourth voltage lines VL3 and VL4 may be respectively defined as first and second initialization voltage lines.
In the present embodiment, the light emitting element ED may be an organic light emitting element. The light emitting element ED may include an anode AE and a cathode CE. The anode AE of the light emitting element ED may be electrically connected to, via at least one transistor, the first voltage line VL1 to which the first driving voltage ELVDD is transmitted, and the cathode CE of the light emitting element ED may be electrically connected to the second voltage line VL2 to which the second driving voltage ELVSS is transmitted.
Each of the first to eighth transistors T1 to T8 may include a first electrode, a second electrode, and a gate electrode. According to an embodiment of the inventive concept, the first electrode and the second electrode may be respectively defined as an input electrode or an output electrode (or a source electrode or a drain electrode). In the present disclosure, “being electrically connected between a transistor and a signal line or between a transistor and a transistor” means that “an electrode of the transistor has a shape of a single body with the signal line, or is connected through a connection electrode.”
The first transistor T1 may be electrically connected between the first voltage line VL1 and the anode AE of the light emitting element ED. The first transistor T1 may include the first electrode electrically connected to the first voltage line VL1 via the fifth transistor T5, the second electrode electrically connected to a second node N2 to which the anode AE of the light emitting element ED is connected via the sixth transistor T6, and the gate electrode electrically connected to a first nod N1 to which the capacitor Cst is connected. The first transistor T1 may receive the data signal Di transmitted by the data line DLi in accordance with a switching operation of the second transistor T2, and supply a driving current to the light emitting element ED. In the present embodiment, the first transistor T1 may be defined as a driving transistor.
The second transistor T2 may be electrically connected between the data line DLj and the first electrode of the first transistor T1. The second transistor T2 may include the first electrode electrically connected to the data line DLi, the second electrode electrically connected to the first electrode of the first transistor T1, and the gate electrode electrically connected to the j-th second scan line GWLj. The second transistor T2 may be turned on according to the second scan signal GWj received through the j-th second scan line GWLj and transmit the data signal Di transmitted from the data line DLi to the first transistor T1. In the present embodiment, the second transistor T2 may be defined as a switching transistor.
The third transistor T3 may be electrically connected between the second electrode of the first transistor T1 and the gate electrode of the first transistor T1. The third transistor T3 may include the first electrode electrically connected to a first node N1, the second electrode electrically connected to a second node N2, and the gate electrode electrically connected to the j-th third scan line GCLj. That is, the first electrode of the third transistor T3 may be connected to the first node N1 which is electrically connected to the gate electrode of the first transistor T1, and the second electrode of the third transistor T3 may be connected to the second node N2 which is electrically connected to the second electrode of the first transistor T1.
The third transistor T3 may be turned on according to the third scan signal GCj received through the j-th third scan line GCLj and electrically connect the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. That is, the first transistor T1 may be diode-connected by the third transistor T3. In the present embodiment, the third transistor T3 may be defined as a compensation transistor.
The third transistor T3 may include first and second sub-transistors T3-1 and T3-2. The first and second sub-transistors T3-1 and T3-2 may be connected in series between the first node N1 and the second node N2.
The first sub-transistor T3-1 may include a first electrode electrically connected to the first node N1, a second electrode connected to the second sub-transistor T3-2, and a gate electrode electrically connected to the j-th third scan line GCLj. The first electrode of the first sub-transistor T3-1 may correspond to the first electrode of the third transistor T3. The second sub-transistor T3-2 may include a first electrode connected to the first sub-transistor T3-1, a second electrode electrically connected to the second node N2, and a gate electrode electrically connected to the j-th third scan line GCLj. The second electrode of the second sub-transistor T3-2 may correspond to the second electrode of the third transistor T3.
The third transistor T3 may include a double gate electrode corresponding to the gate electrodes of the first and second sub-transistors T3-1 and T3-2. Since the third transistor T3 includes the double gate electrode, the leakage current of the pixel PXij may be reduced. However, the embodiment of the inventive concept is not limited thereto, and the third transistor T3 may include a single gate electrode.
The fourth transistor T4 may be electrically connected between the first node N1 and the third voltage line VL3. The fourth transistor T4 may include the first electrode electrically connected to the first node N1, the second electrode electrically connected to the third voltage line VL3 to which the initialization voltage VINT is transmitted, and the gate electrode electrically connected to the j-th first scan line GILj.
The fourth transistor T4 may be turned on according to the first scan signal GIj received through the j-th first scan line GILj and transmit the initialization voltage VINT to the gate electrode of the first transistor T1 electrically connected to the first node N1, and may initialize the voltage of the gate electrode of the first transistor T1. In the present embodiment, the fourth transistor T4 may be defined as an initialization transistor.
The fourth transistor T4 may include third and fourth sub-transistors T4-1 and T4-2. The third and fourth sub-transistors T4-1 and T4-2 may be connected in series between the first node N1 and the third voltage line VL3.
The third sub-transistor T4-1 may include a first electrode electrically connected to the first node N1, a second electrode connected to the fourth sub-transistor T4-2, and a gate electrode electrically connected to the j-th first scan line GILj. The first electrode of the third sub-transistor T4-1 may correspond to the first electrode of the fourth transistor T4. The fourth sub-transistor T4-2 may include a first electrode connected to the third sub-transistor T4-1, a second electrode electrically connected to the third voltage line VL3, and a gate electrode electrically connected to the j-th first scan line GILj. The second electrode of the fourth sub-transistor T4-2 may correspond to the second electrode of the fourth transistor T4.
The fourth transistor T4 may include a double gate electrode corresponding to the gate electrodes of the third and fourth sub-transistors T4-1 and T4-2. Since the fourth transistor T4 includes the double gate electrode, the leakage current of the pixel PXij may be reduced. However, the embodiment of the inventive concept is not limited thereto, and the fourth transistor T4 may include a single gate electrode.
The fifth transistor T5 may be electrically connected between the first power line VL1 and the first transistor T1. The fifth transistor T5 may include the first electrode electrically connected to the first voltage line VL1, the second electrode electrically connected to the first electrode of the first transistor T1, and the gate electrode electrically connected to the j-th emission control line EMLj.
The sixth transistor T6 may be electrically connected between the first transistor T1 and the light emitting element ED. The sixth transistor T6 includes the first electrode electrically connected to the second node N2 to which the second electrode of the first transistor T1 is connected, the second electrode electrically connected to the anode AE of the light emitting element ED, and the gate electrode electrically connected to the j-th emission control line EMLj.
The fifth transistor T5 and the sixth transistor T6 may be turned on according to the emission signal EMj transmitted through the j-th emission control line EMLj. The emission duration of the light emitting element ED may be controlled by the emission signal EMj. In the present embodiment, the fifth transistor T5 and the sixth transistor T6 may be defined as emission control transistors.
When the fifth transistor T5 and the sixth transistor T6 are turned on, a driving current is generated according to a voltage difference between a gate voltage of the gate electrode of the first transistor T1 and the first driving voltage ELVDD, and the driving current is supplied to the light emitting element ED through the sixth transistor T6, so that the light emitting element ED may emit light.
The seventh transistor T7 may be electrically connected between the fourth voltage line VL4 and the anode AE to which the sixth transistor T6 is connected. The seventh transistor T7 may include the first electrode electrically connected to the fourth voltage line VL4, the second electrode electrically connected to the anode AE to which the second electrode of the sixth transistor T6 is connected, and the gate electrode electrically connected to the j-th fourth scan line GBLj.
The eighth transistor T8 may be electrically connected between the fifth voltage line VL5 and the first transistor T1. The eighth transistor T8 may include the first electrode electrically connected to the fifth voltage line VL5, the second electrode electrically connected to the first electrode of the first transistor T1, and the gate electrode electrically connected to the j-th fourth scan line GBLj.
The seventh transistor T7 and the eighth transistor T8 may be turned on according to the j-th fourth scan signal GBj transmitted through the j-th fourth scan line GBLj. In the present embodiment, the seventh transistor T7 and the eighth transistor T8 may be defined as initialization transistors.
As the seventh transistor T7 is turned on, the second initialization voltage AINT may be provided to the anode AE of the light emitting element ED. The seventh transistor T7 may initialize the anode AE of the light emitting element ED to the second initialization voltage AINT. That is, the seventh transistor T7 may prevent the light emitting element ED from instantaneously emitting light at high luminance due to a voltage remaining in the anode AE at the beginning of the driving of the light emitting element ED.
The second initialization voltage AINT may have a level different from that of the first initialization voltage VINT. For example, the second initialization voltage AINT may have a level lower than that of the first initialization voltage VINT. However, if an optimal initialization voltage for removing a voltage remaining in the light emitting element ED may be provided, the embodiment of the inventive concept is not limited to any one.
As the eighth transistor T8 is turned on, the bias voltage Vbias may be provided to the first electrode of the first transistor T1. The bias voltage Vbias may have a predetermined level. The first transistor T1 may exhibit hysteresis properties in which a driving current caused by a signal applied in a current frame driving period is affected by a signal applied in a previous frame driving period. That is, when a driving frequency is varied, a luminance change due to the hysteresis properties of the first transistor T1 may be visually recognized by a user. However, as the eighth transistor T8 provides the bias voltage Vbias to the first electrode of the first transistor T1, the luminance change due to the hysteresis properties may be minimized, and the display quality of the display panel DP (see
The circuit unit PXC may include a first capacitor Cst, and may further include a second capacitor Cse. Each of the first capacitor Cst and the second capacitor Cse may include a first electrode and a second electrode overlapping each other in a plan view.
The first capacitor Cst may include a first electrode electrically connected to the first voltage line VL1 which transmits the first driving voltage ELVDD and a second electrode electrically connected to the first node N1. In the first capacitor Cst, charges corresponding to a voltage difference between the first electrode and the second electrode may be stored. When the fifth transistor T5 and the sixth transistor T6 are turned on, the amount of current flowing through the first transistor T1 may be determined in accordance with a voltage stored in the first capacitor Cst.
The second capacitor Cse may include a first electrode electrically connected to the first voltage line VL1 and a second electrode electrically connected to the first electrode of the first transistor T1. The second capacitor Cse may supplement the capacitance of the first capacitor Cst. The second capacitor Cse allows a data voltage corresponding to the data signal Di to be sufficiently transmitted to the first transistor T1.
Each of the pixels PX illustrated in
Referring to
The pixel units PXU may be arranged along the first direction DR1 and the second direction DR2 in a plan view. Among the pixel units PXU, pixel units PXU arranged in the first direction DR1 may be grouped and defined as a pixel row.
The third voltage line VL3 (or a first initialization voltage line) to which the first initialization voltage VINT is applied may include first initialization voltage line portions VL3-1 and second initialization voltage line portions VL3-2 electrically connected to each other. The second initialization voltage line portions VL3-2 and the first initialization voltage line portions VL3-1 may be disposed on different layers and electrically connected through contact holes. The first initialization voltage VINT may be applied to the first initialization voltage line portions VL3-1 and the second initialization voltage line portions VL3-2 which are electrically connected to each other.
Each of the first initialization voltage line portions VL3-1 may extend in the first direction DR1, and the first initialization voltage line portions VL3-1 may be arranged along the second direction DR2. The first initialization voltage line portions VL3-1 may each be electrically connected to the pixel rows R1, R2, and R3 arranged along the second direction DR2. Pixel units PXU arranged along the first direction DR1 in one pixel row may be electrically connected to the first initialization voltage line unit portion VL3-1 extending in the first direction DR1.
The second initialization voltage line portions VL3-2 may each extend in a direction intersecting the first initialization voltage line portions VL3-1. For example, the second initialization voltage line portions VL3-2 may each extend along the second direction DR2. The second initialization voltage line portions VL3-2 may be arranged along the first direction DR1. r number of pixel columns may be arranged between the second initialization voltage line portions VL3-2. Here, the r is a natural number of 1 or greater.
The first initialization voltage line VL3 may have a mesh shape including the first initialization voltage line portions VL3-1 and the second initialization voltage line portions VL3-2 electrically connected to each other while intersecting each other in a plan view. Accordingly, the first initialization voltage line VL3 may be electrically connected to the pixel units PXU arranged along the first direction DR1 and the second direction DR2 and apply the first initialization voltage VINT.
The second voltage line VL2 (or a second driving voltage line) to which the second driving voltage ELVSS is applied, the fourth voltage line VL4 (or a second initialization voltage line) to which the second initialization voltage AINT is applied, and the fifth voltage line VL5 to which the bias voltage Vbias is applied may each extend along the second direction DR2. The second initialization voltage line portion VL3-2, the second initialization voltage line VL4, the second driving voltage line VL2, and the fifth voltage line VL5 may be arranged along the first direction DR1.
The second initialization voltage line portion VL3-2, the second initialization voltage line VL4, the second driving voltage line VL2, and the fifth voltage line VL5 may each be provided in plurality and arranged according to a predetermined rule along the first direction DR1. For example, the second initialization voltage lines VL4 may be disposed in every two pixel columns and be electrically connected to the pixel units PXU, and the second driving voltage line VL2 and the fifth voltage line VL5 may be disposed in every six pixel columns and be electrically connected to the pixel units PXU. However, the rule in which the second initialization voltage line VL4, the second driving voltage line VL2, and the fifth voltage line VL5 are arranged is not limited to the illustrated embodiment, and may be changed according to the design of the display panel DP.
Referring to
The base substrate BS may provide a base surface on which the circuit element layer D-CL is disposed. The base substrate BS may include a glass substrate, a metal substrate, a polymer substrate, or an organic/inorganic composite material substrate. The base substrate BS may have a single-layered or multi-layered structure. For example, the base substrate BS of a multi-layered structure may include synthetic resin layers coupled through an adhesive.
The circuit element layer D-CL may be disposed on the base substrate BS. The circuit element layer D-CL may include a semiconductor pattern layer, conductive pattern layers, and insulation layers INS1 to INS6 constituting the circuit unit PXC (see
Through coating or deposition, an insulation layer, a semiconductor layer, and a conductive layer are formed on the base substrate BS, and then the insulation layer, the semiconductor layer, and the conductive layer may be patterned through photolithography to form a semiconductor pattern layer, conductive patterns, and insulation layers. However, the cross-sectional structure of the circuit element layer D-CL illustrated in
A first insulation layer INS1 may be disposed on the base substrate BS. The first insulation layer INS1 may be provided as a barrier layer and/or a buffer layer including at least one inorganic layer. For example, the first insulation layer INS1 may include at least one of an aluminum oxide, a titanium oxide, a silicon oxide, a silicon nitride, a silicon oxynitride, a zirconium oxide, or a hafnium oxide. The first insulation layer INS1 may improve coupling force between the base substrate BS and the semiconductor pattern layer or between the base substrate BS and the conductive pattern layers, and may protect the semiconductor pattern layer.
The second to sixth insulation layers INS2 to INS6 may be sequentially disposed on the first insulation layer INS1. Each of the second to sixth insulation layers INS2 to INS6 may include an inorganic layer or an organic layer.
The semiconductor pattern layer may be disposed on the first insulation layer INS1. The semiconductor pattern layer may include polysilicon, amorphous silicon, or a metal oxide. The semiconductor pattern layer may include semiconductor patterns of transistors.
The semiconductor pattern layer may include a plurality of regions having different electrical properties depending on whether or not the semiconductor pattern layer is doped. The semiconductor pattern layer may include a first region having a high conductivity and a second region having a low conductivity. The first region may be doped with an N-type dopant or a P-type dopant. A P-type transistor may include a doped region which is doped with the P-type dopant, and an N-type transistor may include a doped region which is doped with the N-type dopant. The second region may be a non-doped region. The conductivity of the first region may be greater than that of the second region, and the first region may substantially correspond to an electrode (or a source region and a drain region) or a signal line of a transistor. The second region may substantially correspond to an active region (or a channel region) of a transistor.
Referring to
The second insulation layer INS2 may be disposed on the first insulation layer INS1 and cover the semiconductor pattern layer. A sixth gate electrode G6 may be disposed on the second insulation layer INS2. The sixth gate electrode G6 may overlap the sixth active region A6 in a plan view. In an embodiment, the sixth gate electrode G6 may serve as a self-aligned mask in a process of doping the semiconductor pattern of the sixth transistor T6.
The third insulation layer INS3 may be disposed on the second insulation layer INS2 and cover the sixth gate electrode G6. The fourth insulation layer INS4 may be disposed on the third insulation layer INS3.
The circuit element layer D-CL may include connection electrodes CNE1 and CNE2 electrically connecting the sixth transistor T6 and the light emitting element ED. The connection electrodes CNE1 and CNE2 may include a first connection electrode CNE1 and a second connection electrode CNE2.
The first connection electrode CNE1 may be disposed on the fourth insulation layer INS4. The first connection electrode CNE1 may be electrically connected to the sixth transistor T6 through a contact hole CH1 formed through the second to fourth insulation layers INS2 to INS4. The fifth insulation layer INS5 may be disposed on the fourth insulation layer INS4 and cover the first connection electrode CNE1.
The second connection electrode CNE2 may be disposed on the fifth insulation layer INS5. The second connection electrode CNE2 may be electrically connected to the first connection electrode CNE1 through a contact hole CH2 formed through the fifth insulation layer INS5. However, the embodiment of the inventive concept is not limited thereto, and the number of the connection electrodes CNE1 and CNE2 electrically connected between the sixth transistor T6 and the light emitting element ED may be smaller or larger.
The sixth insulation layer INS6 may be disposed on the fifth insulation layer INS5 and cover the second connection electrode CNE2. In an embodiment, the sixth insulation layer INS6 may include at least one organic layer, and the sixth insulation layer INS6 may provide a flat upper surface while covering uneven upper surfaces of components disposed in a lower portion of the sixth insulation layer INS6.
The display element layer D-OL may be disposed on the circuit element layer D-CL. The display element layer D-OL may include the light emitting element ED, a pixel definition film PDL, and an encapsulation layer TFE. The light emitting element ED may include the anode AE, the cathode CE, a hole control layer HCL, an electron control layer ECL, and a light emitting layer EM-L.
The anode AE of the light emitting element ED may be disposed on the sixth insulation layer INS6. The anode AE may be connected to the second connection electrode CNE2 through a contact hole CH3 formed through the sixth insulation layer INS6. That is, the anode AE of the light emitting element ED may be electrically connected to the sixth drain region D6 of the sixth transistor T6 through the connection electrodes CNE1 and CNE2.
The pixel definition film PDL may be disposed on the anode AE. A light emitting opening PX-OP which exposes at least a portion of the anode AE may be defined in the pixel definition film PDL. In the present embodiment, the portion of the anode AE exposed by the light emitting opening PX-OP may correspond to a light emitting region.
The pixel definition film PDL may include a polymer resin, and may further include an inorganic matter included in the polymer resin. The pixel definition film PDL of an embodiment may have a predetermined color. For example, the pixel definition film PDL may include a base resin, and a black pigment and/or a black dye mixed with the base resin. However, the embodiment of the pixel definition film PDL is not limited thereto.
The hole control layer HCL may be disposed on the anode AE and the pixel definition film PDL. The hole control layer HCL may be commonly disposed in the pixels PX (see
The light emitting layer EM-L may be disposed on the hole control layer HCL. The light emitting layer EM-L may be disposed in a region corresponding to the light emitting opening PX-OP. The light emitting layer EM-L may include an organic material and/or an inorganic material. The light emitting layer EM-L may generate light having any one color among red, green, and blue colors.
The electron control layer ECL may be disposed on the light emitting layer EM-L and the hole control layer HCL. The electron control layer ECL may be commonly disposed in the pixels PX (see
The cathode CE may be disposed on the electron control layer ECL. The cathode CE may be commonly disposed in the pixels PX (see
The first driving voltage ELVDD (see
The encapsulation layer TFE may be disposed on the light emitting element ED and seal the light emitting element ED. The encapsulation layer TFE may include a plurality of thin films. For example, the encapsulation layer TFE may include inorganic films and an organic film disposed between the inorganic films. The thin films of the encapsulation layer TFE may be disposed to improve the optical efficiency of the light emitting element ED, or to protect the light emitting element ED. The inorganic film of the encapsulation layer TFE may protect the light emitting element ED from moisture and/or oxygen, and the organic film of the encapsulation layer TFE may protect the light emitting element ED from foreign substances such as dust particles.
Referring to
The first source region S1 and the first drain region D1 of the first transistor T1 may be spaced apart from each other with the first active region A1 interposed therebetween. The first drain region D1 of the first transistor T1 may be connected to the third source region S3 of the third transistor T3 and the sixth source region S6 of the sixth transistor T6. A point to which the first drain region D1, the third source region S3, and the sixth source region S6 are connected may correspond to the second node N2 (see
The second source region S2 and the second drain region D2 of the second transistor T2 may each extend from the second active region A2, and the second source region S2 and the second drain region D2 may be spaced apart from each other with the second active region A2 interposed therebetween. The fifth source region S5 and the fifth drain region D5 of the fifth transistor T5 may each extend from the fifth active region A5, and the fifth source region S5 and the fifth drain region D5 may be spaced apart from each other with the fifth active region A5 interposed therebetween.
The sixth source region S6 and the sixth drain region D6 of the sixth transistor T6 may each extend from the sixth active region A6, and the sixth source region S6 and the sixth drain region D6 may be spaced apart from each other with the sixth active region A6 interposed therebetween. The seventh source region S7 and the seventh drain region D7 of the seventh transistor T7 may each extend from the seventh active region A7, and the seventh source region S7 and the seventh drain region D7 may be spaced apart from each other with the seventh active region A7 interposed therebetween. The sixth drain region D6 of the sixth transistor T6 may be connected to the seventh drain region D7 of the seventh transistor T7.
The third transistor T3 may include a plurality of third active regions A3. The third active regions A3 of the third transistor T3 may extend from a common conductive region SD3, and be connected through the common conductive region SD3. The third source region S3 and the third drain region D3 of the third transistor T3 may be spaced apart from each other with the common conductive region SD3 and the third active regions A3 interposed therebetween. The third source region S3 of the third transistor T3 may extend from any one third active region A3 and be connected to the first drain region D1 of the first transistor T1. The third drain region D3 of the third transistor T3 may extend from another third active region A3 and be connected to the fourth drain region D4 of the fourth transistor T4. However, the embodiment of the inventive concept is not limited thereto, and the third transistor T3 may include a single third active region A3.
The fourth transistor T4 may include a plurality of fourth active regions A4. The fourth active regions A4 of the fourth transistor T4 may extend from a common conductive region SD4, and be connected through the common conductive region SD4. The fourth source region S4 and the fourth drain region D4 of the fourth transistor T4 may be spaced apart from each other with the common conductive region SD4 and the fourth active regions A4 interposed therebetween. The fourth source region S4 of the fourth transistor T4 may extend from any one fourth active region A4 and be connected to the first initialization voltage line portion VL3-1. The fourth drain region D4 of the fourth transistor T4 may extend from another fourth active region A4 and be connected to the third drain region D3 of the third transistor T3. However, the embodiment of the inventive concept is not limited thereto, and the fourth transistor T4 may include a single fourth active region A4.
The semiconductor pattern layer SMP may include a first initialization voltage line portion VL3-1 and a 5-1 voltage line portion VL5-1. Each of the first initialization voltage line portion VL3-1 and the 5-1 voltage line portion VL5-1 may extend in the first direction DR1. The first initialization voltage line portion VL3-1 and the 5-1 voltage line portion VL5-1 may be spaced apart from each other and arranged in the second direction DR2.
The first initialization voltage line portion VL3-1 may be connected to the semiconductor patterns of the fourth transistors T4 of the first to third pixel units PXC-1, PXC-2, and PXC-3 (see
The 5-1 voltage line portion VL5-1 may be connected to the semiconductor patterns of the eighth transistors T8 of the first to third pixel units PXC-1, PXC-2, and PXC-3 (see
The eighth source region S8 and the eighth drain region D8 of the eighth transistor T8 may extend from the eighth active region A8. The eighth source region S8 and the eighth drain region D8 may be spaced apart from each other with the eighth active region A8 interposed therebetween.
Referring to
The first gate electrode G1 is disposed on the semiconductor pattern of the first transistor T1, and may overlap the first active region A1 in a plan view. The second gate electrode G2 is disposed on the semiconductor pattern of the second transistor T2, and may overlap the second active region A2 in a plan view.
The third transistor T3 may include a double gate electrode. The third gate electrode G3 may overlap the third active regions A3 in a plan view. The third gate electrode G3 may be spaced apart from the common conductive region SD3 of the third transistor T3 in a plan view. However, the embodiment of the inventive concept is not limited thereto, and the third gate electrode G3 may overlap the common conductive region SD3 of the third transistor T3 in a plan view.
The fourth transistor T4 may include a double gate electrode. The fourth gate electrode G4 may overlap the fourth active regions A4 in a plan view. The fourth gate electrode G4 may be spaced apart from the common conductive region SD4 of the fourth transistor T4 in a plan view. However, the embodiment of the inventive concept is not limited thereto, and the fourth gate electrode G4 may overlap the common conductive region SD4 of the fourth transistor T4 in a plan view.
The emission control line EML may extend in the first direction DR1, and overlap the semiconductor patterns of the fifth transistor T5 and the semiconductor patterns of the sixth transistor T6 in a plan view. A portion of the emission control line EML overlapping the fifth active region A5 may be the fifth gate electrode G5 of the fifth transistor T5. Another portion of the emission control line EML overlapping the sixth active region A6 may be the sixth gate electrode G6 of the sixth transistor T6. That is, the fifth gate electrode G5 and the sixth gate electrode G6, and the emission control line EML may have a shape of a single body and be electrically connected to each other. An emission signal may be transmitted to the emission control line EML.
The 4-1 scan line portion GBL-1 may extend in the first direction DR1, and overlap the semiconductor patterns of the seventh transistor T7 and the semiconductor patterns of the eighth transistor T8 in a plan view. A portion of the 4-1 scan line portion GBL-1 overlapping the seventh active region A7 may be the seventh gate electrode G7 of the seventh transistor T7. Another portion of the 4-1 scan line portion GBL-1 overlapping the eighth active region A8 may be the eighth gate electrode G8 of the eighth transistor T8. That is, the seventh gate electrode G7 and the eighth gate electrode G8, and the 4-1 scan line portion GBL-1 may have a shape of a single body and be electrically connected to each other.
Referring to
The first conductive pattern portion G2-1 may overlap the first gate electrode G1 in a plan view. A portion of the first gate electrode G1 and the first conductive pattern portion G2-1 which overlap each other may form the first capacitor Cst. For example, the first electrode of the first capacitor Cst may correspond to the first conductive pattern portion G2-1 overlapping the first gate electrode G1, and the second electrode of the first capacitor Cst may correspond to the portion of the first gate electrode G1 overlapping the first conductive pattern portion G2-1. In the first conductive pattern portion G2-1, an opening G-OP may be defined. The opening G-OP of the first conductive pattern portion G2-1 may be disposed in an area overlapping the first gate electrode G1.
The second conductive pattern portion G2-2 may overlap the common conductive region SD3 of the third transistor T3 in a plan view. The third conductive pattern portion G2-3 may overlap the common conductive region SD4 of the fourth transistor T4 in a plan view. By overlapping the common conductive regions SD3 and SD4, the second conductive pattern portion G2-2 and the third conductive pattern portion G2-3 prevent the common conductive regions SD3 and SD4 from floating, and thus may prevent an instantaneous voltage rise.
Referring to
The first connection electrodes CNE1-1, CNE1-2, CNE1-3, CNE1-4, and CNE1-5 may be disposed spaced apart from each other on the same layer. The first connection electrodes CNE1-1, CNE1-2, CNE1-3, CNE1-4, and CNE1-5 may include a 1-1 connection electrode CNE1-1, a 1-2 connection electrode CNE1-2, a 1-3 connection electrode CNE1-3, a 1-4 connection electrode CNE1-4, and a 1-5 connection electrode CNE1-5.
The 1-1 connection electrode CNE1-1 may overlap the second transistor T2 in a plan view. The 1-1 connection electrode CNE1-1 may be electrically connected to the second source region S2 of the second transistor T2 through a contact hole.
The 1-2 connection electrode CNE1-2 may overlap the third drain region D3 of the third transistor T3 and the first gate electrode G1 of the first transistor T1 in a plan view, and may be electrically connected to each of the third drain region D3 and the first gate electrode G1 through contact holes. That is, the third drain region D3 and the first gate electrode G1 may be electrically connected to each other through the 1-2 connection electrode CNE1-2.
The 1-3 connection electrode CNE1-3 may overlap the fifth drain region D5 of the fifth transistor T5 and the eighth drain region D8 of the eighth transistor T8 in a plan view, and may be electrically connected to each of the fifth drain region D5 and the eighth drain region D8 through contact holes. That is, the fifth drain region D5 and the eighth drain region D8 may be electrically connected to each other through the 1-3 connection electrode CNE1-3.
The 1-4 connection electrode CNE1-4 may overlap the sixth transistor T6 in a plan view. The 1-4 connection electrode CNE1-4 may be electrically connected to the sixth drain region D6 of the sixth transistor T6 through a contact hole. The 1-4 connection electrode CNE1-4 may correspond to the first connection electrode CNE1 of
The 1-5 connection electrode CNE1-5 may overlap a protruding portion extending from the first initialization voltage line portion VL3-1 on the plane. The 1-5 connection electrode CNE1-5 may be electrically connected to the first initialization voltage line portion VL3-1 through a contact hole.
The upper electrode UE may overlap the second conductive pattern layer MP2 in a plan view. A portion of the upper electrode UE and a portion of the second conductive pattern layer MP2 which overlap each other may form the second capacitor Cse. For example, the first electrode of the second capacitor Cse may correspond to the portion of the upper electrode UE overlapping the second conductive pattern layer MP2, and the second electrode of the second capacitor Cse may correspond to the portion of the second conductive pattern layer MP2 overlapping the upper electrode UE.
The 4-2 scan line portion GBL-2 may extend in the first direction DR1. The 4-2 scan line portion GBL-2 overlaps the 4-1 scan line portion GBL-1 in a plan view, and may be electrically connected to the 4-1 scan line portion GBL-1 through a contact hole. The 4-1 scan line portion GBL-1 and the 4-2 scan line portion GBL-2 which are electrically connected to each other may constitute a fourth scan line GBL. The fourth scan line GBL may be electrically connected to the eighth gate electrode G8 of the eighth transistor T8.
The 5-2 voltage line portion VL5-2 may extend in the first direction DR1. The 5-2 voltage line portion VL5-2 overlaps the 5-1 voltage line portion VL5-1 in a plan view, and may be electrically connected to the 5-1 voltage line portion VL5-1 through a contact hole. The 5-1 voltage line portion VL5-1 and the 5-2 voltage line portion VL5-2 which are electrically connected to each other may constitute the fifth voltage line VL5. The 5-2 voltage line portion VL5-2 may include a material with better conductivity than the 5-1 voltage line portion VL5-1 does, and may improve the resistance of the fifth voltage line VL5. The fifth voltage line VL5 may be electrically connected to the eighth source region S8 of the eighth transistor T8 to transmit the bias voltage Vbias (see
Each of the first scan line GIL, the second scan line GWL, and the third scan line GCL may extend in the first direction DR1. The first scan line GIL, the second scan line GWL, and the third scan line GCL may be arranged in the second direction DR2. The first scan line GIL may be electrically connected to the fourth gate electrode G4 of the fourth transistor T4 through a contact hole. The second scan line GWL may be electrically connected to the second gate electrode G2 of the second transistor T2 through a contact hole. The third scan line GCL may be electrically connected to the third gate electrode G3 of the third transistor T3 through a contact hole.
The fourth voltage line VL4 may extend in the first direction DR1. The fourth voltage line VL4 may be electrically connected to the seventh source region S7 of the seventh transistor T7 through a contact hole, and transmit the second initialization voltage AINT (see
Referring to
Each of the data lines DL-1, DL-2, and DL-3 may extend in the second direction DR2. The data lines DL-1, DL-2, and DL-3 may be arranged along the first direction DR1. The data lines DL-1, DL-2, and DL-3 may be electrically connected to the second transistors T2 of the first to third pixel units PXC-1, PXC-2, and PXC-3 (see
Each of the first voltage lines VL1-1, VL1-2, and VL1-3 may extend in the second direction DR2. The first voltage lines VL1-1, VL1-2, and VL1-3 may be arranged along the first direction DR1. The first voltage lines VL1-1, VL1-2, and VL1-3 may be electrically connected to the first capacitors Cst and the second capacitors Cse of the first to third pixel units PXC-1, PXC-2, and PXC-3 (see
The second initialization voltage line portion VL3-2 may extend in the second direction DR2. The second initialization voltage line portion VL3-2 may be electrically connected to the first initialization voltage line portion VL3-1. For example, the second initialization voltage line portion VL3-2 may be electrically connected to the first initialization voltage line portion VL3-1 through the 1-5 connection electrodes CNE1-5. The second initialization voltage line portion VL3-2 and the first initialization voltage line portion VL3-1 may be disposed on different layers and include different materials. For example, the second initialization voltage line portion VL3-2 may include a material with greater conductivity than the first initialization voltage line portion VL3-1 does. The first initialization voltage line portion VL3-1 and the second initialization voltage line portion VL3-2 which are electrically connected to each other may constitute the first initialization voltage line VL3 (or a third voltage line). The first initialization voltage line VL3 may be electrically connected to the fourth source region S4 of the fourth transistor T4, and transmit the first initialization voltage VINT (see
The second connection electrode CNE2 may overlap the sixth transistor T6 in a plan view. The second connection electrode CNE2 may be electrically connected to the 1-4 connection electrode CNE1-4 through a contact hole. The second connection electrode CNE2 may be electrically connected to the sixth drain region D6 of the sixth transistor T6 through the 1-4 connection electrodes CNE1-4. The second connection electrode CNE2 may correspond to the second connection electrode CNE2 of
The shapes of the patterns constituting the pixel unit PXU illustrated in
Referring to
Referring to
The first initialization voltage line portions VL3-1 may extend in the first direction DR1, and arranged along the second direction DR2. The first initialization voltage line portions VL3-1 may be disposed in every pixel rows R1, R2, . . . . Each of the first initialization voltage line portions VL3-1 may be connected to pixels disposed in a corresponding pixel row. The second initialization voltage line portions VL3-2 may extend in the second direction DR2, and arranged along the first direction DR1. The second initialization voltage line portions VL3-2 may be disposed in every r number of pixel columns, and electrically connected to the first initialization voltage line portions VL3-1 to provide the initialization voltage to the pixel units PXU. For example,
Each of the pixel units PXU may include first to third light emitting regions PXA1, PXA2, and PXA3 corresponding to regions in which light emitting elements are disposed. The first to third light emitting regions PXA1, PXA2, and PXA3 may be distinguished from each other according to the color of light emitted therefrom. For example, the first light emitting region PXA1 may emit red light, the second light emitting region PXA2 may emit green light, and the third light emitting region PXA3 may emit blue light. However, the colors of emitted light are not limited to the above examples.
At least two or more light emitting regions among the first to third light emitting regions PXA1, PXA2, and PXA3 may have the same area with each other, or may have different areas with each other without being limited thereto. The areas of the first to third light emitting regions PXA1, PXA2, and PXA3 may be variously designed according to the luminous efficiency of the light emitting region, the resolution of the display panel DP, and the like.
In the pixel unit PXU, the first light emitting region PXA1 and the second light emitting region PXA2 may be arranged in the second direction DR2. In the pixel unit PXU, the third light emitting region PXA3 may be arranged in the first direction DR1 with the first light emitting region PXA1 and the second light emitting region PXA2. In the first direction DR1, each of the first light emitting region PXA1 and the second light emitting region PXA2 may overlap the third light emitting region PXA3. The third light emitting region PXA3 may include sub-third light emitting regions PXA3-1 and PXA3-2 which emit light of substantially the same color. The sub-third light emitting regions PXA3-1 and PXA3-2 may be spaced apart from each other in the first direction DR1.
The first light emitting regions PXA1 of the pixel units PXU arranged in one pixel row R1 or R2 may be arranged side by side along the first direction DR1. The second light emitting regions PXA2 of the pixel units PXU arranged in one pixel row R1 or R2 may be arranged side by side along the first direction DR1. The third light emitting regions PXA3 of the pixel units PXU arranged in one pixel row R1 or R2 may be arranged to be shifted from each other in the first direction DR1. For example, within one pixel row R1 or R2, the third light emitting regions PXA3 may be alternately disposed in upper portions and lower portions along the first direction DR1.
The first light emitting regions PXA1 and the second light emitting regions PXA2 of the pixel units PXU arranged in one pixel column C1, C2, C3, C4, C5, C6, C7, or C8 may be alternatively arranged along the second direction DR2. The third light emitting regions PXA3 of the pixel units PXU arranged in one pixel column C1, C2, C3, C4, C5, C6, C7, or C8 may be arranged while having a symmetrical shape in the second direction DR2.
However, the arrangement, shape, and area of the first to third light emitting regions PXA1, PXA2, and PXA3 illustrated in
Referring to
Hereinafter, with reference to the drawings, a method for repairing the display panel DP such that a defect is not generated in adjacent pixel units PXU when a defect is generated due to the short-circuit of the first capacitor Cst (see
Referring to
Referring to
On the path through which the first initialization voltage VINT (see
Referring to
By the first capacitor Cst that is short-circuited in the defective circuit unit, an increased initialization voltage may be applied through the first initialization voltage line portion VL3-1 to circuit units adjacent to the defective circuit unit in the first direction DR1. One cut portion CT1 may block the path of the first initialization voltage VINT (see
A portion v3 formed from the first initialization voltage line portion VL3-1 by the cut portions CT1 and CT 2 may be electrically insulated from the rest of the first initialization voltage line portion VL3-1. A defective circuit unit connected to the portion v3 may be isolated from other pixels, and the defective circuit may be blocked from expanding defects in the other pixels. In addition, even when the cut portions CT1 and CT2 are formed, the remaining pixels other than a defective pixel may be applied with the first initialization voltage VINT (see
Referring to
Referring to
By the first capacitor Cst that is short-circuited in the defective circuit unit, an increased initialization voltage may be applied through the first initialization voltage line portion VL3-1 to circuit units adjacent to a defective circuit unit in the first direction DR1. The cut portion CT3 may block the application of a first initialization voltage which has been increased due to the short-circuited first capacitor Cst to adjacent circuit units through the fourth transistor T4 and the first initialization voltage line portion VL3-1. That is, the cut portion CT3 may block the connection between the third transistor T3 electrically connected to the first capacitor Cst and the fourth transistor T4 electrically connected to the first initialization voltage line portion VL3-1, and by blocking a path through which the first initialization voltage VINT (see
The cut portion CT3 may electrically insulate the defective circuit unit from the first initialization voltage line portion VL3-1. The defective circuit unit may be isolated from other pixels by the cut portion CT3, and the defective circuit may be blocked from generating defects in the other pixels. In addition, even when the cut portion CT3 is formed, the remaining pixels other than a defective pixel may be applied with the first initialization voltage VINT (see
Pixels according to an embodiment of the inventive concept may be electrically connected to initialization voltage line portions which are connected in a mesh form. When foreign matters are introduced between opposing capacitor electrodes of a capacitor in a pixel or there is a defect in the insulator between the opposing capacitor electrodes, the capacitor may be short-circuited. As a result, pixels disposed in the same row with the damaged pixel, thereby being electrically connected through the same initialization voltage line portion may be applied with an increased initialization voltage and be visually recognized to the outside as a dark point.
A method for repairing a display panel according to an embodiment of the inventive concept blocks a path through which an initialization voltage is applied between a damaged pixel and adjacent pixels, and thus may prevent a rise in the voltage of the adjacent pixel, and prevent a defect from visually recognized as dark points. As a result, the degradation in display quality of a display panel may be prevented, and the yield of a display panel manufacturing process may be improved.
Although the present invention has been described with reference to preferred embodiments of the present invention, it will be understood by those skilled in the art that various modifications and changes in form and details may be made therein without departing from the spirit and scope of the present invention as set forth in the following claims.
Accordingly, the technical scope of the present invention is not intended to be limited to the contents set forth in the detailed description of the specification, but is intended to be defined by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0017606 | Feb 2023 | KR | national |
