Claims
- 1. A method of providing high-speed synchronization between hardware and software in a digital processing system, comprising: performing a sync instruction to cause the digital processing system to assume a stopped state; waiting for an interrupt to occur; receiving an interrupt; and vectoring to an interrupt address to service the interrupt or fetching an op code which is next in sequence when the interrupt received is masked.
- 2. A method of synchronizing hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising: stopping the central processing unit and waiting for an interrupt; and deciding whether to vector to an address for the interrupt or whether to fetch a next in sequence op code.
- 3. The method of claim 2 wherein the next in sequence op code is fetched when the interrupt received is masked.
- 4. A method of providing synchronization between hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising: placing the central processing unit in a stopped state; waiting for an interrupt to occur; receiving the interrupt; clearing the stopped state of the central processing unit; and servicing the interrupt or continuing with sequence of instructions if the interrupt is disabled.
- 5. A method of synchronizing hardware and software in a digital system having a central processing unit and at least one peripheral device, comprising:
- a. executing a sync instruction;
- b. waiting for an interrupt;
- c. receiving an interrupt and continuing with d, e, f, and g or continuing with the next instruction in a sequence of instructions thereby avoiding servicing the interrupt;
- d. getting data from an input port;
- e. storing the data and incrementing address;
- f. checking to determine whether all the data has been obtained from the input port; and
- g. repeating d, e, and f until all of the data has been obtained from the input port.
- 6. A method of synchronizing hardware and software in a digital system having a central processing unit, comprising: setting a latch in response to a synchronizing instruction which places the central processing unit in a stopped state; waiting for an interrupt to occur; resetting the latch in response to the interrupt; and continuing processing.
Parent Case Info
This is a continuation, of application Ser. No. 929,628, filed July 31, 1978 which is a continuation-in-part of application Ser. No. 872,857 filed on Jan. 27, 1978 and assigned to the same assignee as the present application.
US Referenced Citations (2)
Number |
Name |
Date |
Kind |
4003028 |
Bennett et al. |
Jan 1977 |
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4004283 |
Bennett et al. |
Jan 1977 |
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Continuations (1)
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Number |
Date |
Country |
Parent |
929628 |
Jul 1978 |
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Continuation in Parts (1)
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Number |
Date |
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Parent |
872857 |
Jan 1978 |
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