Claims
- 1. A method of testing a semiconductor integrated circuit comprising a main circuit, a self testing circuit for testing at least one part of functions of said main circuit, and a test result output circuit having at least one light emitting device for outputting test results from said self testing circuit in the form of light, said method comprising the steps of:
- inputting a test start signal to said self testing circuit so as to initiate operation of said self testing circuit;
- detecting light emitted from said light emitting device with an optical system, said light being emitted based on said test results from said self testing circuit; and
- obtaining said test results based on said light detection.
- 2. A method of testing a plurality of semiconductor integrated circuits formed on a substrate, each of said plurality of semiconductor integrated circuits comprising a main circuit, a self testing circuit for testing at least one part of functions of said main circuit, and a test result output circuit having at least one light emitting device for outputting test results from said self testing circuit in the form of light in a two-dimensional distribution, said method comprising the steps of:
- inputting a test start signal to said self testing circuit so as to initiate operation of said self testing circuit;
- detecting a two-dimensional distribution of light emitted from a plurality of said light emitting devices with an optical system, said light being emitted based on said test results from said self testing circuit; and
- obtaining a two-dimensional map of said test results by an image processing technique, based on said two-dimensional distribution of said light.
- 3. The method of claim 1, wherein said optical system includes a photomultiplier.
- 4. The method of claim 2, wherein said optical system includes a photomultiplier that produces electric signals representative of a two-dimensional image of said two-dimensional distribution of said light, and a two-dimensional map of said test results is obtained based on said electric signals.
Priority Claims (1)
Number |
Date |
Country |
Kind |
2-264003 |
Oct 1990 |
JPX |
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Parent Case Info
This application is a continuation of application Ser. No. 07/767,998, filed Sep. 30, 1991, now U.S. Pat. No. 5,248,936.
US Referenced Citations (6)
Foreign Referenced Citations (1)
Number |
Date |
Country |
2527859 |
Mar 1977 |
DEX |
Non-Patent Literature Citations (3)
Entry |
T. Takeshima et al., "A 55-ns 16 Mb DRAM with Built-in Self-Test Function Using Microprogram ROM", IEEE Journal of Solid-State Circuits, vol. 25, No. 4, pp. 903-909 (Aug. 1990). |
T. Takeshima et al., "A 55ns 16 Mb DRAM", from ISSCC Digest of Technical Papers, at pp. 246-247 (1989). |
"2.3 Built-In Test", from Built-In Test for VLSI, Wiley-Interscience, at pp. 38-43. |
Divisions (1)
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Number |
Date |
Country |
Parent |
767998 |
Sep 1991 |
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