Patent Application
20150093861
The present invention relates to integrated circuits and, in particular, to a process for the formation of complementary metal oxide semiconductor (CMOS) transistors.
Increased circuit density is a critical goal of integrated circuit design and fabrication. In order to achieve higher density, a downscaling of the transistors included within the circuit is effectuated. Such downscaling is typically achieved by shrinking the overall dimensions (and operating voltages) of the transistors. This shrinking cannot, however, be achieved at the expense of electrical performance. This is where the challenge arises: how to reduce transistor dimensions while maintaining the electrical properties of the device.
Conventional planar FET devices formed on bulk semiconductor substrates are quickly reaching their downscaling limit. Integrated circuit designers are accordingly turning towards new process technologies, new supporting substrates and new transistor configurations to support smaller and smaller transistor sizes without sacrificing transistor performance. One such new supporting substrate technology concerns the use of silicon on insulator (SOI) substrates to support the fabrication of transistor devices of smaller size. An SOI substrate is formed of a top semiconductor (for example, silicon or silicon-germanium) layer over an insulating (for example, silicon dioxide) layer over a bottom semiconductor (for example, silicon) substrate layer. Further substrate development has reduced the thickness of the intervening insulating layer to about 50 nm to produce a substrate for use in transistor fabrication that is referred to as an extremely thin silicon on insulator (ETSOI) substrate. Still further substrate development has reduced the thicknesses of all substrate layers to produce a substrate for use in transistor fabrication that is referred to an ultra-thin body and buried oxide (UTBB) substrate where the thickness of the intervening insulating layer is about 25 nm (or less) and the thickness of the top semiconductor layer is about 5 nm to 10 nm.
In a transistor fabricated using any one of the available types of SOI substrates, the channel region of the transistor is formed in the top semiconductor layer (that layer may, for example, be fully depleted for the purpose of controlling short channel effects). A gate stack is fabricated above the channel region and insulated from the channel by a gate oxide. The source and drain regions are provided on either side of the gate and channel, and are typically of the raised source/drain type separated from the conductive material of the gate stack by sidewall spacers. The threshold voltage of the fabricated transistor may be tuned through the application of a back bias to the bottom semiconductor substrate layer.
To isolate adjacent transistors from each other, it is known in the art to use shallow trench isolation (STI) techniques. With transistors formed on a UTBB substrate, for example, the STI structure is preferably a high aspect ratio structure (for example, having a ratio of about 1:10) which extends through both the ultra-thin top semiconductor layer and the thinner intervening insulating layer to reach into the bottom semiconductor substrate layer. In a preferred implementation, the bottom of the STI structure reaches a depth about 150 nm below the intervening insulating layer.
When forming an STI structure, a trench is defined adjacent the transistor active region. The trench typically extends through the top semiconductor layer and the intervening insulating layer and into the bottom semiconductor substrate layer. The trench may be lined and then filled with an insulating material such as silicon dioxide to a level above the top surface of the ultra-thin top semiconductor layer.
Different transistor active regions are typically provided on the wafer to support the fabrication of transistors of different conductivity type such as with CMOS integrated circuits. The transistor active regions are separated from each other by the STI structure. The gate structures and source/drain regions are then fabricated in the active region to define individual transistors.
It is common, however, for certain steps of the fabrication process to be separately applied to the regions of the wafer associated with fabrication of the p-type transistors and n-type transistors. For example, separately applied spacer layers are often used in different active regions. Additionally, certain processes, such as etches, may be separately applied to different active regions. The separated handling of fabrication process steps in different active regions can produce inconsistent structures for the p-type transistors and n-type transistors. For example, the thickness of a layer deposit may not be consistent in different active regions. Still further, the etching performed may affect a common layer differently in different active regions. As a result, the physical characteristics of certain transistor structures, such as spacer layers, channels, source/drain regions, etc., may undesirably be different between a p-type transistor and an n-type transistor formed in different active regions of a CMOS circuit on a common SOI substrate.
There is a need in the art for a fabrication process which addresses the foregoing concerns. More specifically, a need exists for an improved fabrication process designed to minimize differences in structure between fabricated p-type transistors and n-type transistors supported by an SOI substrate.
In an embodiment, a method comprises: forming shallow trench isolation structures on a silicon on insulator (SOI) substrate to define for a wafer a first active region for first conductivity type transistor fabrication separated from a second active region for second conductivity type transistor fabrication; forming a first gate stack over a top semiconductor layer of the SOI substrate in the first active region and a second gate stack over the top semiconductor layer of the SOI substrate in the second active region; conformally depositing a spacer layer on the wafer over the first and second active region; anisotropically etching the wafer to remove the spacer layer except from sidewalls of the first and second gate stacks so as to define sidewall spacers on said first and second gate stacks; forming an oxide layer on the wafer to cover the SOI substrate, shallow trench isolation structures, sidewall spacers and gate stacks; and forming a nitride layer on the wafer over the oxide layer.
In an embodiment, a method comprises: forming a first gate stack over a top semiconductor layer of a SOI substrate in a first active region; forming a second gate stack over the top semiconductor layer of the SOI substrate in a second active region; conformally depositing a spacer layer over the first and second active region; anisotropically etching to remove the spacer layer except from sidewalls of the first and second gate stacks so as to define sidewall spacers on said first and second gate stacks; forming an oxide layer to cover the SOI substrate, sidewall spacers and gate stacks; and forming a nitride layer over the oxide layer.
For a better understanding of the embodiments, reference will now be made by way of example only to the accompanying figures in which:
A lithographic process as known in the art is then used to form openings 64 in the silicon nitride layer 62 and pad oxide layer 60 (which together define a SiN/SiO2 hard mask as known in the art). The openings 64 extend down to reach at least the top surface of the top semiconductor layer 14 of the UTBB substrate. The result of the lithographic process is shown in
A high pressure directional etch process as known in the art is then performed through the openings 64 to form a trench 66 extending fully through the top semiconductor layer 14 and insulating layer 16 of the substrate 12. The trench 66 further penetrates into at least a portion of bottom semiconductor substrate layer 18. The etch may comprise an RIE process as known in the art. The result of the directional etch process is shown in
A process is then performed to fill each trench 66 with a shallow trench isolation structure 68. The shallow trench isolation structure 68 is illustrated in
A deglazing process as known in the art is then performed to recess to a desired depth the shallow trench isolation structure 68 by removing any liner and fill material as indicated at reference 70. The result of the deglazing process is shown in
A hot phosphoric acid etch process as known in the art is then used to remove the silicon nitride layer 62 all the way down to the underlying pad oxide layer 60 made of silicon dioxide (SiO2) material. The result of the hot phosphoric acid etch process is shown in
A hydrofluoric (HF) acid etch process as known in the art is then used to remove the pad oxide layer 60 made of silicon dioxide (SiO2) material all the way down to the underlying top semiconductor layer 14. The result of the hydrofluoric (HF) acid etch process is shown in
Reference is now made to
An anisotropic etch (for example, RIE) is then performed to remove the spacer layer 48. At least one exception with respect to this removal is that the etch will not remove the material of layer 48 from the side walls of the gate stack 40. The remaining portions of the spacer layer 48 accordingly form sidewall spacers 48′ for the transistor gate structures. The result of the etching process is shown in
With reference to
The mask material 54 is then removed. A consequence of the mask removal is the removal of the layer 50 in the region 20p. This will expose the top semiconductor layer 14. The layer 52 present in the region 20n over layer 50 prevents layer 50 from being removed.
Using an epitaxial process tool, an epitaxial growth process as known in the art is performed to grow a silicon-germanium (SiGe) layer 70 on the top semiconductor layer 14 in the area adjacent the gate stack 40. This silicon-germanium (SiGe) layer 70 may be doped as required for the transistor application (for example, including a boron dopant). The thickness of the silicon-germanium (SiGe) layer 70 is, for example, about 20 nm to 30 nm. In its position adjacent the gate stack 40, the epitaxially grown silicon-germanium (SiGe) layer 70 defines raised source-drain structures for the p-channel transistor in region 20p. It will be noted that the spacer 48′ serves to ensure that the raised source-drain is isolated from the conductive material of the gate stack 40. The epitaxy is followed by the deposit of a conformal silicon nitride (SiN) layer 72 over the wafer. Any suitable deposition technique (such as the atomic layer deposition process) may be used for this deposit. The layer 72 may have a thickness of about 3 nm to 4 nm. For reasons of clarity of process explanation, the layers 52 and 72 in the region 20n are shown as separate layers, but it will be understood that the layers 52 and 72 are of a same silicon nitride (SiN) material and thus a clear delineation between layers is 52 and 72 is not likely to exist. The result is shown in
With reference to
The mask material 74 is then removed. A consequence of the mask removal is the removal of the layer 50 in the region 20n. This will expose the top semiconductor layer 14. The layer 72 present in the region 20p over the raised source-drain structures 70 prevents damage from being inflicted on the structures 70.
Using an epitaxial process tool, an epitaxial growth process as known in the art is performed to grow a silicon-carbon (SiC) layer 80 on the top semiconductor layer 14 in the area adjacent the gate stack 40. This silicon-carbon (SiC) layer 80 may be doped as required for the transistor application (for example, including a phosphorous dopant). The thickness of the silicon-carbon (SiC) layer 80 is, for example, about 20 nm to 35 nm. In its position adjacent the gate stack 40, the epitaxially grown silicon-carbon (SiC) layer 80 defines raised source-drain structures for the n-channel transistor. It will be noted that the spacer 48′ serves to ensure that the raised source-drain is isolated from the conductive material of the gate stack 40. The epitaxy is optionally followed by the deposit of a conformal silicon nitride (SiN) layer 82 over the wafer. Any suitable deposition technique may be used for this deposit. The layer 82 may have a thickness of about 3-4 nm. For reasons of clarity of process explanation, the layers 82 and 72 in the region 20p are shown as separate layers, but it will be understood that the layers 82 and 72 are of a same silicon nitride (SiN) material and thus a clear delineation between layers is 82 and 72 is not likely to exist. The result is shown in
In summary, the process advantageously utilizes a common spacer material deposit along with an optimized universal etch on the regions for both n-channel transistors and p-channel transistors to define a common thickness of the sidewall spacers. A bi-layer silicon oxide and silicon nitride masking layer is used in each region type to permit stripping of the silicon nitride in a manner selective versus silicon oxide with a stop at the silicon nitride liner. The silicon oxide is removed prior to epitaxial growth of the raised source-drain structures (in the pre-epi clean) and this removal is very selective to silicon or silicon-germanium so that there is zero loss of the source drain material during fabrication.
The process described above presents a number of advantages including: a) as a result the sidewall spacer for the n-channel devices as a same thickness as the sidewall spacer for the p-channel devices; b) there is no loss with respect to the top semiconductor layer 14 in the source-drain regions because there is no damage inflicted by an RIE process, the fabrication technique instead relying on a HF or SiCoNi attack before epitaxial growth which does not attack SiN, Si or SiGe; c) scalability of the channel thickness is improved; d) there is better electrical connection with the channel; and e) there are no RIE residues and less risk of metal contamination in the source-drain regions.
The foregoing description has provided by way of exemplary and non-limiting examples a full and informative description of the exemplary embodiment of this invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the foregoing description, when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of this invention will still fall within the scope of this invention as defined in the appended claims.
