Claims
- 1. A method of manufacturing an integrated circuit, on a substrate, comprising the steps of:
- depositing a patterned metal layer on said substrate; and
- fabricating a dielectric cover over the patterned metal layer, comprising the steps of:
- depositing a first oxide layer over the substrate and the patterned metal layer, wherein the first oxide layer is deposited in such manner to create hills in the first oxide layer having metal thereunder and valleys in the first oxide layer having no metal thereunder;
- depositing a nitride layer, absent sufficient oxygen to cause liberation of oxygen during etchback, over the first oxide layer, wherein the nitride layer is deposited in such a manner to create hills in the nitride layer having metal thereunder and valleys in the nitride layer having no metal thereunder;
- depositing a spin on glass (SOG) layer on the nitride layer thereby predominantly filling the valleys in the nitride layer;
- etching back the SOG layer and the hills of the nitride layer to create a substantially planar surface; and
- depositing a second oxide layer on the substantially planar surface resulting in a substantially planar oxide layer.
- 2. The method of claim 1, wherein the metal layer is selected from the group consisting of Aluminum, Molybdenum, Tungsten, and Chromium; and
- said step of depositing a first oxide layer is performed by plasma enhanced chemical vapor deposition.
- 3. The method of claim 2, wherein said step of depositing a first oxide layer is carried out by forming the first oxide layer to a thickness in the approximate range of 1,000 .ANG. to 2,000 .ANG..
- 4. The method of claim 1, wherein said step of etching back the nitride layer and the SOG layer is performed using a gas selected from the group consisting of CHF.sub.3, CF.sub.4, C.sub.2 F.sub.6, SF.sub.6 and combinations thereof.
- 5. The method of claim 4, wherein said step of depositing a first oxide layer is carried out by forming the first oxide layer to a thickness in the approximate range of 1,000 .ANG. to 2,000 .ANG..
- 6. The method of claim 1, wherein said step of depositing a first oxide layer is carried out by forming the first oxide layer to a thickness in the approximate range of 1,000 .ANG. to 2,000 .ANG..
- 7. The method of claim 1, wherein said step of depositing a nitride layer is carried out by forming the nitride layer to a thickness in the approximate range of 5,000 .ANG. to 6,000 .ANG..
- 8. The method of claim 1, wherein said step of depositing a SOG layer is carried out by forming the SOG layer to a thickness in the approximate range of at least 2,000 .ANG. over flat regions of the nitride layer.
- 9. The method of claim 1, wherein said step of depositing a SOG layer is carried out by forming the SOG layer to a thickness in the approximate range of 2,500 .ANG. to 3,500 .ANG. over flat regions of the nitride layer.
- 10. The method of claim 1, wherein said step of depositing the first oxide layer is carried out in a reactant gas selected from the group consisting of nitrogen nitride and fluorinated nitride.
Parent Case Info
This application is a continuation in part of U.S. patent application Ser. No. 08/161,642, filed Dec. 1, 1993, now U.S. Pat. No. 5,399,533.
US Referenced Citations (1)
Number |
Name |
Date |
Kind |
5399533 |
Pramanik et al. |
Mar 1995 |
|
Non-Patent Literature Citations (1)
Entry |
Wolf et al., vol. II, Silicon Processing for the VLSI Era, Lattice Press, 1990; pp. 183-186, 361-362. |
Continuation in Parts (1)
|
Number |
Date |
Country |
Parent |
161642 |
Dec 1993 |
|