Smoothing of the dielectric

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HELECTRICITY H01Electric elements H01LSEMICONDUCTOR DEVICES ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof

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H01L21/76819Smoothing of the dielectric

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Methods of forming semiconductor device
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- Taiwan Semiconductor Manufacturing Company, Ltd
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Semiconductor device structures
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Method of forming semiconductor memory device
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Stacked FET contact formation
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Information Patent Grant
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Information Patent Grant
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Method for manufacturing a semiconductor device having a dummy section
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Information Patent Grant
Method for manufacturing semiconductor device
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Information Patent Grant
Integrated circuit structure and method for forming the same
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Information Patent Grant
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Fin field-effect transistor with a gate structure having a dielectr...
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Method of forming an interconnect structure having an air gap and s...
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- Szu-Ping Tung
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Information Patent Grant
Methods for forming recesses in source/drain regions and devices fo...
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- Taiwan Semiconductor Manufacturing Co., Ltd
- Yu-Lien Huang
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Information Patent Grant
Method of forming semiconductor memory device
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- Issue date Aug 6, 2024
- United Microelectronics Corp.
- Yi-Wei Chen
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Planar passivation layers
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Microelectronic assemblies
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Method of manufacturing semiconductor device and ion beam irradiati...
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Information Patent Grant
Trench etching process for photoresist line roughness improvement
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- Issue date Jun 25, 2024
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- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contact structure and method of forming the same
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- Issue date Jun 25, 2024
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- Wei Xu
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Information Patent Grant
Memory cell stack and via formation for a memory device
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- Micron Technology, Inc.
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Information Patent Grant
Polishing composition, polishing method, and method for producing s...
- Patent number 11,992,914
- Issue date May 28, 2024
- Fujimi Incorporated
- I-Chun Chang
- B24 - GRINDING POLISHING

Patents Applicationslast 30 patents

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- Publication number 20250149482
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HEAT DISSIPATION BY NANO PIPES
- Publication number 20250140644
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- NANYA TECHNOLOGY CORPORATION
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CHEMICAL PLANARIZATION OF NON-METALLIC MATERIALS
- Publication number 20250091176
- Publication date Mar 20, 2025
- CHEMPOWER CORPORATION
- Sudhanshu Misra
- B24 - GRINDING POLISHING
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SEMICONDUCTOR CHIP STRUCTURE
- Publication number 20250087531
- Publication date Mar 13, 2025
- Samsung Electronics Co., Ltd.
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METHOD OF FORMING AN INTERCONNECT STRUCTURE HAVING AN AIR GAP AND S...
- Publication number 20250070027
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- Taiwan Semiconductor Manufacturing Co., Ltd.
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MICROELECTRONIC ASSEMBLIES
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- ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC.
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WAFER-LEVEL DIE SINGULATION USING BURIED SACRIFICIAL STRUCTURE
- Publication number 20250048714
- Publication date Feb 6, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hung-Te Lin
- H01 - BASIC ELECTRIC ELEMENTS
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METHOD FOR PRODUCING AN INTERCONNECT VIA
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- Publication date Jan 23, 2025
- IMEC vzw
- Anshul Gupta
- H01 - BASIC ELECTRIC ELEMENTS
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Surface Profile Control Of Passivation Layers In Integrated Circuit...
- Publication number 20250014943
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- Taiwan Semiconductor Manufacturing Co., Ltd.
- Zheng Yong LIANG
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SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHO...
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- Adeia Semiconductor Solutions LLC
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INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20240395699
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- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yi-Wen PAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR MANUFACTURING AN INTERCONNECT STRUCTURE
- Publication number 20240387358
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- Taiwan Semiconductor Manufacturing company Ltd.
- KHADERBAD MRUNAL ABHIJITH
- H01 - BASIC ELECTRIC ELEMENTS
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SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE
- Publication number 20240387248
- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuan-Wei Huang
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INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF
- Publication number 20240379561
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- NANYA TECHNOLOGY CORPORATION
- JI-FENG LIU
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PLANAR PASSIVATION LAYERS
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- Publication date Oct 24, 2024
- Taiwan Semiconductor Manufacturing Co., LTD
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METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE INCLUDING NITROGEN...
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- NANYA TECHNOLOGY CORPORATION
- YING-CHENG CHUANG
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METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE INCLUDING NITROGEN...
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- NANYA TECHNOLOGY CORPORATION
- YING-CHENG CHUANG
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METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE
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- UNITED MICROELECTRONICS CORP.
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MULTI LEVEL CONTACT ETCH
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- TOKYO ELECTRON LIMITED
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TRENCH ETCHING PROCESS FOR PHOTORESIST LINE ROUGHNESS IMPROVEMENT
- Publication number 20240332020
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- Taiwan Semiconductor Manufacturing Company, Ltd.
- Sheng-Lin HSIEH
- H01 - BASIC ELECTRIC ELEMENTS
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METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE
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- Publication date Sep 26, 2024
- UNITED MICROELECTRONICS CORP.
- Yi-Wei Chen
- H01 - BASIC ELECTRIC ELEMENTS
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SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRC...
- Publication number 20240304543
- Publication date Sep 12, 2024
- Intel Corporation
- Kevin Lin
- H01 - BASIC ELECTRIC ELEMENTS
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INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARR...
- Publication number 20240290653
- Publication date Aug 29, 2024
- Taiwan Semiconductor Manufacturing Co., LTD
- Chin-Lung Chung
- H01 - BASIC ELECTRIC ELEMENTS
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METHODS OF FORMING SEMICONDUCTOR DEVICE
- Publication number 20240274527
- Publication date Aug 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Pei-Yu Chou
- H01 - BASIC ELECTRIC ELEMENTS

Smoothing of the dielectric

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods of forming semiconductor device

Semiconductor device structures

Method of forming semiconductor memory device

Integrated circuit devices including metal lines spaced apart from...

Stacked FET contact formation

Microelectronic assemblies

Reducing copper line resistance

Interconnect structure and method for manufacturing the interconnec...

Method for manufacturing a semiconductor device having a dummy section

Method for manufacturing semiconductor device

Semiconductor device including interconnect structure with planariz...

Integrated circuit structure and method for forming the same

In-situ PECVD cap layer

Semiconductor device and a manufacturing method thereof

Manufacturing method of semiconductor structure having elastic memb...

Fin field-effect transistor with a gate structure having a dielectr...

Semiconductor chip structure

Method of forming an interconnect structure having an air gap and s...

Methods for forming recesses in source/drain regions and devices fo...

Method of forming semiconductor memory device

Planar passivation layers

Microelectronic assemblies

Method of manufacturing semiconductor device and ion beam irradiati...

Subtractively patterned interconnect structures for integrated circ...

Semiconductor device structures

Semiconductor devices having a conductive pillar and methods of man...

Trench etching process for photoresist line roughness improvement

Contact structure and method of forming the same

Memory cell stack and via formation for a memory device

Polishing composition, polishing method, and method for producing s...

Patents Applicationslast 30 patents

MULTI-LEVEL SELECTIVE PATTERNING FOR STACKED DEVICE CREATION

SEMICONDUCTOR DEVICE STRUCTURE AND METHOD OF FABRICATING SAME

SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

HIGH VOLTAGE ISOLATION DEVICE

BEOL INTEGRATION SOLUTION BASED ON DIRECT CMP TO IMPROVE INTERMETAL...

SEMICONDUCTOR STRUCTURE WITH BONDING INTERFACE AND METHODS OF FORMI...

HEAT DISSIPATION BY NANO PIPES

SEMICONDUCTOR DEVICE HAVING CAPACITOR ARRAY AND METHOD OF FORMING T...

CHEMICAL PLANARIZATION OF NON-METALLIC MATERIALS

SEMICONDUCTOR CHIP STRUCTURE

METHOD OF FORMING AN INTERCONNECT STRUCTURE HAVING AN AIR GAP AND S...

MICROELECTRONIC ASSEMBLIES

WAFER-LEVEL DIE SINGULATION USING BURIED SACRIFICIAL STRUCTURE

METHOD FOR PRODUCING AN INTERCONNECT VIA

Surface Profile Control Of Passivation Layers In Integrated Circuit...

SEMICONDUCTOR DEVICE INCLUDING A POROUS DIELECTRIC LAYER, AND METHO...

INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME

METHODS FOR MANUFACTURING AN INTERCONNECT STRUCTURE

SEMICONDUCTOR DEVICES AND METHODS OF MANUFACTURE

INTERCONNECT STRUCTURE AND MANUFACTURING METHOD THEREOF

PLANAR PASSIVATION LAYERS

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE INCLUDING NITROGEN...

METHOD OF MANUFACTURING SEMICONDUCTOR STRUCTURE INCLUDING NITROGEN...

METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE

MULTI LEVEL CONTACT ETCH

TRENCH ETCHING PROCESS FOR PHOTORESIST LINE ROUGHNESS IMPROVEMENT

METHOD OF FORMING SEMICONDUCTOR MEMORY DEVICE

SUBTRACTIVELY PATTERNED INTERCONNECT STRUCTURES FOR INTEGRATED CIRC...

INTEGRATED CIRCUIT INTERCONNECT STRUCTURE HAVING DISCONTINUOUS BARR...

METHODS OF FORMING SEMICONDUCTOR DEVICE