Method, medium, and apparatus with interrupt handling in a reconfigurable array

Abstract

A method, medium, and apparatus to effectively handle an interrupt in a reconfigurable array. In the method, the reconfigurable array pauses execution of an operation when an interrupt request occurs, and after storing register values of a register to be used for handling the interrupt request, an interrupt service is performed by select processing units of the reconfigurable array in response to the interrupt request. Upon completion of the interrupt service, the register values are restored, and the reconfigurable array resumes execution of the operation.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

These and/or other aspects and advantages of the invention will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 illustrates a conventional reconfigurable architecture;

FIG. 2 illustrates a conventional coarse grained array;

FIG. 3 illustrates a difficulty with interrupt handling in a reconfigurable architecture;

FIG. 4 illustrates an apparatus having a coarse grained array, according to an embodiment of the present invention;

FIG. 5 illustrates an interrupt handling in a reconfigurable array, according to an embodiment of the present invention;

FIG. 6 illustrates a sequential process of an interrupt handling in a reconfigurable array, according to an embodiment of the present invention;

FIG. 7 illustrates an interrupt handling in a reconfigurable array, according to another embodiment of the present invention;

FIG. 8 is a flowchart illustrating a sequential process of an interrupt handling in a reconfigurable array according to still another exemplary embodiment of the present invention;

FIG. 9 illustrates a programmable interrupt controller, according to an embodiment of the present invention;

FIG. 10 illustrates an interrupt handling in a reconfigurable array, according to another embodiment of the present invention; and

FIG. 11 illustrates a sequential process of an interrupt handling in a reconfigurable array, according to another embodiment of the present invention; and

FIG. 12 illustrates an apparatus having a coarse grained array, according to another embodiment of the present invention.

Claims

1. A reconfigurable array control method, the method comprising: suspending an operation in a reconfigurable array when an interrupt request occurs during execution of the operation by the reconfigurable array;storing register values of at least one register for select processing units of the reconfigurable array to be used for handling the interrupt request;executing an interrupt service with the select processing units in response to the interrupt request; andresuming the operation in the reconfigurable array after restoring the register values to the at least one register.

2. The method of claim 1, wherein the suspending of the operation includes stopping a clock of the reconfigurable array, and wherein the resuming of the operation includes resuming the clock of the reconfigurable array.

3. The method of claim 1, wherein the storing of the register values includes pushing the register values into a predetermined stack, and wherein the restoring of the register values includes popping the register values from the stack.

4. A reconfigurable array control method, the method comprising: suspending an operation in a reconfigurable array when an interrupt request occurs during execution of the operation by the reconfigurable array;executing an interrupt service with select processing units in response to the interrupt request by using a dedicated register for the interrupt service; andresuming the operation in the reconfigurable array after completing the interrupt service in the select processing units.

5. The method of claim 4, wherein the suspending of the operation includes stopping a clock of the reconfigurable array, and wherein the resuming of the operation includes resuming the clock of the reconfigurable array.

6. A reconfigurable array control method, the method comprising: computing a programmed threshold time with regard to an operation to be executed in a reconfigurable array;comparing a current cycle time of the operation with the programmed threshold time when an interrupt request occurs during the execution of the operation by the reconfigurable array; anddiscarding the interrupt request when the current cycle time is greater than the programmed threshold time.

7. The method of claim 6, wherein the programmed threshold time is a time limit within which an interrupt service should start in response to the interrupt request.

8. The method of claim 6, wherein the programmed threshold time is a starting cycle time plus a worst case execution time minus a maximum interrupt latency for the operation, wherein the starting cycle time is a time taken to start the operation in the reconfigurable array, the worst case execution time is a time interval indicating when the operation is expected to terminate even in a worst case of the operation execution by the reconfigurable array, and the maximum interrupt latency is a maximum time allowable to postpone a start of the interrupt service, in response to the interrupt request, after receipt of the interrupt request.

9. The method of claim 6, further comprising: suspending an operation in the reconfigurable array when the current cycle time is less than the programmed threshold time;executing an interrupt service in the reconfigurable array in response to the interrupt request after storing register values of at least one register for select processing units of the reconfigurable array to be used for handling the interrupt request; andresuming the operation in the reconfigurable array after completing the interrupt service in the select processing units.

10. A reconfigurable array control method, the method comprising: comparing a worst case execution time of an operation executed by a reconfigurable array with a maximum interrupt latency of an interrupt request when the interrupt request occurs during the execution of a operation by the reconfigurable array; andexecuting an interrupt service, in response to the interrupt request, by select processing units of the reconfigurable array upon the operation ending in the reconfigurable array, when the worst case execution time is not greater than the maximum interrupt latency.

11. The method of claim 10, further comprising: comparing a current cycle time of the operation with a programmed threshold time; anddiscarding the interrupt request when the current cycle time is greater than the programmed threshold time.

12. The method of claim 11, wherein the programmed threshold time is a starting cycle time plus a worst case execution time minus a maximum interrupt latency for the operation, wherein the starting cycle time is a time to start the operation in the reconfigurable array, the worst case execution time is a time interval indicating when the operation is expected to terminate even in a worst case of the operation execution in the reconfigurable array, and the maximum interrupt latency is a maximum time allowable to postpone a start of the interrupt service, in response to the interrupt request, after receipt of the interrupt request.

13. The method of claim 11, further comprising: suspending an operation in the reconfigurable array when the current cycle time is less than the programmed threshold time;executing the interrupt service in the reconfigurable array in response to the interrupt request after storing register values of at least one register for select processing units of the reconfigurable array to be used for handling the interrupt request; andresuming the operation in the reconfigurable array after completing the interrupt service in the select processing units.

14. A reconfigurable array control method, the method comprising: executing an interrupt service in select processing units of a reconfigurable array in response to an interrupt request when the interrupt request occurs during an execution of an operation by the reconfigurable array in a reconfigurable array mode;storing a context for an instruction set processor mode before converting the instruction set processor mode into the reconfigurable array mode, with the instruction set processor mode including select processing units, of the reconfigurable array, used in the instruction set processor mode that are also used in the reconfigurable array mode; andrestoring the context for the instruction set processor mode after completion of the interrupt service by the select processing units.

15. The method of claim 14, further comprising executing the operation in the reconfigurable array, after the restoring of the context for the instruction set processor mode, from a beginning of the operation in the reconfigurable array.

16. The method of claim 14, wherein the interrupt service is executed by the select processing units in the instruction set processor mode.

17. At least one medium comprising a reconfigurable array unit and a controller unit, the controller unit to implement handling an interrupt according to the method of claim 1.

18. At least one medium comprising a reconfigurable array unit and a controller unit, the controller unit to implement handling an interrupt according to the method of claim 4.

19. At least one medium comprising a reconfigurable array unit and a controller unit, the controller unit to implement handling an interrupt according to the method of claim 6.

20. At least one medium comprising a reconfigurable array unit and a controller unit, the controller unit to implement handling an interrupt according to the method of claim 10.

21. At least one medium comprising a reconfigurable array unit and a controller unit, the controller unit to implement handling an interrupt according to the method of claim 14.

22. A computing apparatus, comprising: a reconfigurable array comprising a plurality of processing units; andan interrupt controller to store register values of at least one register for select processing units of the reconfigurable array to be used for handling an interrupt request, to execute an interrupt service by the select processing units in response to the interrupt request, and to restore the register values to the at least one register upon completion of the interrupt service by the select processing units,wherein the reconfigurable array selectively pauses execution of an operation being executed by the reconfigurable array upon receipt of the interrupt request, and selectively resumes executing the operation upon completion of the interrupt service.

23. The apparatus of claim 22, wherein the execution of the operation by the reconfigurable array pauses by stopping a clock of the reconfigurable array, and resumes execution of the operation by resuming the clock of the reconfigurable array.

24. The apparatus of claim 23, wherein the stopping of the clock includes stopping a clock input to the reconfigurable array and the resuming of the clock includes resuming a clock input to the reconfigurable array.

25. The apparatus of claim 22, wherein at least one of the select processing units does not have an include a matched reference file, while the plurality of processing units other than the select processing units include a respective reference file matched to each processing unit.

26. A computing apparatus, comprising: a reconfigurable array comprising a plurality of processing units; anda plurality of shadow registers each corresponding to one register selected among registers used in an instruction set processor mode,wherein the reconfigurable array selectively pauses execution of an operation being executed by the plurality of processing units of the reconfigurable array upon receipt of an interrupt request, executes an interrupt service using select processing units, of the plurality of processing units, in response to the interrupt by using the shadow registers, and resumes executing the operation upon completion of the interrupt service using the plurality of processing units.