Method of asynchronous memory access

INTRODUCTION
The present invention relates generally to a new and improved system for decoding a plurality of audio and video signals and, more particularly, to a new and improved system for decoding a plurality of MPEG audio and video signals.
A serial pipeline processing system of the present invention comprises a single two-wire bus used for carrying unique and specialized interactive interfacing tokens, in the form of control tokens and data tokens, to a plurality of adaptive decompression circuits and the like positioned as a reconfigurable pipeline processor.
PRIOR ART
U.S. Pat. No. 5,111,292 discloses an apparatus for encoding/decoding a HDTV signal for e.g. terrestrial transmission includes a priority selection processor for parsing compressed video codewords between high and low priority channels for transmission. A compression circuit responsive to high definition video source signals provides hierarchically layered codewords CW representing compressed video data and associated codewords T defining the types of data represented by codewords CW. The priority selection processor, responsive to the codewords CW and T, counts the number of bits in predetermined blocks of data and determines the number of bits in each block to be allocated to the respective channels. Thereafter the processor parses the codewords CW into high and low priority codeword sequences wherein the high and low priority codeword sequences correspond to compressed video data of relatively greater and lesser importance to image reproduction respectively.
One prior art system is described in U.S. Pat. No. 5,216,724. The apparatus comprises a plurality of compute modules, in a preferred embodiment, for a total of four compute modules coupled in parallel. Each of the compute modules has a processor, dual port memory, scratch-pad memory, and an arbitration mechanism. A first bus couples the compute modules and a host processor. The device comprises a shared memory which is coupled to the host processor and to the compute modules with a second bus.
U.S. Pat. No. 4,785,349 discloses a full motion color digital video signal that is compressed, formatted for transmission, recorded on compact disc media and decoded at conventional video frame rates. During compression, regions of a frame are individually analyzed to select optimum fill coding methods specific to each region. Region decoding time estimates are made to optimize compression thresholds. Region descriptive codes conveying the size and locations of the regions are grouped together in a first segment of a data stream. Region fill codes conveying pixel amplitude indications for the regions are grouped together according to fill code type and placed in other segments of the data stream. The data stream segments are individually variable length coded according to their respective statistical distributions and formatted to form data frames. The number of bytes per frame is withered by the addition of auxiliary data determined by a reverse frame sequence analysis to provide an average number selected to minimize pauses of the compact disc during playback, thereby avoiding unpredictable seek mode latency periods characteristic of compact discs. A decoder includes a variable length decoder responsive to statistical information in the code stream for separately variable length decoding individual segments of the data stream. Region location data is derived from region descriptive data and applied with region fill codes to a plurality of region specific decoders selected by detection of the fill code type (e.g., relative, absolute, dyad and DPCM) and decoded region pixels are stored in a bit map for subsequent display.
U.S. Pat. No. 4,922,341 discloses a method for scene-model-assisted reduction of image data for digital television signals, whereby a picture signal supplied at time is to be coded, whereby a predecessor frame from a scene already coded at time t-1 is present in an image store as a reference, and whereby the frame-to-frame information is composed of an amplification factor, a shift factor, and an adaptively acquired quad-tree division structure. Upon initialization of the system, a uniform, prescribed gray scale value or picture half-tone expressed as a defined luminance value is written into the image store of a coder at the transmitter and in the image store of a decoder at the receiver store, in the same way for all picture elements (pixels). Both the image store in the coder as well as the image store in the decoder are each operated with feed back to themselves in a manner such that the content of the image store in the coder and decoder can be read out in blocks of variable size, can be amplified with a factor greater than or less than 1 of the luminance and can be written back into the image store with shifted addresses, whereby the blocks of variable size are organized according to a known quad tree data structure.
U.S. Pat. No. 5,122,875 discloses an apparatus for encoding/decoding an HDTV signal. The apparatus includes a compression circuit responsive to high definition video source signals for providing hierarchically layered codewords CW representing compressed video data and associated codewords T, defining the types of data represented by the codewords CW. A priority selection circuit, responsive to the codewords CW and T, parses the codewords CW into high and low priority codeword sequences wherein the high and low priority codeword sequences correspond to compressed video data of relatively greater and lesser importance to image reproduction respectively. A transport processor, responsive to the high and low priority codeword sequences, forms high and low priority transport blocks of high and low priority codewords, respectively. Each transport block includes a header, codewords CW and error detection check bits. The respective transport blocks are applied to a forward error check circuit for applying additional error check data. Thereafter, the high and low priority data are applied to a modem wherein quadrature amplitude modulates respective carriers for transmission.
U.S. Pat. No. 5,146,325 discloses a video decompression system for decompressing compressed image data wherein odd and even fields of the video signal are independently compressed in sequences of intraframe and interframe compression modes and then interleaved for transmission. The odd and even fields are independently decompressed. During intervals when valid decompressed odd/even field data is not available, even/odd field data is substituted for the unavailable odd/even field data. Independently decompressing the even and odd fields of data and substituting the opposite field of data for unavailable data may be used to advantage to reduce image display latency during system start-up and channel changes.
U.S. Pat. No. 5,168,356 discloses a video signal encoding system that includes apparatus for segmenting encoded video data into transport blocks for signal transmission. The transport block format enhances signal recovery at the receiver by virtue of providing header data from which a receiver can determine re-entry points into the data stream on the occurrence of a loss or corruption of transmitted data. The re-entry points are maximized by providing secondary transport headers embedded within encoded video data in respective transport blocks.
U.S. Pat. No. 5,168,375 discloses a method for processing a field of image data samples to provide for one or more of the functions of decimation, interpolation, and sharpening. This is accomplished by an array transform processor such as that employed in a JPEG compression system. Blocks of data samples are transformed by the discrete even cosine transform (DECT) in both the decimation and interpolation processes, after which the number of frequency terms is altered. In the case of decimation, the number of frequency terms is reduced, this being followed by inverse transformation to produce a reduced-size matrix of sample points representing the original block of data. In the case of interpolation, additional frequency components of zero value are inserted into the array of frequency components after which inverse transformation produces an enlarged data sampling set without an increase in spectral bandwidth. In the case of sharpening, accomplished by a convolution or filtering operation involving multiplication of transforms of data and filter kernel in the frequency domain, there is provided an inverse transformation resulting in a set of blocks of processed data samples. The blocks are overlapped followed by a savings of designated samples, and a discarding of excess samples from regions of overlap. The spatial representation of the kernel is modified by reduction of the number of components, for a linear-phase filter, and zero-padded to equal the number of samples of a data block, this being followed by forming the discrete odd cosine transform (DOCT) of the padded kernel matrix.
U.S. Pat. No. 5,175,617 discloses a system and method for transmitting logmap video images through telephone line band-limited analog channels. The pixel organization in the logmap image is designed to match the sensor geometry of the human eye with a greater concentration of pixels at the center. The transmitter divides the frequency band into channels, and assigns one or two pixels to each channel, for example a 3 KHz voice quality telephone line is divided into 768 channels spaced about 3.9 Hz apart. Each channel consists of two carrier waves in quadrature, so each channel can carry two pixels. Some channels are reserved for special calibration signals enabling the receiver to detect both the phase and magnitude of the received signal. If the sensor and pixels are connected directly to a bank of oscillators and the receiver can continuously receive each channel, then the receiver need not be synchronized with the transmitter. An FFT algorithm implements a fast discrete approximation to the continuous case in which the receiver synchronizes to the first frame and then acquires subsequent frames every frame period. The frame period is relatively low compared with the sampling period so the receiver is unlikely to lose frame synchrony once the first frame is detected. An experimental video telephone transmitted 4 frames per second, applied quadrature coding to 1440 pixel logmap images and obtained an effective data transfer rate in excess of 40,000 bits per second.
U.S. Pat. No. 5,185,819 discloses a video compression system having odd and even fields of video signal that are independently compressed in sequences of intraframe and interframe compression modes. The odd and even fields of independently compressed data are interleaved for transmission such that the intraframe even field compressed data occurs midway between successive fields of intraframe odd field compressed data. The interleaved sequence provides receivers with twice the number of entry points into the signal for decoding without increasing the amount of data transmitted.
U.S. Pat. No. 5,212,742 discloses an apparatus and method for processing video data for compression/decompression in real-time. The apparatus comprises a plurality of compute modules, in a preferred embodiment, for a total of four compute modules coupled in parallel. Each of the compute modules has a processor, dual port memory, scratch-pad memory, and an arbitration mechanism. A first bus couples the compute modules and host processor. Lastly, the device comprises a shared memory which is coupled to the host processor and to the compute modules with a second bus. The method handles assigning portions of the image for each of the processors to operate upon.
U.S. Pat. No. 5,231,484 discloses a system and method for implementing an encoder suitable for use with the proposed ISO/IEC MPEG standards. Included are three cooperating components or subsystems that operate to variously adaptively pre-process the incoming digital motion video sequences, allocate bits to the pictures in a sequence, and adaptively quantize transform coefficients in different regions of a picture in a video sequence so as to provide optimal visual quality given the number of bits allocated to that picture.
U.S. Pat. No. 5,267,334 discloses a method of removing frame redundancy in a computer system for a sequence of moving images. The method comprises detecting a first scene change in the sequence of moving images and generating a first keyframe containing complete scene information for a first image. The first keyframe is known, in a preferred embodiment, as a "forward-facing" keyframe or intraframe, and it is normally present in CCITT compressed video data. The process then comprises generating at least one intermediate compressed frame, the at least one intermediate compressed frame containing difference information from the first image for at least one image following the first image in time in the sequence of moving images. This at least one frame being known as an interframe. Finally, detecting a second scene change in the sequence of moving images and generating a second keyframe containing complete scene information for an image displayed at the time just prior to the second scene change, known as a "backward-facing" keyframe. The first keyframe and the at least one intermediate compressed frame are linked for forward play, and the second keyframe and the intermediate compressed frames are linked in reverse for reverse play. The intraframe may also be used for generation of complete scene information when the images are played in the forward direction. When this sequence is played in reverse, the backward-facing keyframe is used for the generation of complete scene information.
U.S. Pat. No. 5,276,513 discloses a first circuit apparatus, comprising a given number of prior-art image-pyramid stages, together with a second circuit apparatus, comprising the same given number of novel motion-vector stages, perform cost-effective hierarchical motion analysis (HMA) in real-time, with minimum system processing delay and/or employing minimum system processing delay and/or employing minimum hardware structure. Specifically, the first and second circuit apparatus, in response to relatively high-resolution image data from an ongoing input series of successive given pixel-density image-data frames that occur at a relatively high frame rate (e.g., 30 frames per second), derives, after a certain processing-system delay, an ongoing output series of successive given pixel-density vector-data frames that occur at the same given frame rate. Each vector-data frame is indicative of image motion occurring between each pair of successive image frames.
U.S. Pat. No. 5,283,646 discloses a method and apparatus for enabling a real-time video encoding system to accurately deliver the desired number of bits per frame, while coding the image only once, updates the anqutization step size used to quantize coefficients which describe, for example, an image to be transmitted over a communications channel. The data is divided into sectors, each sector including a plurality of blocks. The blocks are encoded, for example, using DCT coding, to generate a sequence of coefficients for each block. The coefficients can be quantized, and depending upon the quantization step, the number of bits required to describe the data will vary significantly. At the end of the transmission of each sector of data, the accumulated actual number of bits expended is compared with the accumulated desired number of bits expended, for a selected number of sectors associated with the particular group of data. The system then readjusts the quantization step size to target a final desired number of data bits for a plurality of sectors, for example describing an image. Various methods are described for updating the quantization step size and determining desired bit allocations.
U.S. Pat. No. 5,287,420 discloses a method and apparatus for image compression suitable for personal computer applications, which compresses and stores data in two steps. An image is captured in realtime and compressed using an efficient method and stored to a hard-disk. At some later time, the data is further compressed in non-realtime using a computationally more intense algorithm that results in a higher compression ratio. The two-step approach allows the storage reduction benefits of a highly sophisticated compression algorithm to be achieved without requiring the computational resources to perform this algorithm in realtime. A compression algorithm suitable for performing the first compression step on a host processor in a personal computer is also described. The first compression step accepts 4:2:2 YCrCb data from the video digitizer. The two chrominance components are averaged and a pseudo-random number is added to all components. The resulting values are quantized and packed into a single 32-bit word representing a 2.times.2 array of pixels. The seed value for the pseudo-random number is remembered so that the pseudo-random noise can be removed before performing the second compression step
U.S. Pat. No. 5,289,577 discloses a method and apparatus for a sequential process-pipeline which has a first processing stage coupled to a CODEC through a plurality of buffers, including an image data input buffer, an image data output buffer and an address buffer. The address buffer stores addresses, each of which identifies an initial address of a block of addresses within an image memory. Each block of addresses in the image memory stores a block of decompressed image data. A local controller is responsive to the writing of an address into the address buffer to initiate the operation of the CODEC to execute a Discrete Cosine Transformation Process and a Discrete Cosine Transformation Quantization Process.
The article, Chong, Yong M., A Data-Flow Architecture for Digital Image Processing, Wescon Technical Papers: No. 2 Oct./Nov. 1984, discloses a real-time signal processing system specifically designed for image processing. More particularly, a token based data-flow architecture is disclosed wherein the tokens are of a fixed one word width having a fixed width address field. The system contains a plurality of identical flow processors connected in a ring fashion. The tokens contain a data field, a control field and a tag. The tag field of the token is further broken down into a processor address field and an identifier field. The processor address field is used to direct the tokens to the correct data-flow processor, and the identifier field is used to label the data such that the data-flow processor knows what to do with the data. In this way, the identifier field acts as an instruction for the data-flow processor. The system directs each token to a specific data-flow processor using a module number (MN). If the MN matches the MN of the particular stage, then the appropriate operations are performed upon the data. If unrecognized, the token is directed to an output data bus.
The article, Kimori, S. et al. An Elastic Pipeline Mechanism by Self-Timed Circuits, IEEE J. of Solid-State Circuits, Vol. 23, No. 1, February 1988, discloses an elastic pipeline having self-timed circuits. The asynchronous pipeline comprises a plurality of pipeline stages. Each of the pipeline stages consists of a group of input data latches followed by a combinatorial logic circuit that carries out logic operations specific to the pipeline stages. The data latches are simultaneously supplied with a triggering signal generated by a data-transfer control circuit associated with that stage. The data-transfer control circuits are interconnected to form a chain through which send and acknowledge signal lines control a hand-shake mode of data transfer between the successive pipeline stages. Furthermore, a decoder is generally provided in each stage to select operations to be done on the operands in the present stage. It is also possible to locate the decoder in the preceding stage in order to pre-decode complex decoding processing and to alleviate critical path problems in the logic circuit. The elastic nature of the pipeline eliminates any centralized control since all the interworkings between the submodules are determined by a completely localized decision and, in addition, each submodule can autonomously perform data buffering and self-timed data-transfer control at the same time. Finally, to increase the elasticity of the pipeline, empty stages are interleaved between the occupied stages in order to ensure reliable data transfer between the stages.
Accordingly, those skilled in the art have recognized a long felt need for a new and improved video decompression system obviating the deficiencies of the prior art systems. The present invention clearly fulfills this need.
SUMMARY OF INVENTION
The present invention embodies a method of asynchronously accessing a random access memory having a plurality of rows and columns, where each row has a wordline connected to read and write row decoders and each column is connected to bitlines. A row address is assigned to a first and second row, i.e. a pair of rows. A read address is provided to the read row decoder and a write address is provided to the write row decoder. The read and write addresses are decoded by the read and write row decoders, respectively, and one of the first or second rows is selected for reading. Asynchronous with selecting one of the first or second rows for reading, one of the first or second rows is selected for writing. Data is then read from the row selected for reading and asynchronously data is written into the row selected for writing. Signals are provided which coordinate the reading and writing of data, where in the event reading or writing is being performed, another of the reading or writing is deferred until completion of the first reading or writing. The read row decoder and the write decoder are unable to select the same row simultaneously and a read control circuit and a write control circuit are unable to select the same bit lines simultaneously.

BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates data flow through a preferred embodiment in the present invention;
FIG. 2 shows an example of a 13 bit word used to address 8 bit data in a 64.times.32 RAM;
FIG. 3 is a functional block diagram of a Register file in the present invention;
FIG. 4 illustrates data flow in a register file as shown in FIG. 3;
FIG. 5 is a block diagram illustrating register file address decoding, in accordance with the present invention;
FIG. 6 is a block diagram of a Microcodable State Machine, in accordance with the present invention;
FIG. 7 shows a fixed width word, in accordance with the present invention, used for addressing and having an address field, a substitution field and a substitution header;
FIG. 8 is a block diagram of one example of an Arithmetic Core in accordance with the present invention;
FIG. 9 illustrates the basis steps in a method, in accordance with the present invention, for performing an IDCT on input data;
FIG. 10 is a block diagram illustrating the combined, simplified, two-stage architecture of an IDCT system, in accordance with the present invention;
Figure 11 is a simplified block diagram of an integrated circuit that comprises the main system components of the IDCT shown in FIG. 10;
FIG. 12a and FIG. 12b taken together are a block diagram of a pre-processing circuit corresponding to one of the main system component; for ease of explanation, these figures are referred collectively as FIG. 12;
FIG. 13a, FIG. 13b and FIG. 13c depict timing diagrams which illustrate the relationships between timing and control signals in the IDCT system of a preferred embodiment;
FIG. 14a and FIG. 14b taken together are a block diagram of a common processing circuit in the IDCT system for ease of explanation, these figures are referred to collectively as FIG. 14;
FIG. 15a, FIG. 15b, FIG. 15c and FIG. 15d taken together are a block diagram of a post-processing circuit which corresponds to another main component of the system and are referred collectively as FIG. 15;
FIGS. 16a and 16b are a block diagram, in accordance with the present invention illustrating an IDCT having a twin data stream, a transpose RAM and an improved buffer and are collectively FIG. 16.
FIGS. 17a, 17b, 17c, 17d, 17e, 17f are a block diagram showing in further detail the 1-D IDCT system shown in FIGS. 16a and 16b and are collectively FIG. 17;
FIGS. 18a and 18b are a block diagram showing greater detail of the transform system as shown in FIGS. 17a-17f and are collectively FIG. 18;
FIGS. 19a and 19b are a block diagram showing in greater detail the input buffer shown in FIGS. 18a and 18b and are collectively FIG. 19;
FIGS. 20a and 20b are a simplified block diagram of a pre-processing circuit "PREC", in accordance with the present invention and are collectively FIG. 20;
FIGS. 21a and 21b are a block diagram illustrating a common processing circuit "CBLK" found in the IDCT and are collectively FIG. 21;
FIGS. 22a and 22b are a block diagram of a post-processing circuit "POSTC" and are collectively FIG. 22;
FIGS. 23a, 23b, 23c, 23d are another illustration of the post-processing circuit shown in FIGS. 22a and 22b and are collectively FIG. 23;
FIG. 24 is a block diagram depicting a round and saturate block, in accordance with the present invention;
FIGS. 25a and 25b are a block diagram of an output buffer in the present invention and are collectively FIG. 25;
FIGS. 26a and 26b (collectively FIG. 26) are a block diagram of a control shift register, in accordance with the present invention;
FIGS. 27a, 27b, 27c (collectively FIG. 27) are a block diagram of a control shift register decode in the present invention;
FIGS. 28a, 28b, 28c (collectively FIG. 28) are depict a control shift register and an input control buffer;
FIGS. 29a-1, 29a-2, 29b, 29c, 29d, 29e, 29f (collectively FIG. 29) illustrate a control circuit for a T2 data stream;
FIGS. 30a, 30b, 30c, 30d (collectively FIG. 30) show data in a counter for a T1 data stream;
FIGS. 31a, 31b, 31c, 31d, 31e (collectively FIG. 31) depict data in a counter for a T2 data stream in the present invention;
FIG. 32 is a timing diagram showing the initialization of the IDCT and associated circuitry
FIG. 33 is a timing diagram showing the interleaving of T1 and T2 data;
FIG. 34 is a timing diagram illustrating slippage and recovery of T2 data;
FIG. 35 is a timing diagram depicting a flushing operation of the IDCT and associated circuitry in the present invention;
FIG. 36 illustrates start-up of the system, in accordance with the present invention;
FIG. 37 depicts slippage and recovery in the early stages of interleaving T1 and T2 data;
FIG. 38 illustrates another preferred embodiment of the IDCT system shown in FIGS. 16a through 37;
FIG. 39 shows MPEG information streams being demultiplexed, in accordance with the present invention, into elementary streams containing data and timestamp information;
FIG. 40 depicts a first embodiment of an elementary stream timestamp error determination and time synchronization system, in accordance with the present invention;
FIG. 41 illustrates a second embodiment of an elementary stream timestamp error determination and time synchronization system, in accordance with the present invention;
FIG. 42 shows a third embodiment of an elementary stream timestamp error determination and time synchronization system, in accordance with the present invention;
FIG. 43 depicts a first embodiment of a video timestamp error determination and time synchronization system, in accordance with the present invention;
FIG. 44 illustrates a second embodiment of a video timestamp error determination and time synchronization system, in accordance with the present invention;
FIG. 45 shows the second embodiment of a video timestamp error determination and time synchronization system as shown in FIG. 44 and operating at 30 Hz;
FIG. 46 shows timestamp information flow through the system of the present invention;
FIG. 47 is a block diagram illustrating synchronization time information being processed by a microprogrammable state machine;
FIG. 48 is a block diagram illustrating a first preferred embodiment of the present invention;
FIG. 49 is another block diagram illustrating the first preferred embodiment of the present invention;
FIG. 50 depicts a second preferred embodiment of the present invention;
FIG. 51 illustrates a detailed method of addressing used by the second preferred embodiment, in accordance with the present invention;
FIG. 52 is a block diagram showing an apparatus for decoding Huffman VLCs, in accordance with the present invention;
FIGS. 53a, 53b, 53c, 53d are collectively FIG. 53 and are a schematic diagram showing the overall structure of the parallel huffman decoder of the present invention;
FIGS. 54a and 54b are collectively FIG. 54 and are a schematic diagram illustrating a ROM adapted for decoding parallel huffman codes;
FIG. 55 illustrates a first embodiment of a ROM adapted for decoding parallel huffman codes;
FIG. 56 illustrates a second embodiment of a ROM adapted for decoding parallel huffman codes;
FIG. 57 depicts a third embodiment of a ROM adapted for decoding parallel huffman codes;
FIG. 58 is a block diagram illustrating the primary system component of one embodiment of the present invention;
FIG. 59 is a block diagram depicting the start code detector of the present invention;
FIG. 60 is a block diagram showing the parser of the present invention;
FIG. 61 is a block diagram depicting the primary components of the spatial processing circuitry of the present invention;
FIG. 62 is a block diagram illustrating the display circuitry, in accordance with the present invention;
FIG. 63 illustrates one embodiment of timestamp management, in accordance with the present invention;
FIG. 64 shows another embodiment of timestamp management in the present invention;
FIG. 65 is a block diagram depicting the hardware components of the system of the present invention;
FIG. 66 is a block diagram providing an overview of the system components of the microcontroller of the present invention;
FIG. 67 is a simplified diagram illustrating the Arithmetic core of the present invention;
FIG. 68 illustrates the ALU of the present invention;
FIG. 69 depicts a register file, in accordance with the present invention;
FIG. 70 illustrates the writing to independent bus registers in the present invention;
FIG. 71 illustrates frame-based prediction wherein vector[1]=0 and vector[0]=0;
FIG. 72 depicts frame-based prediction wherein vector[1]=0 and vector[0]=1;
FIG. 73 shows frame-based prediction wherein vector[1]=1 and vector[0]=0;
FIG. 74 illustrates frame-based prediction wherein vector[1]=0 and vector[0]=1;
FIG. 75 depicts field-based prediction wherein motion.sub.-- vertical.sub.-- field.sub.-- select=0 and vector[0]=0;
FIG. 76 illustrates field-based prediction wherein motion.sub.-- vertical.sub.-- field.sub.-- select=0 and vector[0]=1;
FIG. 77 similarly illustrates field-based prediction wherein motion.sub.-- vertical.sub.-- field.sub.-- select=1 and vector[0]=0;
FIG. 78 shows field-based prediction wherein motion.sub.-- vertical.sub.-- field.sub.-- select=1 and vector[0]=1;
FIG. 79 shows field-based prediction in frame pictures wherein motion.sub.-- vertical.sub.-- field.sub.-- select=0 and vector[0]=0;
FIG. 80 illustrates the prediction of FIG. 79 wherein motion.sub.-- vertical.sub.-- field.sub.-- select=0 and vector[0]=1;
FIG. 81 shows the prediction mode of FIG. 79 wherein motion.sub.-- vertical.sub.-- field.sub.-- select=1 and vector[0]=0;
FIG. 82 shows the prediction mode of FIG. 79 wherein both motion.sub.-- vertical.sub.-- field.sub.-- select and vector[0]=1;
FIG. 83 illustrates an additional mode of prediction filtering;
FIG. 84 shows still another prediction mode;
FIG. 85 illustrates yet another prediction mode, in accordance with the present invention;
FIG. 86 shows another prediction mode of the present invention;
FIG. 87 is a block diagram illustrating the organization of the various system components of the display system of the present invention;
FIG. 88 depicts a 4:3 filtering operation;
FIG. 89 depicts a 3:2 filtering operation;
FIG. 90 illustrates a 2:1 filtering operation of the present invention;
FIG. 91 shows a three tap filter used in the present invention;
FIG. 92 illustrates the repetition of erroneous pels;
FIG. 93 depicts the filed.sub.-- id signal of the present invention;
FIG. 94 shows the horizontal timing points (cycles), in accordance with the present invention;
FIG. 95 illustrates the PAL vertical timing at 625 lines per field, in accordance with the present invention;
FIG. 96 illustrates the NTSCV vertical timing at 525 lines per field, in accordance with the present invention;
FIG. 97 shows a horizontal counting machine, in accordance with the present invention;
FIG. 98 illustrates border generation in the present invention;
FIG. 99 depicts picture cropping, in accordance with the present invention;
FIG. 100 is a block diagram illustrating the present invention as a chip;
FIG. 101 illustrates the sysclock requirements of the present invention;
FIG. 102 depicts the two-wire protocol on a coded data interface, in accordance with the present invention;
FIG. 103 shows a DATA token of the present invention;
FIG. 104 shows a FLUSH token of the present invention;
FIG. 105 illustrates the timing of the coded data interface;
FIG. 106 depicts using non-even mark-space ratio CDCLOCK, in accordance with the present invention;
FIG. 107 shows output timing in 16 bit mode in the present invention;
FIG. 108 illustrates output timing in 8 bit mode in the present invention;
FIG. 109 shows the timing of the video output interface in the present invention;
FIG. 110 depicts video output mode signals, in accordance with the present invention;
FIG. 111 shows horizontal timing in the present invention;
FIGS. 112a and 112b (collectively FIG. 112) show the vertical timing for a 525 line system;
FIGS. 113a and 113b (collectively FIG. 113) depict the vertical timing for a 625 line system;
FIG. 114 illustrates the sync and blanking signals for a 525 line system, in accordance with the present invention;
FIG. 115 shows the sync and blanking signals for a 625 line system, in accordance with the present invention;
FIG. 116 illustrates a zero SDRAM connection configuration in the present invention;
FIG. 117 shows one SDRAM connection configuration in the present invention;
FIG. 118 depicts a two SDRAM connection configuration, in accordance with the present invention;
FIG. 119 illustrates a three SDRAM connection configuration
FIG. 120 is a flow chart depicting the flag.sub.-- picture.sub.-- end operation, in accordance with the present invention;
FIG. 121 is a flow chart showing the start.sub.-- code.sub.-- search operation, in accordance with the present invention;
FIG. 122 shows timestamp modification, in accordance with the present invention
FIG. 123 illustrates the read timing for the microprocessor interface; and
FIG. 124 shows the write timing for the microprocessor interface.

In the ensuing description of the practice of the invention, the following terms are frequently used and are generally defined by the following glossary:
GLOSSARY
BLOCK: An 8-row by column matrix of pels, or 64 DCT coefficients (source, quantized or dequantized).
CHROMINANCE (COMPONENT): A matrix, block or single pel representing one of the two color difference signals related to the primary colors in the manner defined in the bit stream. The symbols used for the color difference signals are Cr and Cb.
CODED REPRESENTATION: A data element as represented in its encoded form.
CODED VIDEO BIT STREAM: A coded representation of a series of one or more pictures as defined in this specification.
CODED ORDER: The order in which the pictures are transmitted and decoded. This order is not necessarily the same as the display order.
COMPONENT: A matrix, block or single pel from one of the three matrices (luminance and two chrominance) that make up a picture.
COMPRESSION: Reduction in the number of bits used to represent an item of data.
DECODER: An embodiment of a decoding process.
DECODING (PROCESS): The process defined in this specification that reads an input coded bitstream and produces decoded pictures or audio samples.
DISPLAY ORDER: The order in which the decoded pictures are displayed. Typically, this is the same order in which they were presented at the input of the encoder.
ENCODING (PROCESS): A process, not specified in this specification, that reads a stream of input pictures or audio samples and produces a valid coded bitstream as defined in this specification.
INTRA CODING: Coding of a macroblock or picture that uses information only from that macroblock or picture.
LUMINANCE (COMPONENT): A matrix, block or single pel representing a monochrome representation of the signal and related to the primary colors in the manner defined in the bit stream. The symbol used for luminance is Y.
MACROBLOCK: The four 8 by 8 blocks of luminance data and the two (for 4:2:0 chroma format) four (for 4:2:2 chroma format) or eight (for 4:4:4 chroma format) corresponding 8 by 8 blocks of chrominance data coming from a 16 by 16 section of the luminance component of the picture. Macroblock is sometimes used to refer to the pel data and sometimes to the coded representation of the pet values and other data elements defined in the macroblock header of the syntax defined in this part of this specification. To one of ordinary skill in the art, the usage is clear from the context.
MOTION COMPENSATION: The use of motion vectors to improve the efficiency of the prediction of pet values. The prediction uses motion vectors to provide offsets into the past and/or future reference pictures containing previously decoded pel values that are used to form the prediction error signal.
MOTION VECTOR: A two-dimensional vector used for motion compensation that provides an offset from the coordinate position in the current picture to the coordinates in a reference picture.
NON-INTRA CODING: Coding of a macroblock or picture that uses information both from itself and from macroblocks and pictures occurring at other times.
PEL: Picture element.
PICTURE: Source, coded or reconstructed image data. A source or reconstructed picture consists of three rectangular matrices of 8-bit numbers representing the luminance and two chrominance signals. For progressive video, a picture is identical to a frame, while for interlaced video, a picture can refer to a frame, or the top field or the bottom field of the frame depending on the context.
PREDICTION: The use of a predictor to provide an estimate of the pel value or data element currently being decoded.
RECONFIGURABLE PROCESS STAGE (RPS): A stage, which in response to a recognized token, reconfigures itself to perform various operations.
SLICE: A series of macroblocks.
TOKEN: A universal adaptation unit in the form of an interactive interfacing messenger package for control and/or data functions.
START CODES [SYSTEM AND VIDEO]: 32-bit codes embedded in a coded bitstream that are unique. They are used for several purposes including identifying some of the structures in the coding syntax.
VARIABLE LENGTH CODING; VLC: A reversible procedure for coding that assigns shorter code-words to frequent events and longer code-words to less frequent events.
VIDEO SEQUENCE: A series of one or more pictures.
DETAILED DESCRIPTIONS
The forthcoming "Detailed Description of the Invention" contains the following Sections:
1) Detailed Description of the Invention for Memory Addressing
Variable Length Fields Within a Fixed Width Word
Using Fixed Width Word with Variable Length Fields to Perform Address Substitution
Addressing Variable Width Data with a Fixed Width Word
Microcodable State Machine Structure
Arithmetic Core
2) Detailed Description of the Invention for Transforming Data using a Common Processing Block
Theoretical Background of the Invention
3) Detailed Description of Invention for Time Synchronization
4) Detailed Description of the Invention for Asynchronous Swing Buffering
5) Detailed Description of the Invention for Storing Video Information
6) Detailed Description of the Invention for a Parallel Huffman Decoder
The Huffman Code ROM
Maximizing Throughput
FLCs and Tokens
Implementation
7) MORE DETAILED DESCRIPTION
DETAILED DESCRIPTION OF THE INVENTION
As an introduction to the illustrative embodiment(s) of the most general features of the invention, and referring more particularly to FIG. 1 of the drawings, the data flow through the preferred embodiment 200 of the invention is shown. The embodiment of the present invention is preferably implemented using a two-wire pipeline system having various control and DATA tokens. The major elements of the system are a Start Code Detector 201, a Video Parser 202 incorporating a Huffman Decoder 203 and a Microprogrammable State Machine (MSM) 204, an Inverse Discrete Cosine Transform (IDCT) 205, a synchronous DRAM controller 206 with an associated address generation unit 207, appropriate prediction circuitry 208 and display circuitry 209 which includes upsampling 210 and 211 and video timing generation 212.
This application relates to similar subject matter disclosed in British Patent Application number 9405914.4 entitled "Video Decompression" filed on Mar. 24, 1994, by Discovision Associates, and the latter application is specifically incorporated by reference in this application.
In accordance with the above, specific aspects, features and subsystem areas of the present invention will be referred to in greater detail below. In the drawings, like reference numerals denote like or corresponding parts throughout the various drawings and figures.
Detailed Description of the Invention for Memory Addressing
In accordance with the present invention, a method and apparatus for addressing memory is described herein. In particular, the present invention provides for deferring variable width bit fields with fixed width words. More particularly, the present invention provides a method of addressing variable width data with a fixed width word. In various forms of the embodiment, variable bit field is used to specify bits to be substituted into the word or to specify an unused portion of the word in addressing variable width data with a fixed width word. In addition, the system of the present invention includes a microcodable state machine having an arithmetic core.
The microcodable state machine is intended to be used for solving design problems where there is a need for versatile and/or complicated calculations. Examples of such designs include address generation, stream parsing and decoding, and filter tap coefficient calculations. In this regard, the addressing must cope with two different features: (1) variable length addresses to access varying width portions of words and (2) address substitution. In the present invention, a RAM having a 64.times.32 bit configuration can be addressed in partial words having 64.times.32 bit, 128.times.16 bit, 256.times.8 bit, 512.times.4 bit, 1024.times.2 bit, or 2048.times.1 bit formats.
Variable Length Fields Within a Fixed Width Word
In many applications, it is useful to define variable portions of a word (to be known as fields) for actions such as substitution, variable width data addressing, or the constriction of other parts of the word. The conventional method for defining variable portions of words is to have an additional word (or words) which specify the width of the field (or fields) within the word. In accordance with the present invention, a method for encoding this information within the word itself is described. The present method has the advantages of savings bits in the overall definition of the word, simplifying decoding of the encoded word and providing a more intuitive view of what has been encoded. Furthermore, this encoding method is applicable if the variable width fields are most or least significant bit justified within the word.
Accordingly, Table 1 shows two examples of variable width fields (marked "F") that are least significant bit justified defined within an eight bit word. A "w" marks other potential fields of these words.
TABLE 1______________________________________Bit number (hex) 7 6 5 4 3 2 1 0______________________________________Fixed word w w w F F F F F w w w w w w F F______________________________________
Table 2 shows the conventional method of encoding the fields shown in Table 1 using sufficient additional bits to specify the maximum width of the field in binary. (Bits marked "x" "don't care", i.e., their value is of no consequence. This method is clearly inefficient in its use of bits and, furthermore, provides a less intuitive form than that described in the present invention.
TABLE 2______________________________________Bit number (hex) 7 6 5 4 3 2 1 0 Field Define______________________________________Fixed word w w w x x x x x 1 0 1 w w w w w w x x 0 1 0______________________________________
The new method, in accordance with the present invention, defines the field within the word. This method defines the field by using a continuation marker and a termination marker. The field is specified, from one end of the field, as a series of continuation markers followed by a termination marker. In the case of a zero length field, however, only a termination marker is provided at the end of the word. Both the continuation marker and the termination marker are single bits, and they must be complementary. In addition, the field must be justified to either end of the word. Accordingly, the method of the present invention for encoding fields requires a width of only one bit extra over the original word width.
As shown in Table 3, the encoding of the fields shown in the Table 1, in accordance with the new method, is depicted. In this example, the continuation marker is "1" and the termination marker is "0". The field in this example is least significant bit justified.
TABLE 3______________________________________Bit number (hex) 7 6 5 4 3 2 1 0______________________________________Fixed word w w w 0 1 1 1 1 1 Continuation marker = 1; w w w w w w 0 1 1 Termination marker = 0.______________________________________
Therefore, the advantages of the encoding method, in accordance with the present invention, are:
1. A reduction in the number of bits needed in the encoding.
2. A simplification in the decoding process is required since the need for a "x to 1 of "decode of the "field define" shown in Table 1-2 that would normally be required is inherent in the encoding which is already in the form of 1 of 2.sup.x ; and
3. The encoding is in a more intuitive form allowing the field defined to be more easily identified.
Furthermore, the use of this encoding method of the present invention can also be used such that the termination marker and the continuation marker are inverted to provide that the encoding of Table 3 resembles that of Table 4. Hence, the use of "1" or "0" is used interchangeably throughout this application.
TABLE 4______________________________________Bit number (hex) 7 6 5 4 3 2 1 0______________________________________Fixed word w w w 1 0 0 0 0 0 Continuation marker = 1: w w w w w w 1 0 0 Termination marker = 0.______________________________________
As previously identified, the field encoded must be justified to either end of the word. Table 5 illustrates most significant justified fields, i.e., these are encoded in a similar way to least significant bit justified fields except that the field reaches from the most significant bit (hereinafter MSB) towards the least significant bit (hereinafter "LSB") up to and including the first termination marker. The encoding of the fields shown in Table 5 are shown in Table 6.
TABLE 5______________________________________Bit number (hex) 7 6 5 4 3 2 1 0______________________________________Fixed word F F F F F w w w F F w w w w w w______________________________________
TABLE 6______________________________________Bit number (hex) 7 6 5 4 3 2 1 0______________________________________Fixed word 1 1 1 1 1 0 w w w Continuation marker = 1; 1 1 0 w w w w w w Termination marker = 0.______________________________________
Moreover, fields may be encoded from the least significant and most significant ends of the word simultaneously. For example, the two fields shown in Table 7 may be encoded as in Table 8, with the addition of just one bit for each field as described previously.
TABLE 7______________________________________Bit number (hex) 7 6 5 4 3 2 1 0______________________________________Fixed word F F F F w w F F w w w w F F F F______________________________________
TABLE 8______________________________________Bit number (hex) 7 6 5 4 3 2 1 0______________________________________Fixed word 1 1 1 1 0 w w 0 1 1 Continuation marker = 1; 0 w w w w 0 1 1 1 1 Termination marker = 0.______________________________________
Using a Fixed Width Word with Variable Length Fields to Perform Address Substitution
There are situations in which it is useful to substitute part of a memory address by another value. In this way it is possible to construct a data dependent address. The encoding method of the present invention can be applied to the addresses of a memory to specify what portion of the address is to be substituted. If a least significant bit justified variable length field is used in the address, a substitution field can be defined. For example, a 12 bit address 0baaaaaaaaaaaa encoded to have its five least significant bit substituted by the 12 bit value 0bcccccccccccc would be 0baaaaaaa011111 and produce the address 0baaaaaaaaccccc. Table 9 shows the encoding for substitution into a 12 bit address.
TABLE 9______________________________________Address substitution No. Bits substituted B A 9 8 7 6 5 4 3 2 1 0______________________________________0 a a a a a a a a a a a a 1 1 a a a a a a a a a a a 0 1 2 a a a a a a a a a a b 1 1 3 a a a a a a a a a 0 1 1 1 4 a a a a a a a a 0 1 1 1 1 5 a a a a a a a 0 1 1 1 1 1 6 a a a a a a 0 1 1 1 1 1 1 7 a a a a a 0 1 1 1 1 1 1 1 8 a a a a 0 1 1 1 1 1 1 1 1 9 a a a 0 1 1 1 1 1 1 1 1 1 10 a a 0 1 1 1 1 1 1 1 1 1 1 11 a 0 1 1 1 1 1 1 1 1 1 1 1 12 0 1 1 1 1 1 1 1 1 1 1 1 1______________________________________
Addressing Variable Width Data with a Fixed Width Word
One embodiment of the present invention is for addressing a memory which can be accessed at its full width or in 2.sup.n widths up to its full width (these smaller words are called partial words). Hence, it will be shown how the variable field encoding of the present invention can be used to address this memory and to index those addresses into the memory.
To access a 64.times.32 bit Register file in widths of 32, 16, 8, 4, 2 and 1 bit requires different lengths of address, i.e., the implementation of this embodiment is a 64.times.32 bit memory which can be accessed as 64.times.32 bits, 128.times.16 bits, 256.times.8 bits, 512.times.4 bits, 1024.times.2 bits, or 2048.times.1 bit. It is seen that 5 bits are required to address one of the 64.times.32 bit locations, while 12 bits are required to address one of the 2048.times.1 bit locations. Hence, the addresses can be of variable length and, in fact, the width of the address specifies the address format of the memory. Accordingly, the address can be defined within a fixed word width by using a most significant justified variable width field which constricts the address and defines its width. This is illustrated in Table 10.
TABLE 10______________________________________Variable width addressing Data Width A 9 8 7 6 5 4 3 2 1 0______________________________________1 1 a a a a a a a a a a a 2 0 1 a a a a a a a a a a 4 0 0 1 a a a a a a a a a 8 0 0 0 1 a a a a a a a a 16 0 0 0 0 1 a a a a a a a 32 0 0 0 0 0 1 a a a a a a______________________________________
To allow indexing of the address, a portion of it can be substituted using the same method described previously for address substitution. The substitution portion (or field) of the address can be defined by a least significant bit justified variable length field (The continuation marker "1"; termination marker "0") that is superimposed on top of those shown in Table 10. Using an address of an eight bit word, as an example, Table 11 shows how to define the number of the least significant bits to be substituted. The least significant bit added is the substitution indicator (marked "w"). The general case of a Fixed width word for substitution is shown in FIG. 2.
TABLE 11______________________________________Address substitution Bits to be substituted A 9 8 7 6 5 4 3 2 1 0 w______________________________________0 0 0 0 1 a a a a a as a a 0 1 0 0 0 1 a a a a a a a 0 1 2 0 0 0 1 a a a a a a 0 1 1 3 0 0 0 1 a a a a a 0 1 1 1 4 0 0 0 1 a a a a 0 1 1 1 1 5 0 0 0 1 a a a 0 1 1 1 1 1 6 0 0 0 1 a a 0 1 1 1 1 1 1 7 0 0 0 1 a 0 1 1 1 1 1 1 1 8 0 0 0 1 0 1 1 1 1 1 1 1 1______________________________________
In effect the substitute code is superimposed on top of the address that is already coded. From this coding, it can be seen that there are illegal addresses, most obviously 0x0000 and 0x3fff. In this case, a "0" must be in the bottom 9 bits to prevent substituting more than 8 bits and a "1" in the top 6 bits specifies an allowable access width. If one of these errors is detected, the access is undefined, but the Register file contents will not be affected.
In accordance with the present invention, the system for addressing and for accessing partial words in a register file is discussed below.
The conventional memory circuitry dictates that the memory must always be accessed at it full width. To achieve variable width accesses, a full (32 bit) width word is read. This full word is rotated until the partial word accessed is justified in the LSB. The upper parts of the word are extended to the full width and then output. Extending may encompass padding with zeros or ones, sign extending, using the sign bit of a sign-magnitude number as the new MSB or any similar conventional method. Extending is dependent on the mode of operation. When the partial word is input to and written back into the memory, it is multiplexed back into the rotated full word, which is then rotated back and written into the array. FIG. 3 shows these steps for the access of a 4 bit partial word in the fourth four bit word of the 32 bit word.
To access or read partial words, such as the highlighted four bit word shown in row "1" 213 of FIG. 3, the full width word must be rotated to place the partial word at the LSB, as shown in row "2" 214. As shown in row "3" 215, the four bit word is extended to create a full 32 bit word: This word can now be accessed.
As shown in FIG. 3, a full width word that has been selected to be written back is truncated to the width of the original partial word which is multiplexed into the word shown in row "2" 214. At the LSB position, this is shown in row "4" 216. The resulting word is rotated back in its original significance in the read word, this is shown in row "5" 217. This full word can now be written back into the register file.
The following list, therefore, summarizes the steps numbered in FIG. 3:
1. Full word read from memory;
2. 12 bit rotated right puts partial word into the LSB;
3. Extended to full word, then passed to output;
4. The inputted partial word is multiplexed into rotated full word from (2); and
5. 12 bit rotated left puts full word back to original state to be written.
The above accesses suggests the data flow structure of the memory that is shown in FIG. 4. The numbers in the structure refer to the above text and to FIG. 3.
The memory address must be decoded to control the above structure. It should be recognized that the MSB of any width of address is at the same significance with reference to the memory. The top six bits of a decoded address are a 32 bit word address, whereas the remainder is a bit address. Therefore, the stage of decoding (in parallel with the substitution) is to decode the address width defining variable field by detecting the position of the most significant termination marker. This allows the address to be MSB justified (shifting in zeros at the LSB). The top six bits can be used directly as a 32 bit word row address of the memory. The bottom five bits can be used to directly control both barrel shifters (as seen in FIG. 4), because, for example, an original 32 bit address will always have a shift of 0b00000 (these having been shifted when the address was MSB justified). Similarly, a 16 bit address can have a shift of 0bx0000, i.e., 0 or 16 bit shift and a 1 bit address can have a shift of 0bxx, i.e., 0 to 31 bit shifts. The extender and input multiplexer are controlled by the access width decode to mask out the output words and multiplex the input words to an appropriate significance, respectively. The block diagram of the decode is shown in FIG. 5. It can be seen that the decode of the two variable width fields for width and substitution can be done in parallel and independently.
FIG. 2 illustrates an example of a fixed width word 13 bits long for addressing variable width data and substitution as shown in the bottom two rows. For these examples, an eight bit word would have been addressed at location 0b110lssss, where "ssss" is substituted from another address source.
Microcodable State Machine Structure
In accordance with the present invention, the substitution into a memory address and the variable width accessing of a memory have been brought together in the implementation of a microcodable state machine the structure of which is shown in FIG. 6. The structure is one of a state machine 218 providing control of an arithmetic core 219 by way of a wide word of control signals called a microcode instruction. The arithmetic core 219, in turn, passes status flags and some data to the state machine 218.
The state machine 218, in accordance with the present invention, includes a memory containing a list of the microcode instructions. As with conventional microcodable state machines, it is capable of either proceeding through the list of microcode instructions contiguously or a jump can occur from one instruction to another. The jump address is in the form shown in FIG. 7. The substituted value comes from the Arithmetic core 219 as shown in FIGS. 6 and 8. This allows the construction of "jump tables" within the microcode programs. Thus, if a jump is made with 3 bits substituted, for example, there are eight possible contiguous locations that may be jumped to, each dependent on the value from the arithmetic core, i.e., it has so become a programmable jump.
Arithmetic Core
The arithmetic core 219, as shown in FIG. 8, includes a memory called a register file 221, an Arithmetic and Logic unit (ALU) 222, an input port 223 and an output port 224. These components are connected via buses and multiplexers. As previously stated, these components, and the multiplexers defining their connections, are entirely controlled by the microcode instruction issued by the state machine 218. The ALU 222 and the ports 223 and 224 are conventional, however, the register file 221 is a memory which allows variable width indexed accesses. The addresses to the register file 221 is coded directly into the microcode instruction.
There are many advantages of using this method of addressing to the register file. First, many locations in an application do not need to be the full width of the memory (32 bits in this case). Whilst it will cause no effect on the operation of the device to use a full width location, it is very wasteful of memory locations. Minimizing the number of memory locations will minimize the amount of space used by the memory and, therefore, minimize the capacitive loading in the register file. This maximizes the speed of the register file. Second, the indexing combined with the variable width of memory accessing allows the stepping through of locations of variable width. In the one bit case this allows an elegant implementation of long division and multiplication.
In summary, therefore, there is described a procedure for addressing memory having the following steps: (1) providing a fixed width word having a predetermined fixed number of bits to be used for addressing variable width data; (2) defining the fixed width word with a width defining field and an address field providing the width defining field with at least one bit to serve as a termination marker; (3) defining the address field with a plurality of bits defining the address of the data; and (4) varying the size of bits in the address field in inverse relation to the size of the variable width data varying the number of bits in the width defining field in direct relation to the size of the variable width data and maintaining a fixed width word for addressing variable width data while varying the width of the width defining field and the address field. In addition, a procedure for addressing memory having the following steps is described: (1) providing a fixed width word having a predetermined fixed number of bits to be used for addressing data; (2) defining the fixed width word with an address field and a substitution field; (3) defining the address field with a plurality of bits defining the address of the data; (4) defining a variable width substitution field with at least one substitution bit; (5) the substitution field has at least one bit to serve as a termination marker between the address field and the substitution field; and (6) using the substitution field to indicate substituted bits from a separate addressing source and maintaining a fixed width word for addressing variable width data while inversely varying the width of the address field and the width of the substitution field. In addition, a process for addressing variable width data in a memory is described as having the following steps: (1) providing a memory having words of predetermined width and composed of partial words; (2) rotating the partial word to be accessed to a least significant bit justification; (3) extending the remaining part of the word so that the accessed word will be recognized as the partial word; and (4) restoring the remaining part of the word and rotating the word until the partial word is restored to its original position.
Detailed Description of the Invention for Transforming Data Using a Common Processing Block
This present embodiment, in accordance with the present invention, relates to a method for the transformation of signals from a frequency to a time representation, as well as a digital circuit arrangement for implementing the transformation.
It is a common goal in the area of telecommunications to increase both information content and transmission speed. Each communications medium, however, imposes a limitation on transmission speed, as does the hardware at the transmitting and receiving end that must process the transmitted signals. A telegraph wire is, for example, typically a much faster medium for transmitting information than the mail is, even though it might be faster to type and read a mailed document than to tap out a telegraph key.
The method of encoding transmitted information also limits the speed at which information can be conveyed. A long-winded telegraph message will, for example, take longer to convey than a succinct message with the same information content. The greatest transmission and reception speed can therefore be obtained by compressing the data to be transmitted as much as possible, and then, using a high-speed transmission medium, to process the data at both ends as fast as possible, which often means the reduction or elimination of `bottlenecks` in the system.
One application in which it is essential to provide high-speed transmission of large amounts of data is in the field of digital television. Whereas conventional television systems use analog radio and electrical signals to control the luminance and color of picture elements (`pixels`) in lines displayed on a television screen, a digital television transmission system generates a digital representation of an image by conveying analog signals into binary `numbers` corresponding to luminance and color values for the pixels. Modem digital encoding schemes and hardware structures typically enable much higher information transmission rates than do conventional analog transmission systems. As such, digital televisions are able to achieve much higher resolution and much more life-like images than their conventional analog counterparts. It is anticipated that digital television systems including so-called High-Definition TV (HDTV) systems, will replace conventional analog television technology within the next decade in much of in the industrialized world. The conversion from analog to digital imaging, for both transmission and storage will, thus, be similar to the change-over from analog audio records to the now ubiquitous compact discs (CD's).
In order to increase the general usefulness of digital image technology, standardized schemes for encoding digital images have been adopted. Once such standardized scheme is known as the JPEG standard and is used for still pictures. For moving pictures, there are at present two standards, MPEG and H.261, both of which carry out JPEG-like procedures on each of the sequential frames of the moving picture. To gain advantage over using JPEG repeatedly, MPEG and H.261 operate on the differences between subsequent frames, taking advantage of the well-known fact that the difference, that is, the movement between frames, is small. It, therefore, takes less time or space to transmit or store the information corresponding to the changes rather than to transmit or store equivalent still-picture information as if each frame in the sequence were completely unlike the frames closest to it in the sequence.
For convenience, all the current standards operate by breaking an image or picture into tiles or blocks, each block consisting of a piece of the picture eight pixels wide by eight pixels high. Each pixel is then represented by three (or more) digital numbers known as `components` of that pixel. There are many different ways of breaking a colored pixel into components, for example, using standard notation, e.g., YUV, YCr, Cb, RGB, etc. All the conventional JPEG-like methods operate on each component separately.
It is well known that the eye is insensitive to high-frequency components (or edges) in a picture. Information concerning the highest frequencies can usually be omitted altogether without the human viewer noticing any significant reduction in image quality. In order to achieve this ability to reduce the information content in a picture by eliminating high-frequency information without the eye detecting any loss of information, the 8-by-8 pixel block containing spatial information (for example, the actual values for luminance) must be transformed in some manner to obtain frequency information. The JPEG, MPEG and H.261 standards all use the known Discrete Cosine Transform to operate on the 8-by-8 spatial matrix to obtain an 8-by-8 frequency matrix.
As described above, the input data represents a square area of the picture. In transforming the input data into the frequency representation, the transform that is applied must be two-dimensional, but such two-dimensional transforms are difficult to compute efficiently. The known, two-dimensional Discrete Cosine Transform (DCT) and the associated inverse DCT (IDCT), however, have the property of being "separable". This means that rather than having to operate on all 64 pixels in the eight-by-eight pixel block at one time, the block can first be transformed row-by-row into intermediate values, which are then transformed column-by-column into the final transformed frequency values.
A one-dimensional DCT of order N is mathematically equivalent to multiplying two N-by-N matrices. In order to perform the necessary matrix multiplication for an eight-by-eight pixel block, 512 multiplications and 448 additions are required, so that 1,024 multiplications and 896 additions are needed to perform the full 2 dimensional DCT on the 8-by-8 pixel block. These arithmetic operations, and especially multiplication, are complex and slow and, therefore, limit the achievable transmission rate. They also require considerable space on the silicon chip used to implement the DCT.
The DCT procedure can be rearranged to reduce the amount of computation required. There are, at present, two main methods used for reducing the computation required for the DCT, both of which use "binary decimation". The term "binary decimation" means than an N-by-N transform can be computed by using two N2-by-N2 transformations, plus some computational overhead whilst arranging this. Whereas the eight-by-eight transform requires 512 multiplications and 448 additions, a four-by-four transform requires only 64 multiplications and 48 additions. Binary decimation, thus, saves 284 multiplications and 352 additions and the overhead incurred in performing the decimation is typically insignificant compared to the reduction in computation.
At present, the two main methods for binary decimation were developed by Eong Gi Lee (`A New Algorithm to Compute the DCT`) IEEE Transactions on Acoustics, Speech and Signal Processing, Vol. Assp 32, No. 6, p 1243 December 1984) and Wen-Hsiung Chen (`A Fast Computational Algorithm for the DCT`, Wen-Hsiung Chen, C. Harrison Smith, S. C. Pralick, IEEE Transactions on Communications, Col. Com 25, No. 9 1004, September 1977). Lee's method makes use of the symmetry inherent in the definition of the inverse DCT and, by using simple cosine identities, it defines a method for recursive binary decimation. The Lee approach is only suitable for the IDCT.
The Chen method uses a recursive matrix identity that reduces the matrices into diagonals only. This method provides easy binary decimation of the DCT using known identities for diagonal matrices.
A serious disadvantage of the Lee and Chen methods is that they are unbalanced in respect of when multiplications and additions must be performed. Essentially, both of these methods require that many additions be followed by many multiplications, or vice versa. When implementing the Lee or Chen methods in hardware, it is, therefore, not possible to have parallel operation of adders and multipliers. This reduces their speed and efficiency since the best utilization of hardware is when all adders and multipliers are used all the time.
An additional disadvantage of such known methods and devises for performing DCT and IDCT operations is that it is usually difficult to handle the so-called normalization coefficient, and known architectures require adding an additional multiplication time when all the multipliers are being used.
Certain known methods for applying the forward and inverse DCT to video data are very simple and highly efficient for a software designer who need not be concerned with the layout of the semiconductor devices which perform the calculations. Such methods, however, often are far too slow or are too complex in semiconductor architecture and hardware interconnections to perform satisfactorily at the transmission rate desired for digital video.
Yet another shortcoming of existing methods and hardware structures for performing DCT and IDCT operations on video data is that they require floating-point internal representation of numerical values. To illustrate this disadvantage, assume that one has a calculator that is only able to deal with three-digit numbers, including digits to the right of the decimal point (if any). Assume further that the calculator is to add the numbers 12.3 and 4.56 (Notice that the decimal point is not fixed relative to the position of the digits in these two numbers. In other words, the decimal point is allowed to `float`). Since the calculator is not able to store the four digits required to fully represent the answer 16.86, the calculator must reduce the answer to three digits either by truncating the answer by dropping the right-most `6`, yielding an answer of 16.8, or it must have the necessary hardware to round the answer up to the closest three-digit approximation 16.9.
As this very simple example illustrates, if floating-point arithmetic is required, one must either accept a loss of precision or include highly complicated and space-wasting circuitry to minimize rounding error. Even with efficient rounding circuitry, however, the accumulation and propagation of rounding or truncation errors may lead to unacceptable distortion in the video signals. This problem is even greater when the methods for processing the video signals require several multiplications, since floating point rounding and truncation errors are typically greater for multiplication than for addition.
A much more efficient DCT/IDCT method and hardware structure would ensure that the numbers used in the method could be represented with a fixed decimal point, but in such a way that the full dynamic range of each number could be used. In such a system, truncation and rounding errors would either be eliminated or, at least, greatly reduced.
In the above example, if the hardware can handle four digits, no number greater than 99.99 were ever needed, and every number had the decimal point between the second and third places, then the presence of the decimal point would not affect calculations at all. Accordingly, the arithmetic could be carried out just as if every number were an integer, e.g., the answer 1230+0456=1686 would be just as clear as 12.30+4.56=16.86, since one would always know that the `1686` should have a decimal point between the middle `6` and `8`. Alternatively, if numbers (constant or otherwise) are selectively scaled or adjusted so that they all fall within the same range, each number in the range couldis ao be accurately and unambiguously represented as a set of integers.
One way of reducing the number of multipliers needed is simply to have a single multiplier that is able to accept input data from different sources. In other words, certain architectures use a single multiplier to perform the multiplications required in different steps of the DCT or IDCT calculations. Although such "crossbar switching" may reduce the number of multipliers required, it means that large complicated multiplexer structures must be included instead to select the inputs to the multiplier, to isolate others from the multiplier, and to switch the appropriate signals from the selected sources to the inputs of the multiplier. Additional large-scale multiplexers are also required to switch the large number of outputs from the shared multipliers to the appropriate subsequent circuitry. Crossbar switching or multiplexing is, therefore, complex, is generally slow (because of the extra storage needed) and costs are significant in a final semiconductor implementation.
Still another drawback of existing architectures, including the "crossbar switching" is that they require general purpose multipliers. In other words, existing systems require multipliers for which both inputs are variable. As is well known, implementations of digital multipliers typically include rows of adders and shifters such that, if the current bit of a multiplier word is a `one` the value of the multiplicand is added into the partial result, but not if the current bit is a `zero`. Since a general purpose multiplier must be able to deal with the case in which every bit is a `1`, a row of adders must be provided for every bit of the multiplier word.
By way of example, assume that data words are 8 bits wide and that one wishes to multiply single inputs by 5. An 9-bit representation of the number 5 is 00000101. In other words, digital multiplication by 5 requires only that the input value be shifted to the left two places (corresponding to multiplication by 4) and then added to its up-shifted value. The other six positions of the coefficients have bit values of `0`, so they would not require any shifting or additional steps.
A fixed-coefficient multiplier, that is, in this case, a multiplier capable of multiplying only by five, would require only a single shifter and a single adder in order to perform the multiplication (disregarding circuitry needed to handle carry bits). A general purpose multiplier, in contrast, would require shifters and adders for each of the eight positions, even though six of them would never need to be used. As the example illustrates, fixed coefficients can simplify the multipliers since they allow the designer to eliminate rows of adders that correspond to zeros in the coefficient, thus saving silicon area.
In an IDCT method, in accordance with the present invention, a one-dimensional IDCT for each N-row and N-column of N-by-N pixel blocks is decimated and a 1-D IDCT is performed separately on the N-2 even-numbered pixel input words and the N-2 odd-numbered pixel input words.
In a preferred embodiment, N=8 according to the JPEG standard. The two-dimensional IDCT result is then obtained by performing two one-dimensional IDCT operations in sequence (with an intermediate reordering-transposition-of data).
In a common processing step, for N=8, a first pair of input values is passed without need for multiplication to output adders and subtractors. Each of a second pair of input values is multiplied by each of two constant-efficient values corresponding to two scaled cosine values. No other multiplications and only one subtraction and one addition are required in the common processing step. The second pair is then added or differenced pairwise with the first pair of input values to form even or odd resultant values.
In a pre-common processing stage, the lowest order odd input word is pre-multiplied by the square root of two and the odd input words are summed pairwise before processing in the common processing block In a post-common processing stage, intermediate values corresponding to the processed odd input words are multiplied by predetermined constant coefficients to form odd resultant values.
After calculation of the even and odd resultant values, the N/2 high-order outputs are formed by simple subtraction of the odd resultant values from the even resultant values, and the N/2 low-order outputs are formed by simple addition of the odd resultant values and the even resultant values.
For both the DCT (at the transmission end of a video processing system) and the IDCT (at the receiving end, which incorporates one or more of the various aspects of the present invention), the values are preferably and deliberately scaled downward by a factor of two by a simple binary right shift. This deliberate, balanced, upward scaling eliminates several multiplication steps that are required according to conventional methods.
According to another aspect of the method, in accordance with the present invention, selected bits of constant coefficient or intermediate resulting data words are rounded or adjusted by predetermined setting of selected bits to either `1` or `0`.
Two-dimensional transformation of pixel data is carried out by a second, identical 1-D operation on the output values from the first 1-D IDCT processing steps.
An IDCT system, according to yet another aspect of the present invention, includes a pre-common processing circuit, and a common processing circuit, in which the pre-common, common, and post-common processing calculations are performed on input data words. A supervisory controller generates control signals to control the loading of various system latches; preferably, to serially time-multiplex the application of the N/2 even and N/2 odd-numbered input words to input latches of the pre-common block to direct addition of the even and odd resultant values to form and latch low order output signals and to direct subtraction of the odd resultant values from the even resultant values to form and latch the high-order output signals and to sequentially control internal multiplexers.
In the present invention, even and odd input words are preferably processed in separate passes through the same processing blocks. Input data words are preferably (but not necessarily) latched, not in strictly ascending or descending order, but rather in an order enabling an efficient `butterfly` structure for the data path.
Furthermore, at least the common processing circuit may be configured as a pre-logic circuit, with no clock or control signals required for its proper operation, as may be other processing blocks, depending on the particular application.
No general-purpose multipliers (with two variable inputs) are required. Rather, constant coefficient multipliers are included throughout the preferred embodiment. Furthermore, fixed-point integer arithmetic devices are included in the preferred embodiment of the invention and can be so designed as to provide a method and system for performing IDCT transformation of video data with one or more of the following features:
1. Constant use of all costly arithmetic operations;
2. In order to reduce the silicon area needed to implement the IDCT, there are a small number of storage elements (such as latches), preferably no more than required for efficient pipelining of the architecture, coupled with a small number of constant coefficient multipliers rather than general purpose multipliers that require extra storage elements;
3. Operations are arranged so that each arithmetic operation does not need to use sophisticated designs, for example, if known `ripple adders` are used, these would allow sufficient time to `resolve` (see below) or produce their answers; if operations are arranged in such a way that other devises precede the rearranging operations so as to avoid delay and to allow greater throughput and efficiency;
4. One is able to generate results in a natural order;
5. No costly, complex, crossbar switching is required;
6. The architecture is able to support much faster operations; and
7. The circuitry used to control the flow of data through the transform hardware can be small in area.
Theoretical Background of the Invention
In order to understand the purpose and function of the various components and the advantages of the signal processing method used in the IDCT system according to the present invention, it is helpful to understand the system's theoretical basis.
Separability of a Two-Dimensional IDCT
The mathematical definition of a two-dimensional forward discrete cosine transforms (DCT) for an N.times.N block of pixels is as follows, where U(j,k) are the pixel frequency values corresponding to the pixel absolute values X(m,n) ##EQU1##
The terms 2N govern the dc level of the transform, and the coefficients c(j), c(k) are known normalization factors.
The expression for the corresponding inverse discrete cosine transform, that is for the IDCT, is as follows: ##EQU2##
The forward DCT is used to transform spatial values (whether representing characteristics such as luminance directly, or representing differences, such as in the MPEG standard) into their frequency representation. The inverse DCT, as its name implies, operates the other `direction`, that is, the IDCT transforms the frequency values back into spatial values.
In the expression, Equation 2, (E2), note that the cosine functions each depend on only one of the summation indices.
The expression E2 can therefore be rewritten as: ##EQU3##
This is the equivalent of a first one-dimensional IDCT performed on the product of all terms that depend on k and n, followed, after a straightforward standard data transposition by a second one-dimensional IDCT using as inputs the outputs of the first IDCT operation.
Definition of the 1-D IDCT
A 1-dimensional N-point IDCT (where n is an even number) is defined by the following expression. ##EQU4## and where y(n) are the N inputs to the inverse transformation function and x(k) are its N outputs. As in the 2-D case, the formula for the DCT has the same structure under the summation sign, but with the normalization constant outside the summation sign and with the x and y vectors switching places in the equation.
Resolution of a 1-D IDCT
As is shown above, the 2-D IDCT can be calculated using a sequence of 1-D IDCT operations separated by a transpose. In accordance to one embodiment, each of these 1-D operations is, in turn, broken down into sub-procedures that are then exploited to reduce even further the required size and complexity of the semiconductor implementation.
Normalization of Coefficients
As is discussed above, an important design goal for IDCT hardware is the reduction of the required number of multipliers that must be included in the circuitry. Most methods for calculating the DCT of IDCT, therefore, attempt to reduce the number of multiplications needed. According to this embodiment, however, all the input values are deliberately scaled upward by a factor of the square root of two. In other words, using the method according to this embodiment of the present invention, the right-hand side of the IDCT expression (E) is deliberately multiplied by the square root of two.
According to this embodiment, two 1-D IDCT operations are performed in series (with an intermediate transpose) to yield the final 2-D IDCT result. Each of these 1-D operations includes a multiplication by the same square root of two factor. Since the intermediate transposition involves no scaling, the result of two multiplications by the square root of two in series is that the final 2-D results will be scaled upward by a factor two. To obtain the unscaled value, the circuitry need then only divide by two. Since the values are all represented digitally, this can be accomplished easily by a simple right shift of the data. As is made clearer below, the upward scaling by the square root of two in each 1-D IDCT stage and final down-scaling by 2 is accomplished by adders, multipliers and shifters all within the system's hardware, so that the system places no requirements for scaled inputs on the other devises to which the system may be connected. Because of this, the system is compatible with other conventional devises that operate according to the JPEG or MPEG standards. Normalization according to this embodiment of the present invention, therefore, eliminates the need for hardware multipliers within the IDCT semiconductor architecture for at least two square root of two multiplication operations. As is explained below in greater detail, the single additional multiplication step (upward scaling by the square root of two) of the input data in each 1-D operation leads to the elimination of still other multiplication steps that are required when using conventional methods.
Separation of the 1-D IDCT into High and Low-Order Outputs
Expression E can now be evaluated separately for the N/2 low-order outputs (k=0, 1, . . . , N/2-1) and the N/2 high order outputs (k=N/2, k=N/2+1, . . . N). For N=8, this means that one can first transform the inputs to calculate y(0), y(1), y(2) and y(3), and then transform the inputs to calculate y(4), y(5), y(6) and y(7).
Introduce the variable k'=(N-1-k) for the high-order outputs (k=N/2+1, . . . , N), so that k' varies from (N/2-1) to N as k varies fm ro(N/2+1) to N. For N=8, this means that k'=(3,2,1,0) for k=(4,5,6,7). It can then be shown that expression E can be divided into the following two subexpressions E5 (which is the same as E except for the interval of summation) and E6:
Low order outputs: ##EQU5##
High-order outputs: ##EQU6##
Note that both E5 and E6 have the same structure under the summation sign except that the term (-1)n changes the sign of the product under the summation sign for the odd-numbered inputs (n odd) for the upper N2 output values and except that the y term will be multiplied by c(O)=1/.sqroot.2.
Separation of the IDCT into Even and Odd Inputs
Observe that the single sum in the 1-D IDCT expression E4 can also be separated into two sums: one for the even-numbered inputs (for N=8 y(0), y(2), y(4), and y(6) and one for the odd-numbered inputs (for n=8, y(1), y(3), y(5), and y(7). Let g(k) represent the partial sum for the even-numbered inputs and h(k) represent the partial sum for the odd-numbered inputs.
Thus: ##EQU7##
Now recall the known cosine identity:
2.cos A.cos B=cos(A+B)+cos(A-B), and set A=.pi.(2k+1)/2N and B=.pi.(2k+1)(2N+1)/2N.
One can then multiply both sides of the expression E8 by:
2.cos A=1/{2cos[.pi.(2k+1)/2N]}=Ck.
Note that, since Ck does not depend on the summation index n, it can be moved within the summation sign. Assume then by definition that y(-1)=0, and note that the cosine function for the input y(7) is equal to zero. The expression for h(k) can then be rewritten in the following form: ##EQU8## Note that the inputs [y(2n+1)=y(2n-1)] imply that in calculating h(k), the odd input terms are paired to form N/2 paired inputs p(n)=[y(2n+1)=y(2n-1)].
For N=8 the values of p(n) are as follows:
______________________________________n p(n)______________________________________0 y(-1) + Y(1) = Y(1) Y(-1) = 0 by definition 1 y(1) + y(3) 2 y(3) + y(5) 3 y(5) + y(7)______________________________________
Expression E9 for h(k) can then be represented by the following: ##EQU9##
Observe now that the cosine term under the summation sign is the same for both g(k) and h(k) and that both have the structure of a 1-D IDCT (compared with expression E5). The result of the IDCT for the odd k terms, that is, for h(k), however is multiplied by the factor Ck=1/{2.cos [.pi.(2k+1)/2N.
In other words, g(k) is an n/2-point IDCT operating on even inputs y(2n) and h(k) is an n/2-point IDCT operating on [y(2n+1)=y(2n=1)] where y(-1)=0 by definition.
Now introduce the following identities:
yn=y(n);
c1=cos(n8);
c2=cos(2n8)=cos(n4)=1..sqroot.2;
c3=cos(3n8);
d1=1[2.cos(n1610)];
d3=1[2.cos(3.pi./116)];
d5=1[2.cos(5.pi./116)]; and
d7=1/[2.cos(97.pi./16)].
Further introduce scaled cosincoe efficients as follows:
c1s=.sqroot.2.cos(.pi./8);
c3s=.sqroot.2.cos(3.pi.8);
Using the evenness (cos(-.phi.)=cos(.phi.)) and periodicity (cos(-.phi.)).pi.(-.phi.)=-cos(.phi.) of the cosine function, expressions E7 and E8 can then be expanded for N=8 to yield (recall also (O) is 1/.sqroot.2; ##EQU10##
Now, recall that according to this embodiment of the present invention, all values are scaled upward by a factor of 2 for both the DCT and IDCT operations. In other words, according to the embodiment, both h(k) and g(k) are multiplied by this scaling factor. The g(k) and h(k) expressions, erthefore, become: ##EQU11##
Notice that since c2=cos (.pi./4)=1/.sqroot.2, multiplication by .sqroot.2, gives a scaled c2 value=1. By scaling the expressions (corresponding to upward scaling of the values of the video absolute and frequency values) according to this embodiment, it is, therefore, possible to eliminate the need to multiply and c3s, both of which are constant coefficients so that general utility multipliers are not needed. This, in turn, eliminates the need for the corresponding hardware multiplier in the semiconductor implementation of the IDCT operations.
The similarity in structure of g(k) and h(k) can be illustrated by expressing these sets of equations in matrix form. Let C be the 4.times.4 cosine coefficient matrix defined as follows: ##EQU12##
Where D=diag[d1, d3, d5, d7]=the 4.times.4 matrix with d1, d3, d5, and d7 along the diagonal and with other elements equal to zero. As E14 and E15 show, the procedures for operating on even-numbered inputs to get g(k) and for operating on the odd-numbered inputs to get h(k) both have the common step of multiplication by the cosine coefficient matrix C. To get h(k), however, the inputs must first be pairwise summed (recalling that y(-1)=0 by definition), y(1) must be premultiplied by 2, and the result of the multiplication by C must be multiplied by D.
As the expressions above also indicate, the N-point, 1-D IDCT (see E4) can also be split into the two N/2-point, 1-D IDCTs each involving common core operations (under the summation sign) on the N/2 odd (grouped) and the N/2 even input values. The expressions above yield the following simple structure for the IDCT as implemented in this embodiment:
Low-order outputs for (N=8, outputs k={0,1,2,3}):
u(k)=g(k)+h(k) Equation 16
High-order outputs (for N=8, outputs k={4,5,6,7}):
y(k)=y(N-1-k')=g(k')-h(k') Equation 17
Note that g(k) operates directly on even input values to yield output values directly, whereas h(k') involves grouping of input values, as well as multiplication by the values d1, d3, d5 and d7.
As always, the designer of an IDCT circuit is faced with a number of trade-offs, such as size versus speed and greater number of implemented devices versus reduced interconnection complexity. For example, it is often possible to improve the speed of computation by including additional, or more complicated devices on the silicon chip, but this obviously makes the implementation bigger or more complex. Also, what is available or desired on the IDCT chip may limit or preclude the use of sophisticated, complicated, designs such as "look-ahead" adders.
Standards of Accuracy
Assuming infinite precision and accuracy of all calculations, and, thus, unlimited storage space and calculation time, the image recreated by performing the IDCT and DCT-transformed image data would reproduce the original image perfectly. Of course, such perfection is not to be had using existing technology.
In order to achieve some standardization, however, IDCT systems are at present measured according to a standardized method put forth by the Comite Consultatif International Telegraphique et Telephonique (`CCIT`) in `Annex 1 of CCITT Recommendations H.261--Inverse Transform Accuracy Specification.` This test specifies that sets of 10,000 8-by-8 Blocks containing random integers be generated. These blocks are then DCT and IDCT transformed (preceded or followed by predefined rounding, clipping and arithmetic operations) using predefined precision to produce 10,000 sets of 8-by-8 `reference` IDCT output data.
When testing an IDCT implementation, the CCITT test blocks are used as inputs. The actual IDCT transformed outputs are then compared statistically with the known `reference` IDCT output data. Maximum values are specified for the IDCT in terms of peak, mean, mean square, and mean mean error of blocks as a whole and as individual elements. Furthermore, the IDCT must produce all zeros output if the corresponding input block contains all zeros, and the IDCT must meet the same standards when the sign of all input data is changed. Implementations of the IDCT are said to have acceptable accuracy only if their maximum errors do not exceed the specified maximum values when these tests are run.
Other known standards are those of the Institute of Electrical and Electronic Engineers (`IEEE`), in `IEEE Draft Standard Specification for the Implementation of 8 by 8 Discrete Cosine Transform`, P1180/D2, Jul. 18, 1990; and Annex A of `8 by 8 Inverse Discrete Cosine Transform`, ISO committee Draft CD 11172-2. These standards are essentially identical to the CCITT standard described above.
Hardware Implementation
FIG. 9 is a simplified block diagram illustrating the data flow of the IDCT method according to one embodiment of the present invention (although the hardware structure, as is illustrated and explained below, is made more compact and efficient). In FIG. 9, the inputs to the system such as Y[0] and Y[4], and the outputs from the system, such as X[3] and X[6], are shown as being conveyed on single lines. It is to be understood that each of the single-drawn lines in FIG. 9 represents several conductors in the form of data buses to convey, preferably in parallel, the several-bit wide data words to which each input and output corresponds.
In FIG. 9, the large open circles 225 and 226 represent two-input adders, whereby a small circle 227 at the connection point of an input with the adder indicates that the complement of the corresponding input word is used. Adders with such a complementing input, thus, subtract the complemented input from the non complemented input. For example, although the output T0 from the upper left adder will be equal to Y[0]+Y[4] that its T0=Y0+Y4, the adder with the output T1 forms the value Y0+(-1),* Y4=Y0-Y4. Adders with a single complementing input can, therefore, be said to be differencing components.
Also in FIG. 9, constant-coefficient multipliers are represented by solid triangles 230 in the data path. For example, the input Y1 passes through a square root of two multiplier before entering the adder to form B0. Consequently, the intermediate value T3=Y2. T3=Y2.c1S+Y6.c3s, and the intermediate value B2=p1.c3s-p1.c1s=(Y1+Y3).c3s-(Y5+Y7).c1s. By performing the indicated additions, subtractions, and multiplications, one will see that the illustrated structure implements the expressions E11 and E12 for g(0) to g(3) and h(0) to h(3).
FIG. 9 illustrates an important advantage of the embodiment, in accordance with the present invention. As FIG. 9 shows, the structure is divided into four main regions: a pre-common block, PREC 231, that forms the paired inputs p(k) and multiplies the input y(1) by the square root of two; a first post-common block, POSTC1 233, that includes four multipliers for the constants d1, d3, d5, d7 (see expression E12); a second post-common block, POSTC2 235, that sums the g0 to g3 terms and the h0 to h3 terms for the low order outputs, and forms the difference of the g0 to g3 terms and the h0 to h3 terms for the high-order outputs (See expressions E17 and E17); and a common block, CBLK 232, is included in both the even and odd data paths. In the processing circuitry according to the embodiment of the present invention, the common operations performed on the odd and even numbered inputs are carried out by a single structure, rather than duplicated structure as illustrated in FIG. 9.
To understand the method of operation and the advantages of certain digital structures used in the embodiment, it is helpful to understand what "carry bits". As a simple example, note that the addition of two binary numbers is such that 1+1=0, with a carry of "1", which must be added into the next higher order bit to produce the correct result "`10`" (the binary representation of the decimal number "2"). In other words, 01+01=00 (the "sum" without carry)+10 (the carry word); adding the "sum" to the "carry word" one gets the correct answer 00+10=10.
As a decimal example, assume that one needs to add the numbers `436` and `825`. The common procedure for adding two numbers by hand typically proceeds as follows:
1. Units `6` plus `5` is `1` with a carry of `1` into the `tens` position--Sum: 1, Carry-in: 0, Carry-Out: 0.
2. Tens: `3` plus `2` is `6`, plus the `1` carried from the preceding step, gives `6` with no carry--Sum: 5, Carry-In: 0, Carry-Out:0.
3. Hundreds: `4` plus `8` is `2` with a carry of 1 into the thousands, but with no carry to be added in from the previous step; Sum: 2, Carry-in:), Carry-Out:1
4. Thousands: `0` plus `0`, plus the `1` carried from the hundreds gives, `1` Sum: 0, Carry-In: 1, Carry-Out:0.
The answer, `1261`, is, thus, formed by adding the carry-in sum for each position to the sum for the same position, with the carry-in to each position being the carry-out of the adjacent lower-order position. (Note that this implies that the carry-in to the lowest order position is always a `0`). The problem, of course, is that one must wait to add the `4` and `8` in the hundreds place until one knows whether there will be a carry-in from the tens place. This illustrates a "ripple adder", which operates essentially in this way. A ripple adder, thus, achieves a `final` answer without needing extra storage elements, but it is slower than some other designs.
One such alternative design is known as `carry-save`, in which the sum of two numbers for each position is formed by storing a partial sum or result word (in this example, 0251) and the carry values in a different word (here, 1010). The full answer is then obtained by `resolving` the sum and carry words in a following addition step, thus, 0251+1010=1261. Note that one can perform the addition for every position at the same time, without having to wait to determine whether a carry word can be added to the partial result at any time as long as it is saved.
Since the resolving operations typically require the largest proportion of the time required in each calculation stage, speeding up these operations has a significant effect on the overall operating speed while requiring only a relatively small increase in the size of the transform. Carry-save multipliers, therefore, are usually faster than those that use ripple adders in each row. However, this gain in time comes at the cost of greater complexity, since the carry word for each addition in the multiplier must be either stored or passed down to the next addition. Furthermore, in order to obtain the final product of a multiplication, the final partial sum and final carry word will have to be resolved, normally by addition in a ripple adder. Note, however, that only one ripple adder will be needed, so that the time savings are normally proportional to the size of the multiplication that must be performed. Furthermore, note that a carry word may be treated as any other number to be added in and as long as it is added in at some time before the final multiplication answer is needed, the actual addition can be delayed.
In this embodiment of the present invention, this possibility of delaying resolution is used to simplify the design and to increase the throughout of the IDCT circuitry. Also, certain bits of preselected carry words are, optionally and deliberately forced to predetermined values before resolution in order to provide greater expected accuracy of the IDCT result based on a statistical analysis of test runs of the invention on standard test data sets.
FIG. 10 is a block diagram that illustrates a preferred structure, in accordance with the present invention. In this preferred embodiment of the present invention, the even and odd numbered inputs are time-multiplexed and are processed separately in the common block CBLK 232. The inputs may be processed in either order.
In FIG. 10, the notation Y[1,0], Y[5,4], Y[3,2] and Y[7,6] is used to indicate that the odd numbered inputs Y1, Y3, Y5, Y7 preferably pass through the calculation circuitry first, followed by the even numbered inputs Y0, Y2, Y4, Y6. This order is not essential to the present embodiment; nonetheless, as is explained below, certain downstream arithmetic operations are performed only on the odd numbered inputs, and by entering the odd numbered input values first, these downstream operations can be processing at the same time that arithmetic operations common to all inputs are performed upstream on the even numbered inputs. This reduces the time that several arithmetic devices would otherwise remain idle.
Similarly, the notation X[0,7], X[1,6], X[3,4], X[2,5] is used to indicate that the low order outputs X0, X1, X2, X3 are output first, followed by the high order outputs X4, X5, X6, X7.
As FIGS. 9 and 10 illustrate, the inputs are preferably initially not grouped in ascending order, although this is not necessary since to odd numbered inputs are Y1, Y5, Y3, and Y7. Arranging the input signals in this order makes possible the simple `butterfly` data path structure shown in FIGS. 9 and 10 and greatly increases the interconnection efficiency of the implementation of the present invention in silicon semiconductor devices.
As shown in FIG. 10, adders and subtractors are indicated by circles either a `+` (adder) 235, `-` (subtractor ) 236 which is an adder with one complementing input or `.+-.` (resolving adder/subtractor, which is able to switch between addition and subtraction 237). The left most adders and subtractors in the common block 232 of the two m-bit input words is the m-bit partial resulting parallel with the m-bit or (m-1) bit word containing the carry bits of the addition/subtraction. In other words, the first additions and subtractions in the common block CBLK 232 are preferably unresolved, meaning that the addition of the carry bits is delayed until a subsequent processing stage. The advantage of this step is that such carry-save adder/subtractors since they do not need to perform the final addition of the carry-bit word to the result. Resolving adders may, however, also be used in order to reduce the bus width at the outputs of the adders.
FIG. 10 also illustrates the use of one and two input latches in the preferred embodiment of the present invention. In FIG. 10, latches are illustrated as rectangles 238 and are used in both the pre-common block PREC 231 and the post-common block POSTC 233. Single-input latches are used at the inputs of the multipliers D1, D3, D5 and D7, as well as to latch the inputs to the resolving adders/subtractors which are the computed g(k) and h(k) values corresponding to the respective outputs from latches g[0,7], g[1,6], g[3,4] and g[2,5] and h[0,7], h[1,6], h[3,4] and h[2,5]. As such, the resolving adders/subtractors perform the addition or subtraction indicated in expressions E16 and E17 above.
As described previously, the even-numbered inputs Y0, Y2, Y4 and Y6 do not need to be paired before being processed in the common block CBLK 232. However, not only do the odd-numbered inputs require such pairing, but the input Y12 must also be multiplied by the square root of two in order to ensure that proper input values are presented to the common block CBLK 232. The pre-common block PREC 231, therefore, includes a 2-input multiplexing (`mux`) latch C10, C54, C32 and C76 for each input value. One input to the 2-input mux latch is consequently tied directly to the unprocessed input values, whereas the other input is received from the resolving adders and, for the input Y.sub.1, the resolving square root of two multiplier. The correct paired or unpaired inputs can, therefore, be easily presented to the common block CBLK 232 easily by simple switching of the multiplexing latches between their two inputs.
As FIG. 10 illustrates, the square root of two multipliers D1, D3, D5, D7 preferably resolve their outputs, that is, they generate results in which the carry bits have been added in to generate a complete sum. This ensures that the outputs from the multipliers have the same bus width as the un-multiplied inputs in the corresponding parallel data paths.
The preferred embodiment of the common block 232, in accordance with the present invention, also includes one `dummy` subtractor 240 in the forward data path for Y[1,0] and Y[5,4], respectively. These devices act to combine the two inputs (in the case of the dummy subtractor, after 2's-complementing the one input) in such a way that they are passed as parallel outputs. In each case, the one input is manipulated as if it contained carry bits, which are added on in the subsequent processing stage. The corresponding addition and subtraction is, thus, performed, although it is delayed.
This technique reduces the resources required in the upper two data paths since a full-scale adder/subtractor need not be implemented for these devices. Therefore, the `combiners` act as adders and subtractors and can be implemented for these devices and can be implemented either as simple conductors to the next device (for addition), or as a row of inverters (for subtraction), either of which requires little or no additional circuitry.
The use of such combiners also means that the outputs from the initial adders and subtractors in the common block CBLK 232 will all have the same width and will be compatible with the outputs of the carry-save adder/subtractor found in the bottom two data paths, with which they form inputs to the subsequent resolving adders and subtractors in the common block CBLK.
As described previously, the even-numbered inputs are processed separately from the odd-numbered inputs in this preferred embodiment of the present invention. Assume, further, that the odd-numbered inputs are to be processed first. Supervisory control circuitry (not shown in FIG. 10) applies the odd-numbered input words to the pre-common block PREC, and selects the lower inputs (viewed as in FIG. 10) of the multiplexing latches C10, C54, C32, C76 which then stores the paired values p0 to p3 (see FIG. 9 and the definition of p(n) above). The latches 1h0, h1, 1h3 and 1h2 are then activated to latch the values H0, H1, H3 and H2, respectively.
The supervisory control circuitry latches and then selects the upper inputs of the two-input multiplexing latches C10, C54, C32 and C76 in the precommon block PREC 231 and applies the even numbered input words to these latches. Since the even-numbered inputs are used to form the values of g0 to g3, the supervisory control circuitry also opens the latches Lg0 to Lg3 in the post-common block POSTC 233, to store the g(k) values.
Once the g(k) and h(k) values are latched, the post-common block POSTC 233 outputs the high-order signals X7, X6, X5 and X4 by switching the resolving adder subtractors to the subtraction mode. The low order output signals X3, X2, X1 and X0 are then generated by switching the resolving adders/subtractors to the addition mode. Note that the output data can be presented in an arbitrary order, including natural order.
The preferred multiplexed implementation, in accordance with the present invention, is illustrated in greatly simplified, schematic form in FIG. 10, performs the same calculations as the non-multiplexed structure illustrated in FIG. 9. The number of adders, subtractors and multipliers in the common block CBLK 232 is, however, cut in half and the use of dummy adder/subtractors 240 further reduces the complexity of the costly arithmetic circuitry.
FIG. 11 illustrates the main components and data lines of an actual implementation of the IDCT circuit according to the embodiment of the present invention. The main components include the precommon block circuit PREC 231, the common block circuit CBLK 232, and the post-common block POSTC 233. The system also includes a controller CNTL 241 that either directly or indirectly applies input, timing and control signals to the precommon block PREC 231 and post-common block POSTC 233.
In the preferred embodiment of the present invention, the input and output signals (Y0 to Y7 and X0 to X7, respectively) are 22 bits wide. Tests have indicated that this is the minimum width that is possible which still yields acceptable accuracy as measured by existing industry standards. As is explained in greater detail below, this minimum width in achieved in part by deliberately forcing certain carry words in selected arithmetic devices to be either a `1` or a `0`. This bit manipulation, corresponding to an adjustment of certain data words, is carried out as the result of a statistical analysis of the results of the IDCT system, in accordance with the present invention, to the after using the IDCT transformation of known input test data. By forcing certain bits to predetermined values, it was discovered that the effects of rounding and truncation errors could be reduced, so that the spatial output data from the IDCT system could be made to deviate less from the known `correct` spatial data. The present invention is equally applicable, however, to other data word lengths since the components used in the circuit according to the present embodiment can all be adapted to different bus widths using known methods.
Although all four inputs that are processed together could be input simultaneously to the pre-common block PREC along 88 parallel conductors (4.times.22), pixel words are typically converted one at a time from the transmission data. According to the present embodiment, input data words are, therefore, preferably all conveyed serially over a single 22 bit input bus and each input word is sequentially latched at the proper input point in the data path. As shown in FIG. 11, the 22 bit input data bus is labelled T.sub.-- IN[21:0] 242.
In the Figures and in the discussion below, the widths of multiple-bit signals are indicated in brackets with the high-order bit to the left of a colon `:` and the least significant bit (LSB) to the right of the colon. For example, the input signal T IN[21:0] 242 is 22 bits wide, with the bits being numbered from 0 to 21. A single bit is identified as a single number within square brackets, thus, T.sub.-- IN[1] indicates the next to least significant bit of the signal T.sub.-- IN.
The following control signals are used to control the operation of the pre-common block PREC 231 in the preferred embodiment of the present invention.
IN.sub.-- CLK.sub.-- OUT CLK The system, in accordance with the present invention, preferably uses a non-overlapping two phase clock. The signals IN.sub.-- CLK and OUT.sub.-- CLK are accordingly columns of latches that hold the values of input, intermediate, and output signals.
LATCH10, LATCH54, LATCH32, LATCH76: Preferably, one 22-bit word is input to the system at a time. On the other hand, four input signals are processed at a time. Each input signal must, therefore, be latched at its appropriate place in the architecture before being processed with three other input words. These latch signals are used to enable the respective input latches. The signal LATCH54, for example, is first used to latch input signal Y5 and later to latch input signal Y4, which enters the pre-common block PREC 231 at the same point as the input signal Y5 (see FIG. 10) but during a subsequent processing stage.
LATCH: Once the four even or odd-numbered input signals are latched into the pre-common block PREC 231, they are preferably shifted at the same time to a subsequent column of latches. The signal LATCH is used to enable a second column of input latches that hold the four input values to be operated on by the arithmetic devices in the pre-common block PREC 231.
SEL.sub.-- BYP, SEL.sub.-- P: As FIG. 10 illustrates, the even-numbered input signals that are latched into the latches C10, C54, C32 and C76 should be those that bypass the adders and the square root of two resolving multiplier. The odd-numbered input signals, however, must first be paired to form the paired inputs p(n), and the signal Y1 must be multiplied by the square root of two. The control signal SEL.sub.-- P is activated in order to select the paired input signals. Hence, these signals are used to control gates that act as multiplexers to let the correct signals pass to the output latches of the precommon block PREC 231.
As discussed previously, not having to arrange the inputs in strictly ascending order leads to a simplified `butterfly` bus structure with high interconnection efficiency. As also described, the odd inputs are preferably applied as a group to the pre-common block first, followed by the even-numbered inputs, but any order may be used within each odd or even group, i.e., any order of inputs may be used, however, suitable latch arrangements as separately provided to process the odd-numbered inputs, or at least are provided in separate regions of the circuit.
The supervisory control circuitry also generates timing and control signals for the post-common block POSTC 233. These control signals are as follows:
EN.sub.-- BH, EN.sub.-- GH: Referring again to FIG. 9, the outputs from the common block CBLK 232, after processing of the odd-numbered inputs, are shown as H0, H1, H3, and H2. These signals are then sent to the coefficient multipliers, d1, d3, d7, d5, respectively, in the first post common block POSTC1 233. The signal EN.sub.-- BH is used to enable latches that hold the g0 to g3 values, as well as to enable the latches that hold the h0 to h3 values after they have been multiplied in the coefficient multipliers.
ADD, SUB: As FIG. 10 illustrates, the embodiment includes a bank of resolving adders/subtractors that sum and difference(k) and h(k) values in order to form the low-order outputs, respectively. The signals ADD, SUB are used to set the resolving adders/subtractors in the addition and subtraction modes, respectively. EN.sub.-- 0: This signal is used to enable output latches that latch the results from the resolving adders/subtractors.
MUX.sub.-- OUT70, MUX.sub.-- OUT61, MUX.sub.-- OUT43, MUX.sub.-- OUT52: In accordance with the present invention, the output data from the system is preferably transmitted over a single 22-bit output bus, so that only one output value (X0 to X7) is transferred at a time. These signals are activated sequentially to select which of the four latched output values is to be latched into a final output latch. Accordingly, these signals thus act as the control signals for a 4-to-1 multiplexer.
T.sub.-- OUT[21:0]: This label indicates the 22-bit output signal from the post-common block POSTC 233.
The output signals from the pre-common block PREC 231 are latched to form the input signals to the common block CBLK 232. As shown in FIG. 11, the output signals from the pre-common block PREC 231 are presented as the four 22-bit data words Cl10[21:0], Cl54[21:0], Cl32[21:0], Cl76[21:0], which become the input signals IN[0], IN[1], IN[3], IN[2], respectively, to the common block CBLK 232.
As FIG. 11 shows, the four 22-bit results from the common block CBLK 232 are transferred in parallel as output signals OUT0[21:0], OUT1[21:0], OUT3[21:0], OUT2[21:0], which are then latched as the input signals of the post common block POSTC 233 as CO70[20:1], CO61[21:0], CO43[21:0], CO52[21:0].
One should take particular note that no control signals are required for the common block CBLK Because of the unique structure of the IDCT system in this example, the common block of the system's operations can be performed as pure logic operations, with no need for clock, timing or control signals. This further reduces the complexity of the device. One should also note that in certain applications (particularly those in which there is plenty of time to perform all needed arithmetic operations) the pre-common and post-common blocks PREC 231, POSTC 233 may also be arranged to operate without clock timing or control signals.
FIG. 12 is a block diagram of the pre-common block PREC 231 of the present invention. In this and following Figures, the notation `S1[a], S2[b], . . . , SM[Z]`, where S is an arbitrary signal label and a, b, . . . , z are integers within the range of the signal's bus width, indicates that the selected bits a, b, . . . , z from the signals S1, S2, . . . , SM are transferred in parallel over the same bus, with the most significant bits (MSBs) being the selected bits `a` of the signal S1, and the least significant bits (LSBs) being the selected `z` of signal SM. The selected bits do not have to be individual bits, but rather, entire or partial multi-bit words may also be transmitted along with other single bits or complete or partial multi-bit words. In the Figures, the symbol S will be replaced by the corresponding signal label.
For example, in FIG. 12, a square root of two multiplier is shown as R2MUL. The `save`; or `unresolved sum` output from this non-resolving multiplier is indicated as the 21-bit word M5S[20:0], similarly, the `carry` output from the multiplier R2MUL is shown as the 22-bit word M5C[20:0], which is transferred over the bus to the `b` input of a carry-save resolving adder M5A. (Recall that a `0` is inserted as an MSB to the least significant 21 bits of the save output, however, this is accomplished before being applied to the `a` input of the resolving adder M5A. This is indicated in FIG. 12 by the notation GND.M5S[20:0]). In other words the conductor corresponding to the MSB input to the adder M5A is forced to be a `0` by tying it to ground GND.
In order to understand why a `0` is inserted as the 22'nd bit of the `sum`, observe that if the partial sum of a multiplication is n places wide, the carry word is shifted one place to the left relative to the partial sum. The carry word, therefore, extends to n+1 places with a valid data bit in the n+1'th position with an `0` in the least significant position (since there is nothing before this position to produce a carry bit into the units position). If these two words are used as inputs to a resolving binary adder, care must be taken to ensure that the bits (digits) of the carry word are properly aligned with the corresponding bits of the partial sum. This also ensures that the decimal point (even if only implied, as in integer arithmetic) is kept `aligned` in both words. Assuming the inputs to the adder are n+1 bits wide, a `0` can then be inserted into the highest-order bit of all n-bit positive partial sum words to provide an n+1 bit input that is aligned with the carry word at the other input.
As is described above previously, the four inputs that are processed at a given time in the pre-common block PREC 231 are transferred over the input bus T.sub.-- IN(21:0). This input bus is connected to the inputs of four input latches IN10L, IN54L, IN32L, AND IN76L. Each respective latch is enabled only when the input clock signal IN.sub.-- CLK and the corresponding latch selection signal LATCH10, LATCH54, LATCH32, LATCH76 are high. The four inputs can, therefore, be latched into their respective input latches in four periods of the IN.sub.-- CLK signal by sequential activation of the latch enabling signals LATCH10, LATCH54, LATCH32, and LATCH76. During this time, the LATCH signal should be low (or on a different phase) to enable the input latches IN10L, IN54L, IN32L, and IN76L to stabilize and latch the four input values.
An example of the timing of the latches, in accordance with the present invention, is illustrated in FIG. 13. Once the four input signals are latched in the preferred order, they are passed to a second bank of latches L10L, L54L, L32L, L76L. These second bank of latches are enabled when the signals OUT.sub.-- CLK and LATCH are high. This signal timing is also illustrated in FIG. 13.
Note that the system of the present invention does not have to delay receipt of all eight input words. Once all the even or odd input words are received and latched in IN10L, IN54L, IN32L and L76L, this frees the In latches, which can then begin to receive the other four input signals without delay at the next rising edge of IN.sub.-- CLK.
The 2-digit suffix notation [10, 54, 32, 76] used for the various components illustrated in the Figures indicates that odd-numbered signals are processed first, followed by the even-numbered signals on a subsequent pass through the structure. As is mentioned above, this order is not required by the present invention, and it will be appreciated by one of ordinary skill in the art that additional orders may be used.
Once the four input signals are latched in proper order in the second set of latches L10L, L54L, L32L, L76L, the corresponding values are either passed as inputs to output latches C10L, C54L, C32L and C76L on activation of the selected bypass signal SEL.sub.-- BYP, or they are passed as paired and multiplied inputs to the same output latches upon activation of the `select p` signal SEL.sub.-- P. In other words, all signals are passed, both directly and indirectly, via arithmetic devices, to the output latches C10L, C54L, C32L, C76L of the pre-common block PREC 231. The proper values, however, are loaded into these latches by activation of the `select bypass` signal SEL BYP (for even-numbered inputs Y0, Y2, Y4, and Y6) or the "select p" signal SEL-P (for the odd-numbered inputs Y1, Y3, Y5 and Y7). As will be appreciated by one of ordinary skill in the art, the desired timing and order of these and other control signals is easily accomplished in a known manner by proper configuration and/or [micro-] programming of the controller CNTL 241.
The uppermost input value at the output of latch L10L is passed first to the square root of two-multiplier R2MUL and then to the resolving adder M5A as indicated. The output from the resolving adder M5A is shown as an equivalent of the resolved multiplication of the output from the latch L10L by the square root of two. The outputs from the other three latches L54L, L32L, L76L are also transferred to corresponding output latches C54L, C32L and C76L, respectively, both directly via 22-bit latch buses LCH54[21:0], LCH32[21:0] LCH76[21:0] and indirectly to the output latches via resolving adders P2A, P1A and P3A, respectively.
In the present invention, each resolving adder P2A, P1A, P1A has two inputs "a" and "b". For adder, P2A, the one input is received from the latch L32L, and the other input is received from the latch L54L. For input values Y5 (latched in L54L) and Y3 (latched in L32L), the output from the adder P2A will, therefore, be equal to Y5+Y3, which, as is shown above, is equal to p(2). Hence, the adders "pair" the odd-numbered inputs to form the paired input values p(1), p(2) and p(3). Of course, the even-numbered input signals latched in L54L, L32L, and L76L will also pass through the resolving adders P2A, P1A and P3A, respectively, however, the resulting p "values" will not be passed to the output latches C54L, C32L and C76L because the "select p" signal SEL P will not be activated for even-numbered inputs.
The values that are latched in the output latches C10L, C54L, C32L and C76L upon activation of the input clock signal IN.sub.-- CLK will therefore be equal to either the even-numbered inputs Y0, Y2, Y4, Y6 or the paired input values P0, P1, P2, P3 for the odd-numbered inputs. One should recall that the input Y(1) is "paired" with the value U(-1), which is assumed to be zero. As illustrated in FIG. 12, this assumption is implemented by not adding anything to the value Y1. Instead, Y1 is only multiplied by the square root of two as is shown in FIGS. 9 and 10.
FIG. 14 illustrates the preferred architecture of the common block CBLK 232, in accordance with the present invention. Because of the various multiplications and additions in the different system blocks, it is necessary or advantageous to scale down the input values to the common block before performing the various calculations. This ensures a uniform position for the decimal point (which is implied for integer arithmetic) for corresponding inputs to the various arithmetic devices in the system.
Accordingly, the input values IN0[21:0] AND IN1[21:0] are accordingly scaled down by a factor of four, which corresponds in digital arithmetic to a right shift of two bits. In order to preserve the sign of the number (keep positive values positive and negative values negative) in binary representation, the most significant bit (MSB) must then be replicated in the two most significant bits of the resulting right-shifted word; this process is known as "sign extension". Hence, the input value IN0 is downshifted by two bits with sign extension to form the shifted input value indicated as IN[21], IN0[21], IN0[21:2]. The input value IN1[21:0] is similarly sign-extended two places. The input IN2 is also shifted and extended to form IN2[21], IN2[21:1]. These one-position shifts correspond to truncated division by a factor of two.
As shown in FIG. 10, the input IN2, IN3 are those which must be multiplied by the scaled coefficients c1s and c3s. Each input IN3 and IN2 must be multiplied by each of the scaled coefficients. As FIG. 14 illustrates, this is implemented by the four constant-coefficient carry-save multipliers MULC1S, MULNC1S, MULC3S3, and MULC2S2. One should note that the bottom multiplier for IN2 is an inverting multiplier MULC1S, that is, its output corresponds to the negative of the value of the input multiplied by the constant C1S. Therefore, the value latched in C76 is subtracted from the value latched in C32 (after multiplication by C3S). By providing the inverting multiplier MULNC1S, subtraction is implemented by adding the negative of the corresponding value, which is equivalent to forming a difference. This allows the use of identical circuitry for the subsequent adders, while allowing a non-inverting multiplier may be used with a following subtractor.
In the illustrated embodiment of the present invention, four cosine coefficient multipliers MULC1S, MULNC1S, MULC2S3, and MULC3S2 are included. If arrangements are made for signals to pass separately through the multipliers, however, the necessary multiplications can be implemented using only two multipliers one for the c1s coefficient and one for the c3s coefficient.
In accordance with the present invention, the multipliers for MULC1S, MULNC1S, MUL3S3 and MULC3S2 are preferably of the carry-save type, which means that they produce two output words, one corresponding to the result of the various rows of additions performed within a hardware multiplier, and another corresponding to the carry bits generated. The outputs from the multipliers are then connected as inputs to either of two 4-input resolving adders BT2, BT3.
For ease of illustration only, five of the output buses from the multipliers are not drawn connected to the corresponding input buses of the adders, as will be appreciated by one of ordinary skill in the art, these connections are to be understood, and are illustrated by each respective output and input having the same label. Hence, the save output M1S[20:0] of the multiplier MULC1S is connected to the lower 21 bits of the "save-a" of the adder BT3.
As shown in FIG. 14, five of the inputs to the adders BT2 and BT3 are shown as being "split". For example, the "ca" input of the adder BT2 is shown as having IN3[21] over M3C[20:0] being input as the least significant 21 bits. Similarly, the "sa" (the "save-a" input) of the same adder is shown as being GND, GND over M3S[19:0]. This means that two zeros are appended as the two most significant bits of this input word. Such appended bits ensure that the proper 22-bit wide input words are formed with the proper sign.
The carry-save adders BT2 and BT3 add the carry and save words of two different 22-bit inputs to form a 22-bit output save word T3S[21:0] and a 21-bit output carry word T3C[21:1]. Accordingly, the input to each adder is thus 88 bits wide and the output from each adder is 43 bits wide. As FIG. 10 illustrates, the output from the latch C10 is combined with the output from the latch C54 in the upper-most data path before addition with the output from the carry-save adder BT3. The "combination" is not, however, necessary until reaching the following adder in the upper data path. Consequently, as FIG. 14 shows, the shifted and sign-extended input value IN0 is connected to the upper carry input.
The upper carry input of adder CS0 is connected to the shifted and sign-extended input value IN0, and the shifted and sign-extended input IN1 is connected as the upper save input of the same adder. In other words, IN0 and IN1 are added later in the adder CS0.
The designation "dummy" adder/subtractor 240 used in FIG. 10, therefore, indicates which operation must be performed, although it does not necessarily have to be performed at the point indicated in FIG. 10. Similarly, the lower dummy subtractor 240 shown in FIG. 10 requires that the output from latch C54 be subtracted from the output from latch C10. This is the same as adding the output from C10 to the complement of the output of C54.
Referring once again to FIG. 14, the complement of the input IN1 (corresponding to the output of latch C54 in FIG. 10) is performed by a 22-bit input inverter IN1[21:0] (which generates the logical inverse of each bit of its input, bit-for-bit). The complement of IN1 value--NlN1[21:0]--is passed to the upper "save" input of the adder CS1, with the corresponding upper "carry" input being the shifted and sign-extended IN0. The upper portion of the adder CS1, therefore, performs the subtraction corresponding to IN0 minus IN1.
In the lower two data paths shown in FIG. 11, resolving subtractors are used instead of the resolving adders shown in the upper two data paths at the output of the common block CBLK 232. Each resolving adder or subtractor is equivalent to a carry-save adder or subtractor followed by a resolving adder. This is shown in FIG. 14. Subtractors CS2 and CS3 have as their inputs the processed values of IN0 to IN3 according to the connection structure shown in FIG. 10.
The 22-bit carry and save outputs from each of the adders/subtractors C20-CS3 are resolved in the resolving adders RES0-RES3. As will be appreciated by one of ordinary skill in the art, resolution of carry and save outputs is well understood in the art of digital design and is, therefore, not described in greater detail here. As FIG. 14 illustrates, the save outputs the carry-save adders/subtractors CS0-CS3 are passed directly as 22-bit inputs to the "a"-input of the corresponding resolving adders RES0-RES3.
As is also well known in the art, the 2's-complement of a binary number is formed by inverting each of its bits (changing all "1's" to "0's" and vice versa) and then adding "1". Note that the "1" can be added immediately after the bit inversion, or later. The LSB of a carry word will always be a "0" which is implemented in the illustrated embodiment of the present invention by tying the LSB of the carry words O0C and O1C to ground GND as they are input to the resolving adders RES0 and RES1, respectively. The addition of "1" to the carry outputs of the subtractors CS2 and CS3 to form 2'S-complemented values, however, is implemented by tying the LSB of these data words O2C and O3C to supply voltage VDD, thus "replacing" the "0" LSB of the carry word by a "1", which is equivalent to addition by "1".
For the reasons provided above, a "0" is appended as the LSB to the 21-bit carry words from the carry-save adders Cs0 and CS1 (by tying the LSB to ground GND) and the LSB of the carry words from the carry-save subtractors CS2 and CS3 is set equal to "one" by tying the corresponding data line to the supply voltage VDD. The resolving adders RES0-RES3, therefore, resolve the outputs from the adder/subtractors CS0-CS3 to form the 22-bit output signals OUT0[21:0]-OUT3[21:0].
Two advantages of the IDCT circuitry according to the embodiment of the present invention can be seen in FIG. 14. First, no control or timing signals are required for the common block CBLK 232. Rather, the input signals to the common block are already processed in such a way they can be applied immediately to the pure-logic arithmetic devise in the common block 232. Second, by proper scaling of the data words, integer arithmetic can be used throughout (or, at least, decimal point for all values will be fixed). This avoids the complexity and slowness of floating-point devices, with no unacceptable sacrifice of precision.
Yet another advantage of the embodiment of the present invention is that, by ordering the inputs as shown, and by using the balanced decimated method in accordance with the present invention, similar design structures can be used at several points in the silicon implementation. For example, as shown in FIG. 14, the constant coefficient multipliers MULC1S, MULC3S3, MULC3S2 and MULNC1S all have similar structures and receive data at the same point in the data path, so that all four multipliers can be working at the same time. This eliminates "bottlenecks" and the semiconductor implementation is, therefore, able to take full advantage of the duplicative, parallel structure. The carry-save adders BT2 and BT3 similarly will be able to work simultaneously, as will the following carry-save adders and subtractors. This symmetry of design and efficient simultaneous utilization of several devices is common throughout the structure according to the embodiment of the present invention.
FIG. 15 shows the preferred arrangement of the post-common block POSTC 233 in accordance with the present invention. As FIG. 10 shows, the primary functions of the post-common POSTC 233 are to form the h0 to h3 values by multiplying the outputs of the common block by the coefficients d1, d3, d5 and d7; to add the g(k) and h(k) values to form the low order outputs; and to subtract the h(k) values from the corresponding g(k) values to form the high-order outputs. Referring now to both FIG. 10 and FIG. 15, the post-common block POSTC 233 latches the corresponding outputs from the common block CBLK 232 into latches BH0L, BH1L, BH3L and BH2L when the Bh latches are enabled, the control circuitry sets the EN.sub.-- BH signal high, and the output clock signal OUTC.sub.-- CLK signal goes high. The g(k), g0 to g3 values are latched into corresponding latches G0L, G1L, G3L and G2L when the control circuitry enables these latches via the signal EN.sub.-- GH and input clock signal IN.sub.-- CLK goes high.
The processed odd-numbered inputs, that is, the values h0 to h3, are latched into latches H0L, H1L, H3L and H2L when the EN.sub.-- GH and IN.sub.-- CLK signals are high, via the constant coefficient multipliers D1MUL, D3MUL, D5MUL and D7MUL. These multipliers multiply, respectively by d1, d3, d5 and d7. In the preferred embodiment, these constant-coefficient multipliers are preferably carry-save multipliers in order to simplify the design and to increase calculation speed. As FIG. 15 illustrates, the "carry" ("c") outputs from the constant coefficient multipliers are connected, with certain changes described below, to the a inputs of resolving adders H0A, H1A, H3A and H2A. The "save" ("s") outputs from the coefficient multipliers are similarly, with certain forced changes described below, connected to other input of the corresponding resolving adder.
As FIG. 15 further illustrates, the LSB of the H0 signal is preferably forced to be a "1" by tying the corresponding "save" output for H0 is set to 0 (tied to ground GND), and the second bit (corresponding to H0S[1]) is set to "1". The data words from the carry and save outputs of the constant-coefficient multiplier D3MUL are similarly manipulated an input to the resolving adder H1A. The advantage of these manipulations and their input to the resolving adder H1A.
In accordance with the present invention, all 22-bits of the carry output from the coefficient multipliers D7MUL and D5MUL are connected directly to the "a" input of corresponding resolving adders H3A and H2A. The MSB of each multipliers "save" output, however, is forced to "0" by tying the corresponding data line to ground GND.
The IDCT system described was tested against the CCITT specification described above. Because of the scaling and other well-known properties of digital adders and multipliers, some precision is typically lost in the 10,000 sample, but run that forcing the various bits described above to either "0" or "1" reduced the expected error of the digital transformation. As a result of the bit manipulation of the data words, the embodiment of the present invention achieved acceptable accuracy under the CCITT standard using only 22-bit wide data words, whereas 24 bits would normally be required to produce equivalent accuracy.
Because of limited precision, and truncation and rounding errors, there is typically some inaccuracy in every data word in an IDCT system. However, forcing selected bits of a data word it was discovered that the error thereby systematically introduced into a particular data word at a particular point in the hardware yielded statistically better overall results. Bit-forcing may also be applied "within" a multiplication, for example, by selectively forcing one or more carry bits to predetermined values.
In the present invention, the bit-forcing scheme need not be static, with certain bits always forced to take specified values, but rather a dynamic scheme may also be used. For example, selected bits of a data word may be forced to "1" or "0" depending on whether the word (or even some other data) is even or odd, positive or negative, or above or below a predetermined threshold, and the like.
Normally, only small systematic changes will be needed to improve overall statistical performance. Consequently, according to this embodiment of the present invention, the LSB's of selected data words (preferably one bit and one data word at a time, although this is not necessary) are forced to be a "1" or a "0". The CCITT test is run, and the CCITT statistics for the run are compiled. The bit is then forced to the other of "1" or "0", and the test is rerun. Then the LSB (or LSBs) of other data words are forced to "1" or "0", and similar statistics are compiled. By examining the statistics for various combinations of forced bits in various forced words, a best statistical performance can be determined.
If this statistically based improvement is not required, however, the outputs from the constant-coefficient multipliers D1MUL, D3MUL, D5MUL and D7MUL may be resolved in the conventional manner in the resolving adders H0A-H3A. The lower 21-bits of the input of the corresponding latches H0L-H3L, with the LSB of these inputs tied to ground.
The outputs from the H-latches (H0L-H3L) and the G-latches (G0L-G3L) pairwise form the respective a and b inputs to resolving adder-subtractors S70A, S61A, S43A and S52A. As was indicated above, these devise add their inputs when the ADD signal is high, and subtract the "b" input from the "a" input when the subtraction enable signal SUB is high. The second bits of the upper two latch pairs H0L, G0L, H1L and G1L are manipulated by multiplexing arrangements in a manner described below.
The outputs from the resolving adder-subtractors S70A, S61A, S43A and S52A are latched into result latched R70L, R61L, R43L, R52L.
As depicted in FIG. 15b, the input words to the adder/subtractor S70A and dS61A, in accordance with the present invention, have the second bits of each input word manipulated. For example, the second bit of the input word to the "a"-input of the adder subtractor S70A is G0[1M], G0[1M], G0[0]. In other words, the second bit is set to have the value G01M. The second bits of the other inputs to the adder/subtractors S70A and S61A are similarly manipulated. This bit manipulation is accomplished by four 2:1-bit multiplexers H01MUX, G01MUX, H11MUX and G11MUX (shown to the right in FIG. 15b). In the present invention, these multiplexers are controlled by the ADD and SUB signals such that the second bit (H01M, G01M, H11M, and G11M) is set to one if the respective adder subtractor S70A, S61A is set to (ADD is high), and the second bit is set to its actual latch output value if the SUB signal is set too high. Setting of individual bits in this manner is an easily implemented high-speed operation. The preferred embodiment, therefore, includes this bit-forcing arrangement since, as is described above, statistical analysis of a large number of tests pixel words has indicated that more accurate results are thereby obtained. It is not necessary, however, to manipulate the second bits in this manner, although it gives the advantage of smaller word width.
The four high or low-order results are latched in the output latches R70L, R61L, R43L and R52L. The results are sequentially latched into the final output latched OUTF under the control of the multiplexing signals MUX.sub.-- OUT70, MUX.sub.-- OUT61, MUX.sub.-- OUT43, MUX.sub.-- OUT52. Hence, the order in which resulting signals are output can therefore be controlled simply by changing the sequence with which they are latched into the latch.
The relationship between the clock and control signals in the post-common block POSTC 233 is shown in FIGS. 13b and 13c.
As was discussed previously, two 1-dimensional IDCT operations may be performed in series, with an intervening transposition of data, in order to perform a 2-D IDCT. The output signals from the post-common block POSTC 233, are therefore, according to this embodiment of the present invention, first sorted in a known manner column-wise (or row-wise) in a conventional storage unit, such as a RAM memory circuit (not shown), and are then read from the storage unit row-wise (column-wise) so as to be passed as inputs to a subsequent pre-common block and for processing as described above in this block, and in a common block CBLK 232, and a post-common block POSTC 233.
Storing by row (column) and reading out by column (row) performs the required operation of transposing the data before the second 1-D IDCT. The output from the second POSTC 233 will be the desire, 2-D IDCT results and can be scaled in a conventional manner by shifting to offset the scaling shifts carried out in the various processing blocks. In particular, a right shift by one position will perform the division by 2 necessary to offset the two square root of two multiplications performed in the 1-D IDCT operations.
Depending on the applications, this second IDCT structure (which is preferably identical to that shown FIG. 11) is preferably a separate semiconductor implementation. This avoids the decrease in speed that would arise if the same circuits were used for both transforms, although separate 1-D transform implementations are not necessary if the pixel-clock rate is now sufficient such that a single implementation of the circuit will be able to handle two passes in real time.
As shown in FIGS. 16 through 38, a second preferred embodiment, in accordance with the present invention, uses a single one-dimensional transform. This embodiment does not require a lowering of the pixel-clock rate as discussed previously.
The existing "resolving-adders" in the first preferred embodiment have been changed to "fast-resolving-adders". As seen in FIG. 38, these have been titled, "Fast Resolving Adders". This change has the effect of allowing more time for each datapath arithmetic block to act on its data inputs. The existing "latches" in the first preferred embodiment have been changed to 2-phase "flip-flops" or "registers".
The latching memory elements located on the front and end of the existing 1D IDCT datapath pipelines have been combined into single blocks, as shown particularly in particular in FIG. 18. Additionally, the amount of memory elements present at the input and the output of the second preferred embodiment has been increased to allow variable amounts of T2 data to be buffered.
As shown in FIGS. 16 and 17, the two data streams, stream "T1" (raw unoperated upon data) and stream "T2" (data which has been through the 1D IDCT once and has been transposed in the TRAM), are introduced into the datapath pipeline in a time multiplexed fashion.
In the present invention, each stream takes its turn to introduce a group of data items into the datapath pipeline. The data streams are "interleaved" as they pass sequentially down the datapath pipeline and are "de-interleaved" at the datapath output, as shown in FIGS. 17, 18 and 33. A group can vary in number, but in this example, they are eight bits.
In accordance with the present invention, Ti must not be stalled. If T2 arrives at the point of interleaving with T1, but the input buffer should not introduce its data into the pipeline because this would clash with the T1 stream, then stream T2 provides an extra buffering so that T2 does not stall the data stream, but instead will buffer up data from its input stream until such a time as it may safely interleave with stream T1. This is shown in FIGS. 19 and 33 where the data from stream T1 is being loaded into the first transform in latches 0-7, using signals, "Latch 1(0) `through` Latch 1(7)". Additionally, data from T2 is being loaded in "Latch 2(0) `through` Latch 2(15)", as shown in FIG. 19, using signals shown in FIG. 33.
The interleaving is controlled by "T1 OK2 insert" and "T2 OK2 insert" signals. Under normal operation, the interleaving will occur when the signals go high. However, if the appropriate amount of data in the latch for T2 has not yet been reached when "T2 OK insert" goes high, then the latch will miss its opportunity and must continue buffering data until the next opportunity to insert data occurs.
In summary, if the above described buffering, in accordance with the present invention, is to occur, comparable "slippage" has to occur at the output of T2. T2 slips when it misses its data insertion point and has to continue buffering in the latches shown in FIG. 19. If T2 slipped and did not introduce data into the pipeline there will be a corresponding gap in the T2 stream output at the datapath output. This gap may be removed or "swallowed up" by use of the extra buffering at the T2 output. This process may be thought of as having a "fixed" T1-1D IDCT transform with a variable T2-1D IDCT, where the data streams are interleaved in a time multiplex fashion such that they may use the same piece of arithmetic datapath pipeline.
In the present invention, "Recovery" takes place when non-data enters T1. It is an opportunity for the T2 buffer to catch up to T1 and the datastream. Non-data is a data type that bypasses the IDCT and is shown as a data spike in "Latch 2 [.phi.]" of FIG. 34. This eventually makes its way to T2 input, which allows the T2 buffering to fill up at the output. Recovery is shown in FIG. 33 and FIG. 25 when the "T2 dout" signal and the "out" signal are gapped by a number of cycles. The gap is used as a reference to fix the data stream. It should be noted that the gap in cycles between these two signals is the same as the gap of buffering when the latch for T2 was waiting to insert its data.
Following the TRANSFORM in POSTC 233 part B, the interleaved stream is de-interleaved into "T2 out", as shown in FIGS. 18 and 23. The "T2 out" data stream has slip gaps in the data as described above. The T2 out [143:.phi.], shown in FIG. 17, enters a 16 to 1 multiplexor block, shown as block "IDDPMUX" in FIG. 17. This multiplexor block will select data from one of 16 positions in the output buffer block, as shown in FIG. 25. This position is selected by the control logic, shown in FIG. 29, which uses the gap by which T2 "buffered-up" at its input. This gap is used as a reference. The output stream, T2DOUT, from the multiplexer block is the "fixed" data stream.
In range tests carried out on an embodiment of the present invention for the IDCT arrangement described above, it was found that all intermediate and final values were kept well within a known range at each point while still meeting the CCITT standards. Because of this, it was possible to "adjust" selected values as described above by small amounts (for example, by forcing certain bits of selected data words to desired values) without any fear of overflow or underflow in the arithmetic calculations.
The method and system, in accordance with the present invention, can be varied in numerous ways. For example, the structures used to resolve additions or multiplications may be altered using any known technology. Thus, it is possible to use resolving adders of subtractors where the preferred embodiment uses carry-save devices with separate resolving adders. Also, the preferred embodiment of the present invention uses down-scaling at various points to ensure that all values remain within their acceptable ranges. Down-scaling is not necessary, however, because other precautions may be taken to avoid overflow or underflow.
In one embodiment of the present invention, certain bits of various data words were manipulated to reduce the required word width within the system. However, the various intermediate values may, of course, be passed without bit manipulation. Furthermore, although only data words were bit-manipulated in the illustrated example of the present invention, it is also possible to manipulate the bits of constant coefficients as well and evaluate the results under the CCITT standard. If a comparison of the results showed that it would be advantageous to force a particular bit to a given value, in some cases, on might then be able to increase the number of "zeros" in the binary representation of these coefficients in order to decrease further the silicon area required to implement the corresponding multiplier. Once again, bit manipulation is not necessary.
In summary of the above aspects of the present invention, the following is disclosed: an apparatus for transforming data having a first latch defining a first data stream source and a second latch defining a second data stream source. The first and second latches are in communication with a single arithmetic unit. The arithmetic unit communicates data to a transpose RAM, the transpose RAM transposes the data and communicates it to the second latch. The second latch is adjustable and can be varied in size to accommodate variable rates of data being received and transmitted. The second latch and first latch communicate 1st and 2nd data stream to the arithmetic unit sequentially, however, the sequential communication of the second latch does not interrupt the communication from the first latch. In this manner, common arithmetic unit is used for a first and second data stream. Furthermore, a process for transforming data using a common arithmetic unit having the following steps is described. First, loading the data into a first latch and, upon reaching a predefined number of cycles transmitting the data to an arithmetic unit and loading a first marker bit into a control shift register. Next, loading data into a second latch, the second latch is adjustable and can be varied in size to accommodate variable rate of data being received and transmitted at different rates. The next step is to transmit the data in the second latch to the arithmetic unit when the first control shift register reaches a predetermined state and the second latch is filled with a predetermined amount of data. Next, preventing transmission of data from the second latch, if the second latch is not filled with a predetermined amount of data and then recovering the second latch when the first latch is receiving non data.
Detailed Description of Invention for Time Synchronization
In MPEG-2, video and audio data is synchronized using information carried in the MPEG-2 systems stream. In this regard, there are essentially two types of information that deal with synchronization; clock references and time stamps. Clock references are used to inform the decoder what number is used to represent the time "now". This is used to initialize a counter that is incremented at regular intervals so that the decoder always knows what the current time is.
Time stamps are carried in some of the streams of data that are used to make up the programme (typically video and audio). In the case of video, a time stamp is associated with a picture and tells the decoder at what "time" (defined by the counter that was initialized by the clock reference) a picture should be displayed.
In MPEG, multiplexed into the system stream are a series of clock references. These clock references define the "system time". There are two types of clock reference; Program Clock References (PCRs) and System Clock References (SCRs). In the present invention, the distinction between PCRs and SCRs is not relevant since each of the clock references are used in the same manner by the decoder. PCRs and SCRs have timing information to a resolution of 90 kHz with a further field extending the resolution to 27 MHz (or 1/27.times.10e6 in seconds). Clock references are included in the data stream fairly often in order that "system time" may be reinitialized after a random access or channel change.
Accordingly, it is important to appreciate that timestamps refer to a hypothetical model of a decoder that can decode pictures instantly. As will be appreciated by one of ordinary skill in the art, any real decoder cannot do this and must take steps to modify the theoretical time in which pictures should be displayed. Furthermore, time stamps and the clock references are used to determine display time and errors in display time. This modification depends upon the details of the architecture of the particular decoder. Clearly any delay introduced by the video decoder must be matched by an equivalent delay in the audio decoder.
When decoding MPEG, discontinuities in the concept of "system time" may occur. For instance in an edited bitstream, each edit point will have discontinuous time. A similar situation occurs at channel change. It will be appreciated that care must be taken when using time stamps, because using a time stamp that was encoded in one time regime with respect to a "system time" defined by a clock reference from another regime will clearly lead to incorrect results.
FIG. 39 shows the demultiplexing of the MPEG systems stream into elementary streams 250. Each elementary stream will typically carries either video or audio data although, in general, any form of data may be transported. Each elementary stream is divided into a series of access units. In the case of video, the access unit is a picture. In the case of audio, it is a fixed number of samples of audio data.
Also multiplexed into the systems stream are a series of clock references. These clock references define the "system time".
In accordance with the present invention, associated with each elementary stream is a series of time stamps 251. The time stamps specify the "system time" at which the next access unit for the respective elementary stream is to be presented. These time stamps are referred to as presentation time stamps, "PTS".
In the case of video data, a second type of time stamp is also defined is referred to as a decode time stamp, "DTS". Since the DTS is only present when a PTS is also present and there is a simple relationship between them, the detailed differences between these two types of timestamps can be ignored since PTS/DTS differences have no bearing on the present invention.
The decode time stamps (DTS) define the time at which an access unit (picture in the case of video) is to be decoded. The presentation time stamps (PTS) define the time at which an access unit is to be presented (displayed). However, the timing model used is a hypothetical model in which the decoder is infinitely fast. In this case, the DTS and PTS would be identical to one another.
However, in MPEG video decoding, some of the pictures are reordered. Therefore, after decoding, the pictures are held in storage for a time period, e.g., several frame times, before they are displayed. During this time period, other pictures that are decoded subsequent to the picture in question are displayed. Consequently, for these reordered pictures there is a difference between the DTS and PTS.
In accordance with the present invention, it will be appreciated that to properly synchronize time, it is necessary to be consistent in the use of time stamps. In one preferred embodiment, the time synchronizing circuitry is placed at a point in the decoding pipeline when the pictures occur in their decoded order. Accordingly, this embodiment uses the DTS.
Nevertheless, the circuitry could equally be moved to a point in the decoding pipeline that occurs after the pictures are reordered and, therefore, the pictures would reach the synchronizing circuitry in their display order. Hence, as will be appreciated by one of ordinary skill in the art, PTS would be used in this embodiment.
In the preferred embodiments of the present invention, the information derived from the timestamps is transported through the various circuits by means of tokens. Tokens consist of a series of one or more words of information. The first word of the token contains a code which identifies the type of token and, hence, the type of information carried by that token. Associated with each word of the token is an extension bit which is set to one to indicate that there are more words in the current token. Therefore, the last word of a token is indicated by the extension bit being zero. In the present invention, the code in the first word indicating the type of token may be of a variable number of bits so that some codes use a small number of bits (allowing the remainder of the bits in the first word to be used to represent other information) while other codes use a larger number of bits.
Tokens may be characterized as being either control or DATA tokens. For example, at the interface between the system decoder and the video decoder, there are two types of information: (1) the coded video data and (2) the synchronization time derived from the time stamp information. The coded video data is viewed as data and is carried in a DATA token (e.g., the token called DATA) while the synchronization time is viewed as control information and is carried in a control token (called SYNC.sub.-- TIME). Additional control tokens may also be used from time to time in the present invention. For example, a FLUSH token that behaves in a manner similar to a reset signal may be required to initialize the video decoding circuitry before attempting to restart decoding because of an error.
In accordance with the present invention, it is an object of one preferred embodiment to time synchronize two circuits and, more particularly, to time synchronize two circuits without directly communicating system time from the first to the second circuit. In accordance with the invention, time synchronization of two circuits is accomplished without passing system time directly to the second circuit by providing synchronized time counters in each circuit.
The present invention also enables the system to time synchronize two circuits without communicating system time from the first to the second circuit by providing an elementary stream time counter in each circuit.
Accordingly, another object of the present invention is to time synchronize two circuits and to determine the presentation time error, if any, of the object being presented by using time stamp information, system time, and elementary stream time from the first circuit to generate synchronization time passed to the second circuit and compared to a copy of elementary stream time in the second circuit which is synchronized with the elementary stream time in the first circuit. The system of the present invention can time synchronize a system decoder and a video decoder without directly communicating system time from the system decoder to the video decoder, without passing system time directly to the video decoder by providing synchronized time counters in each circuit and without communicating system time from the system decoder to the video decoder by providing a video counter in each circuit.
The invention also enables the system to time synchronize a system decoder and a video decoder and to determine the display time error, if any, of the picture being displayed by using video time stamp information, system time, and video decoding time from the system decoder to generate synchronization time which is then passed to the video decoder and compared to a copy of video decoding time in the video decoder which is synchronized with the video decoding time in the system decoder.
In accordance with the present invention, information derived from the timestamps can be transported through the system using a control token as previously described.
FIG. 40 shows a first preferred embodiment implementing elementary stream timestamp management, in accordance with the present invention. The clock references 253, which represent system time, are decoded by the system demultiplexer 254 and placed initially, and then as needed, into a time counter 255 within the system decoder 256, and are incremented at 90 kHz. A second copy of the clock reference 253 is simultaneously loaded into the time counter 258 that is inside the elementary stream decoder 257, incremented also at 90 kHz, and synchronized to the time counter 255 in the system decoder 256.
The time stamps 251, in accordance with the present invention, flow from the system demux 254 through the elementary stream buffer 260 so that they are delayed by the same amount as the incoming data. The time stamps 251 may also have a correction added to compensate for the non-zero decode time of the elementary stream decoder 257. The corrected time stamps 251 are then compared with the copy of the time stored in the time counter 258 inside the elementary stream decoder 257 to determine whether the decoded information is presented too early or too late.
The above embodiment is better than merely passing system time directly to the elementary stream decoder 257 from the time counter 255 in the system decoder 256 because the counter in the system decoder changes 90,000 times a second. Therefore, system time would, in all essence, need to be continually passed to the elementary stream decoder 257. Passing system time continually would require dedicated pins or the like. By using a time counter 255 located in the system decoder 256 and a time counter 258 located in the elementary stream decoder 257, system time can be passed in the form of clock references 253 a few times a second.
Another embodiment is shown in FIG. 41. The embodiment shown in FIG. 41 avoids the need for the clock references 253 to be passed to the elementary stream decoder 257. This is achieved by using a second counter "es.sub.-- time" 262, containing information on elementary stream time, which is maintained in both the system decoder 256 and the elementary stream decoder 257. The two es.sub.-- time counters 262 and 263 are reset at power on, and at other times such as channel change, and then they free run from there on. Since this embodiment depends on the two es.sub.-- time counters 262 and 263 staying in step, it will be appreciated that it is necessary to take measures to ensure the es.sub.-- time counters do not get out of step. One way to ensure the es.sub.-- time counters 262 and 263 stay in step is to use carry out of the es.sub.-- time counter in the system decoder to reset the es.sub.-- time counter in the elementary stream decoder 257 as shown in FIG. 41.
As further shown in FIG. 41, the clock references 253, which represent system time, are decoded by the system demultiplexer 254 and placed into a time counter 255 within the system decoder 256 and incremented at 90 kHz. The es.sub.-- time counter 262 in the system decoder 256 of the present invention and the es.sub.-- time counter 263 in the elementary stream decoder 257 of the present invention are synchronized with each other and incremented at 90 kHz. Elementary stream time stamps are also decoded by the system demultiplexer 254. Accordingly, a synchronization value X is computed using the elementary stream timestamp, the system time contained in the time counter and the elementary stream time contained in the es.sub.-- time counter 262 contained in the system decoder 256 according to the equations 3-1.
The following set of equations 3-1 (a-d) is illustrative of one method in accordance with the present invention, for time synchronization which avoids passing the clock references 253 to the elementary stream decoder 257. Equation 3-1 (a) is the equation required for time synchronization. Since it is undesirable to pass system time directly to the elementary stream decoder circuit 257, as shown in FIG. 41, a synchronization time representation X is generated, using Equation 3-1 (b-d), by the system decoder 256 and this value is passed to the elementary stream decoder. Synchronization time X is then compared to the elementary stream time contained within the es.sub.-- time counter 263 located within the elementary stream decoder 257. Hence, the compared result is used to determine whether the decoded information is presented too early or too late and then is further used in time synchronizing the system.
Equations 3-1:
a) Time Synchronization=(Elementary stream timestamp-system time)
b) Time Synchronization=(X-elementary stream time)
c) (X-elementary stream time)=(elementary stream timestamp-system time)
d) X=(elementary stream timestamp-system time+elementary stream time)
In the present invention, the synchronization time, X, may have a correction added to compensate for the non-zero decode time of the elementary stream decoder 257. The corrected synchronization time is then compared with the elementary stream time contained in the es.sub.-- time counter 263 located inside the elementary stream decoder 257 to determine whether the decoded information is presented too early or too late and is further used to time synchronize the system. Note, the time correction could be subtracted from elementary stream time contained in the es.sub.-- time counter 263 located inside the elementary stream decoder 257 instead of added to synchronization time X for the same result. The above embodiment is an example of a solution for generating synchronization time X and determining whether the information is presented early or late. It will be apparent to those skilled in the art that there are many other equivalent solutions for accomplishing the above.
For example, FIG. 42 shows an alternative method for determining the synchronization time, X, in accordance with the present invention. In this arrangement, the system decoder 256 does not maintain an elementary stream time. Instead it records, in the register initial.sub.-- time 265, the value of system time at the instant that the elementary stream time counter, es.sub.-- time 263, located in the elementary stream decoder 257 is reset to zero. The value in es.sub.-- time 263 can be computed by the system decoder 256 because it will be the difference between the current system time and the value recorded in initial.sub.-- time.
The following equations 3-2 (a-c) is illustrative of this alternative method for time synchronization. Equation 3-2 (a) is the equation representing the value of the elementary stream time stored in es.sub.-- time 263 located in the elementary stream decoder 257. This is substituted into equation 3-1 (d) to give equation 3-2 (b) which is simplified to derive equation 3-2 (c) providing the synchronization time, X, as a function of the system time and the value stored in the initial.sub.-- time register 265.
Equations 3-2:
a) elementary stream time=system time-initial.sub.-- time
b) X=(elementary stream timestamp-system time+[system time-initial.sub.-- time])
c) X=(elementary stream timestamp-initial.sub.-- time)
Two solutions for deriving the synchronization time, X, in accordance with the present invention have been illustrated. However, it will be apparent to those skilled in the art that there are many other equivalent solutions.
FIG. 43 shows another embodiment of the present invention implementing video timestamp management. The clock references 253, which represent system time, are decoded by the system demultiplexer 254 and placed initially, and then as needed, into a time counter 255 within the system decoder 256 and are incremented at 90 kHz. A second copy of the clock references 253 are simultaneously loaded into the time counter 258 that is inside the video decoder 270 and incremented at 90 kHz, and synchronized to the time counter 255 in the system decoder 256.
The video time stamps flow from the system demux 254 through the video decoding buffer 271 so that they are delayed by the same amount as the incoming video data. The video time stamps may have a correction added to compensate for the non-zero decode time of the video decoder 270. The corrected video time stamps are than compared with the copy of the time in the time counter 258 inside the video decoder 270 to determine whether the decoded picture is displayed too early or too late.
The embodiment shown in FIG. 43 is an improvement over the process of merely passing system time directly to the video decoder from the time counter in the system decoder because the counter in the system decoder changes 90,000 times a second. Therefore, system time would in all essence need to be continually passed to the video decoder. Passing system time continually would require dedicated pins or the like. By using a time counter located in the system decoder and a time counter located in the video decoder system time can be passed in the form of clock references a few times a second.
Referring now to FIG. 44, the clock references, which represent system time, are decoded by the system demultiplexer 254 and placed into a time counter 255 within the system decoder 256 and incremented at 90 kHz. The vid.sub.-- time counter 272 in the system decoder 256 and the vid.sub.-- time counter 273 in the video decoder 270 are synchronized with each other and incremented at 90 kHz. Video time stamps are also decoded by the system demultiplexer 254. Accordingly, a synchronization value X is computed using a video timestamp, the system time contained in the time counter 273 and the video decoding time contained in the vid.sub.-- time counter 272 contained in the system decoder 256 according to the equations 3-3.
The following set of equations 3-3 (a-d) is illustrative of one method in accordance with the present invention, for time synchronization which avoids passing the clock reference 253 to the video decoder 270. Equation 3-3 (a) is the equation required for time synchronization. Since it is undesirable to pass system time directly to the video decoder circuit 270 as shown in FIG. 44, a synchronization time representation X is generated, using Equation 3-3 (b-d), by the system decoder 256 and passed to the video decoder 270. Synchronization time, X, is then compared to the video decoding time contained within the vid.sub.-- time counter 273 located within the video decoder 270. The compared result is used to determine whether the decoded picture is displayed too early or too late and then further used in time synchronizing the system.
Equations 3-3:
a) Time Synchronization=(Video timestamp-system time)
b) Time Synchronization=(X-video decoding time)
c) (X-video decoding time)=(video timestamp-system time)
d) X=(video timestamp-system time+video decoding time)
In the present invention, the synchronization time, X, may have a correction added to compensate for the non-zero decode time of the video decoder. The corrected synchronization time is then compared with the video decoding time contained in the vid.sub.-- time counter 273 located inside the video decoder 270 to determine whether the decoded picture is displayed too early or too late and is also used to time synchronize the system. Note, the time correction can be subtracted from the video decoding time contained in the vid.sub.-- time counter 273 located inside the video decoder 270 instead of added to synchronization time X for the same result. The above embodiment of the present invention is another example of a solution for generating synchronization time X and determining whether the picture is displayed early or late. However, it will be apparent to those skilled in the art that there are many other equivalent solutions for accomplishing the above.
Another nice feature, in accordance with the present invention, is that there is no need to deal with the full 33 bit time stamp number or 42 bit clock reference number. The present invention restricts the counters to 16 bits to allow 16 bit handling on the video decoder 270. At first glance, it would appear that 16 bits cannot represent a sufficient number range at a resolution of 90 kHz (only 2/3 second to be used). However, there is no need for such high precision because the time control on the video decoder 270 is only accurate to a field time (since the video timing generator VTG free-runs or is gen-locked to something that has nothing to do with the MPEG stream being decoded) and, therefore, it is not related to timestamps or presentation time in any way.
As shown in FIG. 44 and FIG. 45, the synchronization time X and the vid.sub.-- time counter 273 within the video decoder 270 use only sixteen bits. This is made possible by two factors. First, the difference between system time and the timestamp (used to derive the synchronization time; see Equation 3-3) should always be small, thus allowing the more significant bits to be discarded. Second, it is only possible to control the presentation of video to the nearest frametime. Therefore, the less significant bits are not required and are discarded by shifting right by four bits.
Thus, the sixteen bits of time information used in the present invention are able to deal with timing errors of up to about 11.5 seconds with an accuracy of about 180 .mu.s (about 1% of a field time). A PAL or SECAM European 625 line TV system is, thus, 112.5 ticks of the 5625 Hz clock; a NTSC 525 line TV system is 93.84 ticks. Hence, using 16 bits allows timing calculations with an accuracy of about 1% of a field time.
FIG. 46 shows the preferred process, in accordance with the present invention, of the moving the time stamp through the hardware. The preferred method for communicating information in this hardware is Tokens, but it will be appreciated that alternative methods may also be employed. The hardware is divided into two modules. The first module is added just after the Start Code Detector 201. This module is responsible for generating a token, SYNC.sub.-- TIME containing the synchronization time X, as discussed above, and this occurs just before an associated PICTURE.sub.-- START token. In the MPEG systems stream, the time stamp is carried in a packet header and refers to the first picture in the packet of data. Since the packets do not line up with the video data, there will, in general, be the end of the previous picture before the start of the picture to which the time stamp refers.
The synchronization time information may be supplied to the present invention either via a microprocessor interface or by using a Token. In either case, the synchronization time date (16 bits) is stored in the synchronization time register (divided into two parts to allow access to each byte individually), as further detailed in Table 12.
TABLE 12__________________________________________________________________________Microprocessor registers for handling synchronization timeRegister Name Size/Dir Reset State Description__________________________________________________________________________ts.sub.-- low 8/rw The lower eight bits of the synchronization time value. The ts.sub.-- low register is slaved so that new values may be written into this register without affecting the value previously written (that will become part of a SYNC.sub.-- TIME token). Writes to ts.sub.-- low register affect the master register whilst reads read-back the slave register. Until a master -to-slave transfer has been effected using ts.sub.-- valid the value written into ts.sub.-- low cannot be read back. ts.sub.-- high 8/rw The upper eight bits of the synchronization time value. Slaved in the same way as ts.sub.-- low. ts.sub.-- valid 1/rw 0 This bit controls the master-slave transfer of ts.sub.-- low and ts.sub.-- high. When values have been written into ts.sub.-- low and ts.sub.-- high the microprocessor should write the value one into this bit. It should then poll the bit unit it reads back the value one. At this point the values written into ts.sub.-- low and ts.sub.-- high will have been transferred into the slave registers (and can be read back) and ts.sub.-- waiting will be set to one. The microprocessor should then write the value zero in preparation for the next access. ts-waiting 1/ro 0 When set to zero the registers ts.sub.-- low and ts.sub.-- high do not contain valid synchronization time information. When set to one the registers ts.sub.-- low and ts.sub.-- high contain valid synchronization time information. A SYNC.sub.-- TIME token will be generated before the next PICTURE.sub.-- START token and ts.sub.-- waiting will then become zero. This bit should be polled to ensure that it is zero before writing a one into ts.sub.-- valid to ensure that the previous synchronization time value has been used before it is overwritten by the master-to-slave transfer.__________________________________________________________________________
In the present invention, a flag, ts.sub.-- waiting, is set to indicate the fact that valid synchronization time information is in the timestamp register. If the data was supplied using the SYNC.sub.-- TIME token, then that token is removed from the stream of tokens.
When a PICTURE.sub.-- START token is encountered, the flag that indicates the status of the synchronization time register is examined. If the flag is not set, then no action is taken and the PICTURE.sub.-- START token and all subsequent data is unaffected. If, however, the flag is set, indicating that valid synchronization time information is available in the register, then a SYNC.sub.-- TIME token is generated and placed in the data stream before the PICTURE.sub.-- START token. The flag is then cleared and the synchronization time register is made available for the next time-stamp that occurs.
The second module as shown in FIG. 46, consists of a prescaler clocked at 27 MHz and a vid.sub.-- time counter clocked by the prescaler 278 which are associated with the microprogrammable state machine, (MSM) 218.
There is a prescaler 278 that divides the clock by 4800, as shown in FIG. 44 and FIG. 46. In other words, 4800 is 300 (27 MHz/90 kHz) times 16. The 4804.8 option shown in FIG. 45 and FIG. 46 is discussed below.
In the NTSC color television, the frame rate is not 30 Hz but is, in fact, approximately 29.94 Hz (precisely 30000/1001 Hz). [Before the advent of color television 30 Hz precisely was used.] There are precisely 1716, 27 MHz clock periods per NTSC line time (line time is 1/525 of frame time).
The American television standards body has expressed an interest in returning to 30 Hz in the future (or more probably 60 Hz for HDTV). As a result MPEG supports a frame rate of 30 Hz precisely. However, since it is not possible to generate a stable 30 Hz television signal from a 27 MHz clock (there being 1714.29 . . . cycles per line) it is difficult to generate a 30 Hz raster in the MPEG framework.
One possible solution is to "bend" the clock rate at the decoder so that instead of producing a 27 MHz clock, a 27.027 MHz clock is generated. This clock is generated using the MPEG clock references with a divider of 300.3 (rather than 300) to yield the 90 kHz clock. This 27.027 MHz clock when clocking the identical video timing circuitry that provides a 29.94 Hz frame rate from 27 MHz will give a precise 30 Hz rate.
In the framework of the present invention, the 90 kHz is prescaled by a further factor of 16. Accordingly, division of the 27.027 MHz clock by 300.3.times.16=4804.8.
The Vid.sub.-- time counter 273 (discussed above) contains the video decoding time and is incremented each time that the prescaler reaches its terminal count. The vid.sub.-- time counter 273 is reset by the reset-time pin.
The prescaler and vid.sub.-- time counter of the present invention can be implemented with fully clocked feed-back flip-flops which are much more resistant to .alpha.-particle corruption than the resistive-feedback or weak-feedback latches used elsewhere. Using clocked feedback flip-flops for time counters will help ensure that the time counter in the video decoder stays in step with the time counter in the system decoder.
FIG. 47 illustrates the process the MSM 218 performs when it receives the SYNC.sub.-- TIME token. The MSM 218 is able to read the current time indicated by the video time counter and to then compare it with the value supplied by the video SYNC.sub.-- TIME token. It can, therefore, determine whether it is early or late, as compared to the time at which it should be decoding the pictures.
In the present invention, a 16 bit signed timestamp correction is added to the synchronization time X (discussed above) that was carried by the video SYNC.sub.-- TIME token. This correction is reset to zero by the MSM 218 at chip-reset, and if no action is taken, the synchronization time remains be unaltered. The controlling microprocessor can always write value into ts.sub.-- correction to modify the synchronization time and, therefore, compensate for differential delays through the video and audio decoders.
The current video decoding time contained in the vid.sub.-- time counter 273 is subtracted from the corrected synchronization time. The sign of value gives the direction of the error (and determines the error code, if any, generated by the MSM 218). The absolute value of the difference is then taken and the result is compared to a threshold value to determine whether the timing error is within acceptable limits. Since, at present, the video timing can only be controlled to an accuracy of plus or minus a frame time from the nominal time (because the VTG 333 free-runs) this threshold is set at one frame time.
If the error exceeds a frame-time, then some correction must be made. The MSM 218 of the present invention can correct the situation itself if the decoding is too early since the MSM can simply delay the decoding until the appropriate time. However, if the decoding is later than the intended time, then time correction is more difficult because it is not possible to discard pictures reliably at the output of the coded data buffer. Essentially, the decoding of the sequence is broken and the most reliable way to correct the situation is to restart the decoding process in a manner similar to random-access or channel change. In order to facilitate this process, the control register of the MSM 218 may be programmed to discard all data until a suitable start code or FLUSH token is encountered. In addition, the error "ERR.sub.-- TOO.sub.-- EARLY" is not generated during start-up, irrespective of the setting of disable.sub.-- too.sub.-- early, because at start up, the first picture is expected to be early.
Table 13 is illustrative of how the MSM 218 registers work and details some of the actions and error messages information placed in the registers can generate.
TABLE 13__________________________________________________________________________Timestamp MSM registersRegister Name Size/Dir Reset State Description__________________________________________________________________________ts.sub.-- correction 16/rw zero Correction added to synchronization time before it is used. frame.sub.-- time 16/rw 226 or 188 Represents the tolerance on the timing of decoding pictures. Reset state determined by the PAL/NTSC pin. vid.sub.-- time 16/ro zero Reset by either reset or reset.sub.-- time. The current value of video decoding time. manual.sub.-- startup 1/rw zero When set to one the start-up is to be performed manually using decode.sub.-- disable. In this case SEQUENCE.sub.-- END and FLUSH tokens at the MSM cause decode.sub.-- disable to be set to one. decode.sub.-- disable 1/rw zero When set to zero the decoding proceeds normally. At the start of each picture the MSM checks the status of decode.sub.-- disable and will not proceed if it is set to one. Note that if manual start-up is to be performed (i.e. without the time-stamp management hardware) then this bit should be set to one at the same time as manual.sub.-- startup is set to one. disable.sub.-- too.sub.-- early 1/rw zero When set to one the error "ERR.sub.-- TOO.sub.-- EARLY" indicating that the decoding is too early is suppressed and the MSM simply waits to correct the situation. NTSC.sub.-- 30 1/rw zero When set to one the prescaler divides by 4804.8 rather than 4800. Set automatically when decoding 30 Hz frame rates. discard.sub.-- if.sub.-- late 1/rw zero This has no effect unless an "ERR.sub.-- TOO.sub.-- LATE" is generated (or would be generated if errors were not masked out). If it is set to one then data is discarded until the condition indicated by discard.sub.-- until. discard.sub.-- until 2/rw zero Indicate the condition which causes time-stamp triggered discarding to be terminated. 0 - FLUSH 1 - SEQUENCE.sub.-- START 2 - GROUP.sub.-- START 3 - NEXT PICTURE Note 1 - that discarding one picture may immediatety be un-done if that picture is a field picture by the generation of a dummy field to preserve the alternating top/bottom field structure. As a result if discard.sub.-- until is set to "Next Picture" but the dummy field would be generated one further picture is discarded.__________________________________________________________________________
As a result of the synchronization time handling of the present invention, it is possible that one of two errors will be generated.
ERR.sub.-- TOO.sub.-- EARLY is generated if the decoding is taking place earlier than the time indicated by the time.sub.-- stamp. ERR.sub.-- TOO.sub.-- EARLY may be suppressed, but ERR.sub.-- TOO.sub.-- LATE will always be generated unless all errors are masked out.
In summary, the present invention includes: an apparatus for synchronizing time having, a timestamp for determining presentation time, a clock reference for initializing system time in a first circuit, a first time counter in communication with the clock reference for keeping system time in a first circuit and a second time counter initialized by the clock reference in a second circuit synchronized with the first time counter, for keeping a local copy of the system time and for determining the presentation timing error between the local copy of system time and system time by comparing the timestamp to the second time counter. It further includes an apparatus for synchronizing a system decoder and a video decoder using a timestamp for determining display time, a clock reference for initializing system time in the system decoder, a first time counter in communication with the clock reference for keeping system time in the system decoder and a second time counter initialized by the clock reference in the video decoder synchronized with the first time counter, for keeping a local copy of system time and for determining the display timing error between the local copy of system time and system time by comparing the timestamp to the second time counter. A still another embodiment includes an apparatus for synchronizing a first circuit and a second circuit using a clock reference for initializing system time in the first circuit, a first circuit having a time counter in communication with the clock reference for keeping system time, a first elementary stream time counter in the first circuit for providing elementary stream time. The first circuit is adapted to receive a time stamp, and the first circuit generates synchronization time by adding elementary stream time to the time stamp and subtracting system time. The second circuit is adapted to receive synchronization time from the first circuit and has a second elementary stream time counter in synchronization with the first elementary stream time counter for providing a local copy of the elementary stream time and for determining a timing error between the system time and the time stamp by comparing synchronization time to the local copy of elementary stream time. In this way, the clock reference signal does not have to be passed directly to the second circuit in order to determine the timing error. In another embodiment, an apparatus for synchronizing a first circuit and a second circuit has a clock reference for initializing system time in the first circuit. The first circuit has a time counter in communication with the clock reference for keeping system time, and a first video time counter for providing video decoding time. The first circuit is adapted to receive a video time stamp and generates synchronization time by adding video decoding time to the video time stamp and subtracting system time. The second circuit is adapted to receive synchronization time from the first circuit and has a second video time counter in synchronization with the first video time counter for providing a local copy of video decoding time and for determining a timing error between system time and the video time stamp by comparing synchronization time to the local copy of video decoding time. Accordingly, the clock reference signal does not have to be passed directly to the second circuit in order to determine the timing error. The present invention also includes a method for providing timing information by providing a video data stream having a time stamp carried in packet header wherein the time stamp refers to the first picture in the packet of data. In the next step a register is provided having a flag used to indicate valid time stamp information which is taken from the packet header and placed into the register. Next, the timestamp is removed from the video data stream and placed in the register. Next, the method encounters a picture start and subsequently examines the status of the register to determine if valid time stamp information is contained in the register by checking the flag status. A time stamp is generated in response to the picture start if the flag indicates valid time stamp information is contained in the register and then the timestamp is inserted back into the data stream. Another embodiment includes an apparatus described above wherein the elementary stream time counters are restricted to 16 bits. Likewise, there is an apparatus as described above, wherein the second elementary stream time counter located in the elementary stream decoder is restricted to 16 bits. Furthermore, there is an apparatus as described above wherein the synchronization time is restricted to 16 bits for controlling the elementary stream decode. The present invention also has a process for decoding video and for determining display time errors against a threshold value. It then parses video data into tokens for further processing, determining if a time stamp token is indicated, comparing the time stamp token to a video time, and generates a compared value to determine an indicative of timing error. Next, it determines whether the compared value, when compared against a threshold value, is within acceptable parameters when a timing error is indicated and indicates when the compared value is outside acceptable parameters. An alternative embodiment includes an apparatus for using a system decoder and a video decoder. The system decoder is adapted to accept MPEG system streams and demultiplexing video data and the video time stamp from the stream. The system decoder has a first time counter representative of system time. The video decoder accepts the video data and the video time stamp, and has a second time counter in synchronization with the first time counter. The video decoder also has a video decoder buffer for accepting the video data at a substantially constant rate and outputting the video data at a varying rate and for passing a video time stamp. The video decoder while decoding a picture from the video data also compares the video time stamp for the decoded picture with the second time counter to determine the appropriate display time. There is also a method for determining a time error between a first circuit and a second circuit by providing the first circuit with a system time (SY), a time stamp (TS), and an elementary stream time (ET), obtaining synchronization time (X) by using the elementary stream time (ET), the time stamp (TS) and the system time (SY), in accordance with the equation; X=ET+TS-SY, providing synchronization time (X) to the second circuit and generating a synchronized elementary stream time (ET2) and obtaining a time error by using synchronized time (X) and in accordance with the equation ET2-X; hence, the first circuit can be time synchronized with the second circuit without passing system time to the second circuit. Another method for determining a time error between a first circuit and a second circuit has the following steps: providing the first circuit with a time stamp (TS), and an initial time(IT), obtaining synchronization time (X) by using the time stamp (TS) and the initial time (IT), in accordance with the equation X=TS-1, providing synchronization time (X) to the second circuit and generating a synchronized elementary stream time (ET) and obtaining a time error by using synchronized time (X) and in accordance with the equation ET-X. In this way, the first circuit can be time synchronized with the second circuit without passing system time to the second circuit. Still another method for determining a time error between a first circuit and a second circuit includes the following steps: providing the first circuit with a system time (SY), a video time stamp (VTS), and a video decoding time (VT), obtaining synchronization time (X) by using the video decoding time (VT), the video time stamp (VTS) and the system time (SY), in accordance with the equation; X=VT+VTS-SY, providing synchronization time (X) to the second circuit and generating a video decoding time (VT2) in the second circuit which is synchronized to the video decoding time (VT) in the first circuit, and obtaining a time error by using synchronized time (X) and in accordance with the equation VT2-X. Accordingly, the first circuit can be time synchronized with the second circuit without passing system time to the second circuit.
Detailed Description of the Invention for Asynchronous Swing Buffering
For asynchronous swing buffering, in accordance with the present invention, two buffers are operated asynchronously; one is written while the other is read. Accordingly, this allows for a data stream having a first rate of through-put to be resynchronized to another rate, while still maintaining a desired rate. In the invention, the write control and read control both have state indicators for communicating which buffer they are using and whether the controls are waiting for access or are, in fact, accessing that buffer. Each side communicates to the other side a single bit to indicate which buffer it is using. This is the only signal that must be synchronized between the two sides of asynchronous circuitry.
When one control circuit (read or write) finishes accessing a buffer, then the invention will allow control to pass to the other circuit. If, after the control has swung, and two control circuits are trying to use the same buffer, then the later control circuit will begin waiting. The control circuit will wait until each side is using alternate buffers, i.e., the other side has swung. If, after it has swung, it finds that it is now using the alternate buffer to the other side, it will not wait, but immediately commence accessing. This system of arbitration between the buffers is started up by both buffers using the same buffer, buffer 0, in this case. The read side starts up by waiting, while the write side is accessing, since there is nothing valid to read out of either buffer.
In one embodiment, in accordance with the present invention, the swing buffers are two discrete RAMS having all signals, such as enabling strobes, addresses and data multiplexed from either the read or write side, dependent on which buffer is being accessed by each side. This structure has been shown to use a lot of area in the busing of a large number of signals between the two buffers.
Combining the two RAMs into a single structure saves much of the busing area while still maintaining performance to the same standard. This structure contains twice as many rows of cells as one of the discrete RAMs found in the first embodiment of the present invention. However, the second embodiment must have two pairs of bit lines since the read and write to the discrete buffers is happening simultaneously and asynchronously. Each row will be of its original width (i.e., have the same number of cells) since accesses are the same width as for the discrete RAMS. Each pair of rows are accessed as if at the same address, but from different buffers, so they connect to a different pair of bitlines. Using the same address, these pair of rows can be readily accessed by one row decoder connected to the read address and one row decoder connected to the write address. Again, the read and write control never access the same buffer at the same time so there is no conflict as to which pair is accessed by which row decoder.
In the same way in which each row decoder can access rows from each buffer, both the read and write circuitry within the structure of the present invention connect to each pair of bitlines, one pair from each buffer. The read and writes are then multiplexed into each of the buffers and, for the same reasons explained above, there will not be conflict.
As shown in FIG. 48, a swing unit 1 includes swing buffers 10 with RAM 12 and 14 in accordance with the present invention. The swing unit 1 also includes a write control circuit and a read control circuit, which control the data into and out of the RAM 12 and 14. The read control circuit and the write control circuit accomplish this by use of strobes, data and address control lines, 8. Lines 7 and 9 are control lines to indicate the RAM used by the write control circuit and the RAM used by the read control circuit. Line 7 functions to control the write control circuitry, i.e., when the read control circuitry is using, RAM 12 if low, RAM 14 if high. Similarly, Line 9 functions to inform the read control circuitry that the write control circuitry is using RAM 12 if low, RAM 14 if high.
In the present invention, swing buffer 10 has two RAM arrays, 12 and 14. Swing Buffer 10 is capable of asynchronous, alternative reading and writing to the RAM area which enables the apparatus to achieve the necessary band width for high speed accessing of the memory. The RAMs 12 and 14 require the following signals: write address 16, read address 18, data in 20, data out 22; and a read and write enable signal (not shown). See also FIG. 49.
The write address and read address signals are multiplexed by multiplexers 24. The RAM array 12 and 14 operate with the write circuitry, row decoder and read circuitry in a conventional sense.
In the first embodiment of the present invention, during initiation of the swing buffer 10, RAM 12 will be written to until the control circuitry switches a write enable single to RAM 14.
Once the RAM array 12 has been written, it falls under the control of the read circuitry 4, to be read. During this time, the RAM array 14 is also being written. It is important to note when the RAM array falls under the control of the read array control 2, or the write control circuit 4, the control is established until reading or writing is completed and then control is turned over. In the situation where the read control circuit 4 is accessing the RAM array, such as 12, and the write control circuitry 2 needs to access the same RAM array 12, then the write control circuit will begin waiting.
Therefore, in accordance with the present invention, two control events are created. When a write control circuit or a read control circuit swings to a different RAM, it will either begin immediately accessing the RAM since the RAM is free and not under control of the alternative circuit, or it will begin to wait. During start up, the read side defers to the write side, since there is nothing valid to be read out of either buffer.
The second embodiment of the present invention is shown in FIG. 50. An integrated swing buffer 30 includes a RAM array 32 having the logical size of RAM array 12 combined with RAM array 14. In other words, there is the same amount of RAM in both the first and second embodiments, however, it is combined in the second embodiment. Accordingly, the integrated swing buffer has the advantage of saving much of the busing area while still performing the same swing buffer function.
In the second embodiment of the present invention, the write circuit and read circuit 34 and 36 respectively, are similar to those used in the swing buffer 10. However, these circuits now include selectors which choose from the pairs of bit lines described hereinafter. Likewise, the read access row decoder 38 and the write access row decoder 40 are similar to those contained in swing buffer 10, however, they are able to access a pair of rows as described hereinafter in FIG. 51.
As shown in FIG. 51, the particular structure of the integrated swing buffer 30, in accordance with the present invention, is detailed. Individual cells 42 are contained in rows 44. The read row decoder 38 and write row decoder 40 access the rows 44 in pairs. A pair of rows have the same address provided by the address lines 16 and 18. The read buffer line 52 and write buffer line 54 provide the control information for selecting one of the paired rows 44. The buffer 0 bitlines 48 and buffer 1 bitlines 50 connect to alternative rows of cells and to the read and write circuitry 34 and 36. For clarity in depicting the addressing, the lighter shading illustrates the read row decoder 38 accessing a row in buffer 0. Similarly, the darker shading illustrates the write row decoder 40 accessing a row in buffer 1.
In summary, the present invention includes a swing buffer apparatus having at least two RAM arrays, a write control circuit in communication with the RAM arrays for controlling data input into the RAM array, and a read control circuit in communication with the RAM arrays for controlling data output from the RAM arrays. Furthermore, the write control circuit and read control circuit are in communication with one another to allow a synchronized control of the RAM arrays. There is also a swing buffer apparatus having a RAM array, a write control circuit in communication with the RAM array through a pair of bit lines, a read control circuit in communication with the RAM array through another pair of bit lines and a read row decoder and a write row decoder for addressing the RAM through a pair of rows so that individual cells are read. The present invention also provides a method of asynchronously addressing RAM, by decoding at least a pair of cells in the RAM, using a row decoder to decode at least a pair of rows and selecting one of the rows to be assessed, using at least two pairs of bitlines connected to read a circuit and a write circuit and selecting the pair of bitlines to be used.
Detailed Description of the Invention for Storing Video Information
Video decompression systems contains three basic parts used to decode and display picture information. The three main parts of a video decompression system are the spatial decoder, temporal decoder and the video formatter. The present invention involves the temporal decoder and video formatter and the way in which the temporal decoder and video formatter manage their respective picture buffers, hereinafter the frame store buffer. In MPEG systems, the temporal decoder contains two frame store buffers and the video formatter contains two frame store buffers.
MPEG uses three different picture types: Intra (I), Predicted (P) and Bidirectionally interpolated (B). B pictures are based on predictions from two other pictures; one picture is from the future and one from the past. The I pictures require no further decoding by the temporal decoder, but must be stored in one of the two frame store buffers for later use in decoding P and B pictures. Decoding a P picture requires forming predictions from a previously decoded P or I picture. The decoded P picture is stored in a frame store buffer for use in decoding further P and B pictures. B pictures can require predictions from both of the frame store buffers. However, B pictures are not stored in the frame store buffers.
It will be appreciated that I and P pictures are not output from the temporal decoder as they are decoded. Instead, I and P pictures are written into one of the frame store buffers, and they are read out only when a subsequent I or P picture arrives for decoding. In other words, the temporal decoder relies on subsequent P or I pictures to flush previous pictures out of the two picture buffers. Accordingly, the spatial decoder of the present invention can provide a fake I or P picture when it is necessary to flush the temporal decoder's two frame store buffers. In turn, this fake picture is flushed when a subsequent video sequence begins.
As shown in Table 14, the picture frames are displayed in numerical order.
TABLE 14______________________________________Frame Stores______________________________________Display Order I1 Be B3 P4 B5 B6 P7 B8 B9 I10 Transmit Order I P4 Be B3 P7 B5 B6 I10 B8 B9______________________________________
However, in order to reduce the number of frames that must be stored in memory by the temporal decoder, the frames are transmitted in a different order. It is useful to begin the analysis from an intra frame (I frame). The I frame is transmitted in the order it is to be displayed. The next predicted frame (P frame), P4 is then transmitted. Then, any bidirectionally interpolated frames (B frames) to be displayed between the I frame and P4 frame are transmitted, represented by Be and B3. This allows the transmitted B frames to reference a previous frame (forward prediction) or a future frame (backward prediction).
After transmitting all the B frames to be displayed between I and P4, the P7 frame is transmitted. Next, all the B frames to be displayed between the P4 and P7 frames are transmitted, i.e., corresponding to B5 and B6. Then, the next I frame, 110, is transmitted. Finally, all the B frames to be displayed between the P7 and 110 frames are transmitted, corresponding to B8 and B9. This ordering of transmitted frames requires only 2 frames to be kept in memory by the temporal decoder at any one time, and does not require the decoder to wait for the transmission of the next P frame or I frame to display an interjecting B frame. As described above and shown in Table 14, the temporal decoder of the present invention can be configured to provide MPEG picture reordering. With this picture reordering, the output of P and I pictures is delayed until the next P or I picture in the data stream starts to be decoded by the temporal decoder.
As the P and I pictures are reordered, certain tokens, i.e. Picture.sub.-- Start, Picture.sub.-- Type, and Temporal.sub.-- Reference, are stored temporarily on the chip as the picture is written into the picture buffers. When the picture is read out for display, these stored tokens are retrieved. At the output of the temporal decoder, the DATA tokens of the newly decoded P or I picture are replaced with DATA tokens for the older P or I picture, and they are then sent to the video formatter. Note that the output from the temporal decoder is in tokenized macroblock format and there is no block-to-raster conversion.
In brief, the video formatter of the present invention stores two framestores or pictures. In some video formatters three pictures or framestores are used to accommodate such features as repeating or skipping pictures. The video formatter's off-chip DRAM holds three framestores. The use of three framestores here allows frames to be either repeated or skipped in situations where the frame rates of the decoded video and the display are different.
All I, B and P frames are stored in the framestores of the video formatter. At any one time, there may be one frame store from which data is being displayed, one frame store into which data is being written, and in video formatters with three framestores, one other frame may be being stored in the third frame store.
The present embodiment performs all the prediction, reordering and block-to-raster tasks MPEG normally handles by using a temporal decoder with two framestores and a video formatter with two framestores, i.e., for a total of four framestores. This is accomplished in the present invention by using a frame store sharing scheme that only uses three framestores. The present embodiment cannot, however, handle the repeat and skip frame tasks of a video formatter with only the three framestores.
The present invention stores I pictures in a first frame store and P pictures in a second frame store. Because of the need to perform the block-to-raster conversion, B frames are stored in the manner detailed below in a third frame store. In order to minimize the amount of external DRAM required, a scheme is used where successive B frames share the same third frame store.
When a B frame is decoded, it may refer to the two previously decoded I or P frames occupying the first and second framestores. The decoded B frame is written into the third frame store. The present embodiment allows the raster to commence prior to a frame store being completely filled. The raster is allowed to start before the frame store is filled so that the next B frame can be written into the same frame store to occupy the space vacated by the raster at the top of the previous frame.
In order to keep a record of which parts of the frame store are occupied with picture data, and which are available for new data, each frame store is split into sectors. In the present invention, each frame store is first split into two field stores, each of which comprises N sectors, where N is the number of block rows in the field.
Frames coded as field pictures are straightforward. Each successive macroblock row occupies two sectors in a field store. Once the write back has progressed far enough down the frame, the raster starts reading out each sector from the top. Once the write back of the first frame has been completed, the start of the next frame is written into the space left by the raster. Checks on the status of each of the sectors ensures that the sector to be rastered is indeed full, and that for write back, the two sectors required are empty.
Frames coded as frame pictures are more difficult. Unlike field pictures, the macroblock rows of data are not written to the DRAM in the same order as they are to be rastered. The field stores are written to in parallel, whereas the fields are rastered in turn.
Consider a picture with 8 sectors per field store. That is, Field store 0 consists of 8 sectors numbered 0 to 7, each of which contains one row of blocks (i.e., each 8 pixels deep by the width of the picture). Field store 1 consists of 8 sectors, numbered 8 to 15, each of which contains one row of blocks (i.e., each 8 pixels deep by the width of the picture).
The first macroblock row is written back into sector 0 in field store 0 and to sector 8 in field store 1. The field stores continue to be filed in parallel. At some point, the raster beings displaying sectors from field store 0, that point being chosen so that the raster of field store does not catch up with the write back. However, the second frame cannot be written back in the same manner as the first. Because the sectors are written and read in a different order, waiting for the same two sectors to be free at the start of a frame would mean that write and read could not run continuously. This must be achieved in order to maintain the display and to maintain decoding at the necessary rate.
Accordingly, the second frame must be written into sectors of the frame store already freed by the raster. This is implemented by dividing the framestores in two. Hence, for the second frame, the meanings of the half field stores change. Sectors 4-7 become the upper part of the second field store and sectors 8-11 become the lower part of the first field store, i.e., they swap over. The first macroblock row is written to sectors 0 and 4, once they are freed, with subsequent rows written to 1 and 5, then 2 and 6, and then 3 and 7. The next row is written to sectors 8 and 12, and so on through to 11 and 15. This reallocation to the memory is sufficient to allow the write back and raster to continue at the appropriate rate.
Should a third successive B frame arrive, the write back order reverts to that of the first frame.
In the shared B frame store, with FRAME pictures:
The FIRST picture is written back to--Sectors 0 and 8 [1st macroblock row=2 block rows] Then 1 and 9, 2 and 10, 3 and 11, 7 and 15.
The FIRST picture is rastered from--Sector 0, Then 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15.
The SECOND frame is written to--Sectors 0 and 4, Then 1 and 5, 2 and 6, 3 and 7, 8 and 12, 9 and 13, 10 and 14, 11 and 15.
The SECOND frame is rastered from--Sector 0, Then 1, 2, 3, 8, 9, 10, 11, 4, 5, 6, 7, 12, 13, 14, 15.
Note that, in accordance with the present invention, the second frame, the first macroblock row is not written into sectors 0 and 1, which are, after all, the first two sectors to be freed by the raster. Instead, it waits for sector 4 to clear. This is done for two reasons: First, waiting for sector 4 to clear does not affect the system's ability to maintain continuous decoding and display, even in the situation of worst-case coded data, and it is easier to implement. Secondly, with picture sizes which divide into a number of sectors that are not a power of two, the sequence for writing to and reading from sectors of memory does not repeat often (for example, NTSC format has 30 sectors per field and the sequence would repeat every 58 frames). This makes testability and recovery difficult.
As far as implementation is concerned in the present invention, rather than keep a record of the status of each individual sector, each half field store is effectively implemented as a fifo, with pointers to the next location to be written and to be read. Thus, each fifo being full or empty causes write back and raster, respectively to be disabled. This makes use of the knowledge that each half field store is itself written and read only one way, just like a fifo.
In summary, the present invention, provides method for storing video information by providing video information in the form of an I Frame, a P Frame, a B.sub.1 Frame and a B2 Frame, storing the I Frame in a first Frame store, storing the P frame in a second frame store; providing a third Frame store having a first and second field store, the first and second field store being split into at least two memory areas respectively, storing the B.sub.1 Frame in the third register, reading the B.sub.1 Frame from a selected portion of the memory area in the first or second field store; writing a portion of the B2 Frame into the selected portion of the memory area from which the B.sub.1 Frame was read; whereby a reduced amount of memory can be used to store video information.
The two programs found herein below contain code to be used in the preferred embodiment of the invention.
Detailed Description of the Invention for a Parallel Huffman Decoder
In accordance with the present invention, the Parallel Huffman Decoder block will decode Huffman coded Variable Length Codes (VLCs) and Fixed Length Codes (FLCs), and pass through tokens under the control of the parser microprogrammable state machine (MSM).
This embodiment of the present invention handles both MPEG-2 as well as MPEG-1 Huffman codes. An important aspect of this embodiment of the invention is that it can sustain a high through-put due to the fact that it is a parallel decoder rather than a serial one.
This embodiment of the present invention uses a code lookup technique to decode Huffman codes. This is done to achieve the performance requirements and also to handle the second MPEG-2 transform coefficient table which is irregular or non-canonical in nature.
Furthermore, this embodiment of the invention has some features that allow it to decode certain more complex components from the stream in a single cycle without the assistance of an external controller. Examples of such complex components are Escape-coded coefficients, Intra-DC values and Motion Vector deltas, all of which are present in the stream as combined VLC/FLC components.
Referring now to FIG. 52, there is shown how the Parallel Huffman Decoder 300 deals with variable length codes (VLCs). FLCs require a bypass mechanism which uses the selector 301 output to generate data and an input field to specify the length of the FLC. Thus, the ROM 302 is not required at all during FLC decoding.
However, to decode a VLC, input is first loaded into the two input data registers, `MSReg` and `LSReg` as shown in FIG. 52. As the names imply, the "earlier" or most significant data is stored in MSReg. The selector is used to align the beginning of the next VLC with the ROM input. Thus, to decode the very first VLC, the selector outputs the top 28 bits of its 59-bit input and the top 16 bits of these are passed to the Huffman Code ROM 302. For subsequent VLCs, the selector effectively shifts the input according to the total count of bits decoded thus far. The count is maintained by adding the size of each VLC, as it is decoded, to a running total. The various word widths are a result of the maximum coded size which can be decoded, which is the 28-bit MPEG-1 Escape Coded Coefficient, and the maximum VLC size which is 16 bits (DCT coefficient tables).
The "table select" input is used to select between the various different Huffman code tables required by MPEG.
The Huffman Code ROM
The core of the implementation of the present invention, used to decode all the VLCs is a special ROM 302 whose addresses are controlled with a selector/shifter 301 as shown in FIGS. 52 and 53. The ROM 302 has the job of performing a VLC table index calculation, followed by the index-to-data operation that yields decoded data.
The index calculation can be thought of as a content addressable memory (CAM) operation with "don't care" matching implemented to handle the Huffman codes which form the presented data. Since all the VLC code tables are fixed, a CAM-ROM will suffice and this is the job of the ROM AND-plane shown in FIGS. 54 through 57. Since the index generation is performed in a look-up manner (rather than algorithmically) there is no restriction to handling tables which are canonical.
The ROM Or-plane converts the "index" (an activated word-line) into the decoded data and the size (or length) of the code. The data forms the decoded output (subject to error checking) and the size information is fed back to allow a calculation to be performed which controls the selector and, thus, presents the decoder ROM 302 with the correct data to perform the decoding of the next VLC in the subsequent cycle.
The ROM 302 address of the present invention is in two fields. The larger field is the bit-pattern to be decoded and the smaller field selects which Huffman code table is to be examined. The bit-pattern which must be examined is quite long, 16 bits, corresponding to the longest VLC code and there is an additional 4 bits of table select. Thus, there is a total address space of 20 bits (approximately one million addresses) although there are only in 450 entries in the ROM 302. The reason for the difference is due to the existence of "don't care" bits.
In order to decode VLCs, the AND-plane must be able to decode "don't care" bits in the VLC bit-pattern. This is because all VLCs which are shorter than the maximum 18 bits will be followed by additional bits which form no part of the decoding of that VLC. Because of the wide address, the AND-plane is predecoded (2.fwdarw.4), and the ROM 302 must combine "don't care" handling with this predecode. Furthermore, in addition to the complete MPEG code tables, the ROM 302 also has entries to identify illegal VLC patterns, which exist for some code tables.
Maximizing Throughput
In order to sustain output of one decoded item every cycle, some care must be taken to control the decoder input and special handling must be used for some "complex" symbols (i.e., ones which are not single FLCs or VLCs).
In order to sustain peak throughput of Escape-coded coefficients it must be possible to input at least one complete code per cycle. Since the maximum length required is 28 bits in MPEG-1 this dictates the input word width of 32 bits (being the next sensible size greater than 28).
Normal transform coefficients are also "complex" symbols, in the sense that they consist of a VLC followed by a 1-bit FLC which gives the sign of the level value and are handled in a similar manner to the other complex symbols (e.g. motion Vectors, Intra DC and Escape coded coefficients). Peak throughput cannot be achieved if coefficients are decoded as a VLC followed by an FLC (in separate cycles) and the alternative of allowing the ROM 302 to decode the sign bit would double the size of the two largest tables in the ROM. Thus in the present invention, special handling is used for various symbols so that a single cycle can produce the "final" required result.
FLCs and Tokens
The basis of FLC handling is to control the selector with the required length of the FLC and to bypass the ROM 302 and simply output the correctly selected FLC. Thus, simple FLCs are handled fairly naturally by the decoder, without significant extra hardware. Furthermore, tokens are not manipulated, but simply passed directly to the output of the decoder.
Implementation
This section describes several important features of the implementation of the decoder, in accordance with the present invention. The implementation includes the arrangement of registers with the counter 303 and selector 301, as shown in FIG. 52, and the actual code ROM.
The schematic of FIG. 53 shows how the core components are interconnected to implement the main Huffman decoding core section of the present invention. The registers ms[31:0] and ls[31:0] are MSReg and LSReg, respectively, and the block phselect is the selector. The counter logic is contained in the block phcclog (together with various other logic) and the count latch is called cntl[4:0]. The other logic on this schematic deals with handling commands, data and command dynamics, tokens, and the manipulation of the more "complex" symbols (performed in block phcop).
The schematic shown in FIG. 54 illustrates a very small sample ROM design of the type used to implement the Huffman code ROM 302 in accordance with the present invention. The unusual features of this ROM 302 lie in the AND-plane where predecode and "don't care" handling are used to implement a method of decoding variable length Huffman codes.
Referring now to FIGS. 55, 56 and 57 and, more particularly to FIG. 55, there is shown a first embodiment of a ROM AND-plane capable of "don't care" handling. In this embodiment, each address line (a[3], a[2], a[1] and a[0]) is driven across the AND-plane in both its true and inverted directions. To decode a "one" or a "zero" on a given address line, a transistor is connected to either the true or inverted address line in the conventional manner. In order to decode a "don't care" (denoted by x) a transistor is not connected to either the true or the inverted line.
FIGS. 56 and 57 show alternative embodiments that utilize pre-decoding to reduce worst-case number of series transistors in the decoding logic. In these examples, two address bits are combined together in predecoding such that one of four lines is driven high for each of the four possible numbers that can be represented with the two address bits. It will be appreciated by one of ordinary skill in the art that the present invention would work equally well with higher levels of predecoding in which more than two bits are combined together. If the two address bits that are grouped together in the predecoding have defined values (either 1 or zero, but not the "don't care") then a transistor is connected to the appropriate predecoded address line in the conventional manner. Similarly, if both of the address bits have a "don't care", then no transistor is used as before. However, if one of the address bits needs to have a defined value (1 or zero) whilst the other address bit requires "don't care", then the decoding requires that the wordline driven across the Or-plane be selected when either of two of the predecoded address lines is active. In the embodiment shown in FIG. 56, this is achieved by placing two transistors, one on each of the relevant predecoded address lines, in parallel as shown in the case for the code; 001x. In the embodiment shown in FIG. 57 the required decoding is achieved without using a parallel connection of transistors. In this case, two separate decodes are performed both of which must be selected. They are combined together using a NOR gate in the wordline driver such that the wordline is only activated if both of the selects are active.
The foregoing description is believed to adequately describe the overall concepts, system implementation and operation of the various aspects of the invention in sufficient detail to enable one of ordinary skill in the art to make and practice the invention with all of its attendant features, objects and advantages. However, in order to facilitate a further, more detailed in depth understanding of the invention, and additional details in connection with even more specific, commercial implementation of various embodiments of the invention, the following further description and explanation is proffered. ##SPC1##
Note that additional Figures, which are self explanatory to those of ordinary skill in the art, are included with this application for providing further insight into the detailed structure and operation of the environment in which the present invention is intended to function.
The aforedescribed pipeline system of the present invention satisfies a long existing need for further improvements in various aspects of video decoding systems, including an MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.
It will be apparent from the foregoing that, while particular forms of the invention have been illustrated and described, various modifications can be made without departing from the spirit and scope of the invention. Accordingly, it is not intended that the invention be limited, except as by the appended claims.

Number	Date	Country	Kind
9415413	Jul 1994	GBX
9511569	Jul 1995	GBX

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0446956	Sep 1991	EPX
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0468480	Jan 1992	EPX
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	Number	Date
Parent	991234	Dec 1997
Parent	473813	Jun 1995
Parent	400397	Mar 1995

	Number	Date	Country
Parent	475729	Jun 1995
Parent	082291	Jun 1993

Method of asynchronous memory access

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CROSS REFERENCE TO RELATED APPLICATIONS

US Referenced Citations (14)

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Non-Patent Literature Citations (8)

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Entry
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