Claims
- 1. A process for forming a barrier film on a polysilicon plug in a dielectric layer of an integrated circuit, comprising:depositing a layer of titanium on an upper surface of the polysilicon plug; depositing a layer of amorphous material on an upper surface of the layer of titanium; and depositing a layer of titanium nitride on an upper surface of the layer of amorphous material.
- 2. The process of claim 1, further comprising:recessing the upper surface of the polysilicon plug; and forming a well in a portion of the dielectric layer above said polysilicon plug; depositing portions of the layer of titanium, the layer of amorphous material, and the layer of titanium nitride within the well and a portion of a surface of the dielectric layer; and removing at least a portion of each of the layer of titanium, the layer of amorphous material, and the layer of titanium nitride deposited on said portion of the surface of the dielectric layer.
- 3. The process of claim 1, further comprising:placing the dielectric layer of an integrated circuit in a low-pressure chemical vapor deposition chamber; providing a carrier atmosphere in the low-pressure chemical vapor deposition chamber having a pressure in a range between 0.1 Torr to 100 Torr; providing a precursor compound in the low-pressure chemical vapor deposition chamber; and heating the dielectric layer to a temperature in a range of between 200° C. to 600° C.
- 4. The process of claim 3, wherein the carrier atmosphere comprises a mixture including at least one gas selected from a group consisting of a noble gas, nitrogen and hydrogen.
- 5. The process of claim 3, wherein the precursor compound comprises an organo-metallic compound.
- 6. The process of claim 5, wherein the precursor compound comprises tetrakis-dialkylamido-titanium.
- 7. The process of claim 6, wherein the precursor compound selected comprises a sole precursor.
- 8. The process of claim 2, wherein said removing at least a portion of each of the layer of titanium, the layer of amorphous material, and the layer of titanium nitride deposited on the surface of the dielectric layer comprises planarizing the dielectric layer to remove the portions of the layer of titanium, the layer of amorphous material, and the layer of titanium nitride deposited on said portion of the surface of the dielectric layer.
- 9. The process of claim 1, wherein said depositing said layer of amorphous material comprises depositing a layer of titanium carbonitride having an amorphous structure without grain boundaries.
- 10. The process of claim 9, wherein said depositing said layer of titanium carbonitride comprises depositing a layer of titanium carbonitride having a ratio of carbon to nitrogen therein in the range of from 1:5 to 1:20.
- 11. The process of claim 1, wherein said depositing said layer of amorphous material comprises depositing a layer of substantially amorphous material without crystal grain boundaries.
CROSS REFERENCE TO RELATED APPLICATION
This application is a continuation of application Ser. No. 08/290,655, filed Aug. 15, 1994, now U.S. Pat. No. 6,093,615 issued Jul. 25, 2000.
Government Interests
This invention was made with Government support under Contract No. MDA972-93-C-0033 awarded by Advanced Research Projects Agency (ARPA). The Government has certain rights in this invention.
US Referenced Citations (14)
Foreign Referenced Citations (1)
Number |
Date |
Country |
1-266718 |
Oct 1989 |
JP |
Non-Patent Literature Citations (1)
Entry |
IBM Technical Disclosure Bulletin, vol. 35, No. 5, OCt. 1992 (Collimated Sputtering). |
Continuations (1)
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Number |
Date |
Country |
Parent |
08/290655 |
Aug 1994 |
US |
Child |
09/535050 |
|
US |