This invention relates to a method for fabricating good quality light emitting apertures of Vertical Cavity Surface Emitting Lasers (VCSELs) on wings of an Epitaxial Lateral Overgrowth (ELO) region.
There has been a lot of interest in fabricating a VCSEL which satisfies manufacturability, good quality, non-critical tolerances, best characteristics and better yield. The work done by Kuramoto et al. (APEX, 11, 112101 (2018)) on developing epitaxial distributed Bragg reflectors (DBRs), and Hamaguchi et al (APEX, 12, 044004 (2019)) on developing a curved mirror approach on the substrate side, are some examples that mention industry's interest for better quality VCSEL devices.
In the case of visible region light emitters, III-nitride materials, namely (B, Al, Ga, In)N semiconductors having the formula BwAlxGayInzN where 0≤w≤1, 0≤x≤1, 0≤y≤1, 0≤z≤1, and w+x+y+z=1, such as GaN, are required to fabricate good quality VCSELs. Alternatively, there have been approaches utilizing III-nitride templates on foreign substrates, such as Si, sapphire, etc. However, especially with devices that involve stimulated emission and smaller dimensional light emitting areas, a homogeneous epitaxy would be suggested, rather than a non-homogeneous epitaxy or hetero-epitaxy, in order to tolerate micron-level defects.
In U.S. Pat. No. 9,407,067, and US Patent Application Publication No. 2019/0173263, and in the publication Phys. Status Solidi A 2016, 213, 1170-1176, Hamaguchi et al. mentioned fabricating a light emitting element aperture on an ELO region; however, mass production and an unwanted crystal quality between the resonating length of the cavity might affect the final characteristics of the device.
Also, Hamaguchi et al. uses a curved mirror approach that still needs substrate thinning to reduce absorption loss in the cavity, which can be a difficult process to control at industrial scales. In addition, removing or thinning the substrate by chemical or mechanical polishing would be a tedious and affect yields.
In Takeshi et al. (APEX, Vol. 27, Issue 17, pp. 24717-24723 (2019)), as well as PCT International Patent Application No. PCT/US18/31293, filed on May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE,” which is cross-referenced above, a robust method was demonstrated for removing a substrate after fabricating a light emitting element on it. This method is utilized as an example to remove a substrate after making a light emitting element on it.
Nonetheless, there remains a need in the art for improved methods for fabricating VCSELs, including the resonant cavity and mirrors of the resonant cavity. The present invention satisfies this need.
To overcome the limitations in the prior art described above, and to overcome other limitations that will become apparent upon reading and understanding this specification, the present invention discloses a method for fabricating a good quality aperture for devices that emit light normal to substrates from where the devices have been epitaxially fabricated, such as VCSELs.
Specifically, this invention proposes a method for preparing good quality VCSEL device designs using a combination of epitaxial lateral overgrowth and mechanical peeling. Additionally, this invention provides away to solve yield and dead pixel problems associated in display applications, when the display applications require VCSELs for better quality and faster communications. This invention also proposes a handling method to integrate or mass produce VCSELs by assembling or packaging in terms of pre-assembled bars.
Key aspects of this invention include:
A few of the possible designs using this method are illustrated in the following description. The invention has many benefits as compared to conventionally manufacturable device elements when combined with the cross-referenced inventions on removing semiconducting devices from a semiconducting substrate set forth above.
In one embodiment, this invention performs the following steps: island-like III-nitride semiconductor layers are grown on a substrate using a growth restrict mask and an ELO method; where the growth restrict mask occupies at least 50% or more of a single device. The ELO regions are meant to be a region with reduced dislocation densities as compared to a region that is not covered by ELO. The light emitting aperture of the VCSEL is made to be confined to the wings of the ELO region, such that a good crystal quality aperture can be formed. The resonant cavity and DBR mirrors of the VCSEL device are made on the ELO region wings, and on the top and bottom of the ELO region wings, respectively.
The interface at the growth restrict mask surface and the ELO regions is smooth enough to fabricate one of the light reflecting DBR mirrors, without severe chemical treatments. The island-like III-nitride semiconductor layers are removed from the substrate and another one of the DBR mirrors is placed at the backside of the ELO III-nitride layer, which is the interface served between growth restrict mask and ELO III-nitride layer.
The method of ELO to form the island-like III-nitride semiconductor layers may include growth by metal organic chemical vapor deposition (MOCVD), hydride vapor phase epitaxy (HVPE), etc., to accurately control thickness, and thus the cavity length of the VCSEL device. The III-nitride semiconductor layers are dimensioned such that one or more of the island-like III-nitride semiconductor layers form a bar (known as a semiconductor bar or a bar of the device). By doing this, nearly identical devices can be fabricated adjacent to each other in a self-assembled array, and thus by integration, to scale up can be made easier. Alternatively, ELO III-nitride layers can made to coalesce initially, such that they can be later divided into bars of devices or individual chips.
Every device of such a bar can be addressed separately or together with other devices, by designing a proper fabrication process. For example, one could make a common cathode or anode for such a device bar for a monolithic integration or one can address individual devices for full color display applications. Consequently, a high yield can be obtained.
Moreover, the present invention can use hetero-substrates to grow the island-like III-nitride semiconductor layers that form the bar. For example, a GaN template grown on a hetero-substrate, such as sapphire, Si, GaAs, SiC, etc., can be used in the present invention.
Furthermore, the ELO method can drastically reduce dislocation density and stacking faults density, which are critical issues when using hetero-substrates.
Therefore, this invention can solve many kinds of problems incurred with the use of hetero-substrates, at the same time. For example, in a laser device, the interface between growth restrict mask and the ELO III-nitride layer can be used as a facet for the resonator.
Referring now to the drawings in which like reference numbers represent corresponding parts throughout:
In the following description of the preferred embodiment, reference is made to a specific embodiment in which the invention may be practiced. It is to be understood that other embodiments may be utilized, and structural changes may be made without departing from the scope of the present invention.
Overview
The present invention describes a method of fabricating a light emitting aperture on or above an interface for an ELO III-nitride layer and manufacturing a light emitting element according to the following steps.
Specifically, the present invention discloses a method of fabricating VCSELs that is aimed at tolerating designs for mass production and better thermal characteristics. This invention can incorporate a curved DBR mirror either on a p-side, on an n-side, or can even embed DBR designs, in addition to regular planar DBR designs.
This invention covers the following approaches:
In the following example, a process of realizing a VCSEL is described.
A growth restrict mask 102 is formed on or above the GaN-based substrate 101. Specifically, the growth restrict mask 102 is disposed directly in contact with the substrate 101 or is disposed indirectly through an intermediate layer grown by MOCVD, etc., made of III-nitride-based semiconductor deposited on the substrate 101.
The growth restrict mask 102 can be formed from an insulator film, for example, an SiO2 film deposited upon the base substrate 101, for example, by chemical vapor deposition (CVD), sputter, ion beam deposition (IBD), etc., wherein the SiO2 film is then patterned by photolithography using a predetermined photo mask and etching to include opening areas 103, as well as no-growth regions 104 (which may or may not be patterned).
Epitaxial III-nitride layers 105, such as GaN-based layers 105, are grown by ELO on the GaN substrate 101 and the growth restrict mask 102. The growth of the ELO III-nitride layers 105 occurs first in the opening areas 103, on the GaN-based substrate 101, and then laterally from the opening areas 103 over the growth restrict mask 102. The growth of the ELO III-nitride layers 105 is stopped or interrupted before the ELO III-nitride layers 105 at adjacent opening areas 103 can coalesce on top of the growth restrict mask 102. This interrupted growth results in the no-growth regions 104 between adjacent ELO III-nitride layers 105.
Additional III-nitride semiconductor device layers 106 are deposited on or above the ELO III-nitride layers 105, and may include an active region 106a, a p-type layer 106b, an electron blocking layer (EBL) 106c, and a cladding layer 106d, as well as other layers.
The ELO III-nitride layers 105 include one or more flat surface regions 107 and layer bending regions 108 at the edges thereof adjacent the no-growth regions 104. The width of the flat surface region 107 is preferably at least 5 μm, and most preferably is 30 μm or more.
The ELO III-nitride layers 105 and additional III-nitride based semiconductor device layers 106 separated by no-growth regions 104 are referred to as island-like III-nitride semiconductor layers 109, which take the shape of a bar 110. The distance between the island-like III-nitride semiconductor layers 109, which is the width of a no-growth region 104, is generally 20 μm or less, and preferably 5 μm or less, but is not limited to these values.
The growth of the island-like III-nitride semiconductor layers 109 is terminated before coalescing with its next neighbors, and by doing so, the ELO region of the island-like III-nitride semiconductor layers 109 is free of unwanted crystal defects that arise due to coalescence between next neighbors, as most of the defects originate from the opening areas 103 and will not propagate to the top surface of the island-like III-nitride semiconductor layers 109.
A light-emitting aperture of a VCSEL device 111 is processed on either side of the opening area 103, preferably between opening area 103 and the layer bending region 108, as shown in
There are many methods of removing the bar 110 containing the devices 111 from the substrate 101. For example, the present invention can utilize an ELO method for removing the bar 110 of the device 111. Generally, the ELO method is utilized to reduce the defect density in the island-like III-nitride semiconductor layers 109.
In the ELO method for removing the bar 110 of the device 111, the bonding strength between the substrate 101 and the ELO III-nitride layers 105 is weakened by the growth restrict mask 102. In this case, the bonding area between the substrate 101 and the ELO III-nitride layers 105 is the opening area 103, wherein the width of the opening area 103 is narrower than the ELO III-nitride layers 105. Consequently, the bonding area is reduced by the growth restrict mask 102, so that this method is preferable for removing the epitaxial layers 105, 106, 109.
In another embodiment, the ELO III-nitride layers 105 are allowed to coalesce to each other, as shown in
After the ELO III-nitride layers 105 coalesce at region 201 in
In one embodiment, as shown in
In one embodiment, as shown in
The typical fabrication steps for this invention are described in more detail below:
In process #1, the open region of the ELO III-nitride layer 105 is referred to as Region 1 and the region at the which the neighboring ELO III-nitride layer 105 wings meet or may not meet is referred to as Region 2:
In process #2, the removal method follows Step 4 and etches accordingly. The second process leaves open area 202 of the ELO III-nitride layers 105 un-etched. Carriers, supporting plates, receptors or recipients, are attached to divided devices 111. Alternatively, divided ELO III-nitride layers 105 can be removed by a polymer film having an adhesive attachment layer, as described below in Step 7.
In process #2, Step 6 can be performed before or after Step 4 as an open region, which is a weak connection region between the ELO III-nitride layer 105 and its growth substrate 101, keeps the layers 105 from floating away or falling apart.
After separation by either process #1 or #2, the ELO III-nitride layers 105 or the devices 111 are attached directly or indirectly to the polymer film facing an exposed interface between ELO III-nitride layer 105 and growth restrict mask 102. The interface is smooth enough to place a second DBR mirror to complete the resonant cavity of the VCSEL device 111. This is illustrated in
There are alternatives to placing a second DBR mirror onto the ELO wing interface:
These steps are explained in more detail below.
Process Steps
Step 1: Forming a Growth Restrict Mask
In one embodiment, the III-nitride layers 105 are grown by ELO on a III-nitride substrate 101, such as an m-plane GaN substrate 101, patterned with a growth restrict mask 102 comprised of SiO2, wherein the ELO III-nitride layers 105 do not coalesce on top of the SiO2.
The growth restrict mask 102 is comprised of striped opening areas 103, wherein the SiO2 stripes of the growth restrict mask 102 between the opening areas 103 have a width of 1 μm-20 μm and an interval of 30 μm-150 μm, if a nonpolar substrate 101 used the opening areas 103 are oriented along a <0001> axis. If semipolar (20-21) or (20-2-1) planes are used, the opening areas 103 are oriented in a direction parallel to [−1014] or [10-14], respectively. Other planes may be use as well, with the opening areas 103 oriented in other directions.
When using a III-nitride substrate 101, the present invention can obtain high quality III-nitride semiconductor layers 105, 106, 109, and avoid bowing or curvature of the substrate 101 during epitaxial growth due to homo-epitaxial growth. As a result, the present invention can also easily obtain devices 111 with reduced defect density, such as reduced dislocation and stacking faults.
Moreover, these techniques can be used with a hetero-substrate 101, such as sapphire, SiC, LiAlO2, Si, etc., as long as it enables growth of the ELO III-nitride layers 105 through the growth restrict mask 102.
Step 2: Growing a Plurality of Epitaxial Layers on the Substrate Using the Growth Restrict Mask
At Step 2, the III-nitride semiconductor device layers 106 are grown on the ELO III-nitride layers 105 in the flat region 107 by conventional methods. In one embodiment, MOCVD is used for the epitaxial growth of the island-like III-nitride semiconductor layers 109, including the ELO III-nitride layers 105 and the III-nitride semiconductor device layers 106. In one embodiment, the island-like III-nitride semiconductor layers 109 are separated from each other, because the MOCVD growth is stopped before the ELO III-nitride layers 105 coalesce. In another embodiment, the island-like III-nitride semiconductor layers 109 are made to coalesce and later etching is performed to remove unwanted regions.
Trimethylgallium (TMGa), trimethylindium (TMIn) and triethylaluminium (TMAl) are used as III elements sources. Ammonia (NH3) is used as the raw gas to supply nitrogen. Hydrogen (H2) and nitrogen (N2) are used as a carrier gas of the III elements sources. It is important to include hydrogen in the carrier gas to obtain a smooth surface epi-layer.
Saline and Bis(cyclopentadienyl)magnesium (Cp2Mg) are used as n-type and p-type dopants. The pressure setting typically is 50 to 760 Torr. III-nitride-based semiconductor layers are generally grown at temperature ranges from 700 to 1250° C.
For example, the growth parameters include the following: TMG is 12 sccm, NH3 is 8 slm, carrier gas is 3 slm, SiH4 is 1.0 sccm, and the V/III ratio is about 7700.
ELO of Limited Area Epitaxy (LAE) III-Nitride Layers
In the prior art, a number of pyramidal hillocks have been observed on the surface of m-plane III-nitride films following growth. See, for example, US Patent Application Publication No. 2017/0092810. Furthermore, a wavy surface and depressed portions have appeared on the growth surface, which made the surface roughness worse. This is a very severe problem when an VCSEL structure is fabricated on the surface. For that reason, it is better to grow the epitaxial layers 105, 106, 109 on a nonpolar and semipolar substrate 101, which is well known to be difficult.
For example, according to some papers, a smooth surface can be obtained by controlling an off-angle (>1 degree) of the substrate's 101 growth surface, as well as by using an N2 carrier gas condition. These are very limiting conditions for mass production, however, because of the high production costs. Moreover, GaN substrates 101 have a large fluctuation of off-angles to the origin from their fabrication methods. For example, if the substrate 101 has a large in-plane distribution of off-angles, it has a different surface morphology at these points in the wafer. In this case, the yield is reduced by the large in-plane distribution of the off-angles. Therefore, it is necessary that the technique does not depend on the off-angle in-plane distribution.
The present invention solves these problem as set forth below.
Using at least steps #1, #2 and #3 above, a bar 110 of the device 111 with a smooth surface is obtained. It is preferable that every one of steps #1, #2, #3, #4, #5, #6 and #7 above is performed.
Those results have been obtained by the following growth conditions.
In one embodiment, the growth pressure ranges from 60 to 760 Torr, although the growth pressure preferably ranges from 100 to 300 Torr to obtain a wide width for the island-like III-nitride semiconductor layers 109; the growth temperature ranges from 900 to 1200° C. degrees; the V/III ratio ranges from 1000-30,000 and more preferably 3000-10000; the TMG is from 2-20 sccm; NH3 ranges from 3 to 10 slm; and the carrier gas is only hydrogen gas, or both hydrogen and nitrogen gases. To obtain a smooth surface, the growth conditions of each plane needs to be optimized by conventional methods.
After growing for about 2-8 hours, the ELO III-nitride layers 105 had a thickness of about 8-50 μm and a bar 110 width of about 20-150 μm, wherein the bar 110 width comprises the width of the island-like III-nitride semiconductor layers 109.
Step 3: Fabricating the Device
At Step 3, the device 111 is fabricated at the flat surface region 107 by conventional methods, wherein various device 111 designs are possible, as shown in
Similarly,
The designs illustrated can also be fabricated on III-nitride layers grown by following various approaches mentioned in
In these designs, a first light reflecting mirror was designed at a designated portion of the wing regions of the ELO III-nitride layer 105 by defining a current confinement region 308 on the p-GaN side. Later, a current spreading layer 309, a contact layer, for example, ITO, is deposited on the region comprising current confinement aperture. A light reflecting DBR mirror 301 is a combination of dielectric layers with different refractive indices placed over the current confinement aperture such that contact layer lies between p-GaN and DBR. A p-pad 305 is lithographically defined.
Step 4: Forming a Structure for Separating Devices
The aim of this step is to prepare ELO III-nitride layers 105 comprising current confinement, current spreading, DBRs, p-electrode and n-electrode into the form of bars 110 or individual units of devices 111. i.e., VCSELs. By etching regions 202, 203, a bar 110 of the device 111 can be realized as shown in
As shown in
The dividing support regions 202, 203 are lines scribed by a diamond tipped scriber or laser scriber, as shown in
Both cases can divide the bar 110 into separate devices 111 at the dividing support regions 202, 203, because the dividing support regions 202, 203 are weaker than any other part. The dividing support region 202 avoids breaking the bar 110 at unintentional positions, so that it can precisely determine the device 111 length.
The vertical dividing support region 202 is created at the open area 103 surface in a manner that avoids a current injection region, which is in the light emitting structure, and the p-electrode, and the layer bending region, although it may encompass at least a portion of the current confinement layer.
As shown in
In addition, a whole bar 110 containing an array of VCSEL devices 111, or VCSEL devices 111 laying side-by-side to the open area, can be lifted as indicated in
Whole bar 110 lifting is helpful when integrating monochromatic lighting or scaling up power from individual devices 111. Alternatively, bar 110 type lifting can also be performed when polychromatic integration needed for display or any such demanding applications.
Step 5: ELO III-Nitride Layers are Removed from the Substrate.
After process #1 for removal of the ELO III-nitride layers 105, the semiconductor layers comprising the current confinement layer, currents spreading layer, DBR mirror, and electrodes are divided into individual devices 111 or a group of devices 111 together. Anchors or hookings may be placed on the individual devices 111 or a group of devices 111.
The divided semiconductor layers are then attached to a receptor or supporting plates via a bonding layer. The devices 111 are then removed from the III-nitride native substrate 101 by gently peeling. Here, the anchor material can be as same as the growth restrict mask 102 or any material that can be strong enough to hold divided devices 11 and weak enough to break when peeling is performed. Alternatively, attached devices 111 can be self-separated from the substrate 101 when the growth restrict layer 102 and anchors are dissolved, for example, using hydrofluoric acid (HF) or buffered HF (BHF) to dissolve growth restrict mask 102 and anchor layer.
A second light reflecting DBR mirror, is placed on the backside of the removed ELO III-nitride layers 105 in the wing region, on the n-GaN side, at an interface between the growth restrict mask 102 and ELO III-nitride layers 105. Then, n-pads are deposited to contact the n-GaN layer. On a few designs, the n-pads are placed on the opposite side of the interface.
During process #2 for removal of the ELO III-nitride layers 105, in Step 4, etching Region 1202 can be avoided when process #2 is performed, and then skip to Step 5.
Step 6: Dissolving the Growth Restrict Mask by Wet Etching
The method may further comprise a step of removing, by dissolving using a wet etchant, at least a portion of, or preferably almost all of, or most preferably all of, the growth restrict mask 102.
The growth restrict mask 102 is removed using a chemical solution, such as HF or BHF. This allows the devices 111 to be easily removed from the substrate 101. This process would better be conducted before removing the III-nitride layers 105, 106, 109 from substrate 101. This step can also be conducted before processing the device 111 in Step 3 or during Step 3.
Step 7: Removing the Devices from the Substrate
From here, the procedure for removing the bar 110 of devices 111 is explained. Specifically.
Step 7.1 comprises attaching a polymer film 1201 to the bar 110 of the device 111. In this embodiment, the polymer film 1201 is comprised of a base film, an adhesive and a backing film. Preferably, the polymer film 1201 with the adhesive attachment is sensitive to UV energy, so that later detachment of the devices 111 from the film 1201 can be realized in a UV controlled environment.
Step 7.2 comprises applying pressure to the polymer film 1201 and the substrate 101. The aim of applying pressure is to put the polymer film 1201 in-between the bars 110 of the devices 111 or in between carrier (supporting) plates, 1202. The polymer film 1201 is softer than the bars 110 of the devices 111, so the polymer layer 1201 can easily surround the bars 110 and/or carrier plates 1202 of the devices 111. Preferably, the polymer film 1201 is heated in order to soften it, which makes it easy for the polymer film 1201 to cover the bars 110 of the devices 111 and/or carrier plates 1202.
Step 7.3 comprises reducing the temperature of the polymer film 1201 and the substrate 101, while maintaining the applied pressure. It is not necessary to apply pressure during the changing of the temperature.
Step 7.4 comprises utilizing the differences in thermal coefficients between the polymer film 1201 and the substrate 101 for removing the bars 110 of the devices 111. The polymer film 1201 shrinks as the temperature decreases. As a result, the bottom of the polymer film 1201 is lower than the top of the carrier plates 1202 or bars 110 of the devices 111.
The polymer film 1201 can apply the pressure in the horizontal direction at side facets of the bars 110 of the devices 111, exposing cleaving points 1203 and tilting the bars 110 of the devices 111 downward obliquely. This pressure applied from the side facets allows the bars 110 of the devices 111 to be effectively removed from the substrate 101. During low temperature, the polymer film 1201 maintains the applied pressure from the top of the polymer film 1201 to the bars 110 of the devices 111.
Various methods may be used to reduce the temperature. For example, the substrate 101 and the polymer film 1201 can be placed into liquid N2 (for example, at 77° K) at the same time while applying pressure. The temperature of the substrate 101 and the polymer film 1201 can also be controlled with a piezoelectric transducer.
When reducing the temperature, the substrate 101 and the polymer film 1201 may be wetted by atmospheric moisture. In this case, the temperature reduction can be conducted in a dry air atmosphere or a dry N2 atmosphere, which avoids the substrate 101 and the polymer film 1201 getting wet.
Thereafter, the temperature increases, for example, to room temperature, and the pressure is no longer applied to the polymer film 1201. At that time, the bars 110 of the devices 111 have already been removed from the substrate 101, and the polymer film 1201 is then separated from the substrate 101. When using a polymer film 1201, especially a polymer film 1201 having adhesive, the bars 110 of the devices 111 can be removed using the polymer film 1201 in an easy and quick manner.
There may be an occasion having a different height among the bars 110 of the devices 111, depending on a growth condition. In this case, the removal method with the polymer film 1201 is good at removing the different height bars 110 of the devices 111, because these films 1201 are flexible and soft.
Alternatively, above procedure can be realized when the carrier or supporting, plates 1202 have a finger-like structure.
Step 8: Fabricating a Second Light Reflecting DBR Mirror
Removed bars 110 of the devices 111 have a back surface that is an interface between the ELO III-nitride layer 105 and the growth restrict mask 102. The interface is formed by allowing epitaxial layers to grow laterally from open region 103 of the substrate 101. Surface morphology at the ELO interface, between the ELO III-nitride layer 105 and growth restrict mask 102, can be controlled by parameters of the growth restrict mask 102 and growth parameters of the ELO III-nitride layer 105.
The dependency of surface morphology on the growth restrict mask 102 dependency is illustrated in
Case 1: A thinner growth restrict mask 102, for example, a thickness of 10 nm-50 nm, may deteriorate at higher MOCVD growth temperatures while performing epitaxial lateral overgrowth. Thus, producing non-controllable open areas 901 in the growth restrict mask 102. These non-controllable open areas 901 can be refilled along with the pre-determined open area 103 during the epitaxial lateral overgrowth resulting in connecting paths between the substrate 101 and the ELO III-nitride layers 105. The diffused epitaxial layers at these non-controllable open areas 901 may comprise a rough region interface 902 at the backside of the device 111 when bars 110 of the devices 111 are removed. In this case, the yield having a smooth interface surface at the removed ELO III-nitride layer 105 wing may be reduced.
Case 2: A thicker growth restrict mask 102, for example, a thickness of 100 nm-1000 nm, or more typically 1000 nm, can restrict a deteriorated region to within the growth restrict mask 102, such as damage region 903, at higher MOCVD growth temperatures while performing epitaxial lateral overgrowth. Thus, non-controllable open areas 901 can be eliminated by increasing the growth restrict mask 102 height, which translates to a better interface 904 between the ELO III-nitride layer 105 and the growth restrict mask 102. An increased aspect ratio (thickness/width) at the breaking point due to thicker growth restrict mask 102 will ease the removal of bars 110 of the devices 111 as an added advantage.
Case 3: Alternatively, instead of a thicker growth restrict mask 102, a combination of growth restrict masks 905 will also function as Case 2. One growth restrict mask 102 for easy liftoff, for example, SiO2 and another growth restrict mask 102 for stability at higher temperature, for example, SiN, can be deposited as a combined growth restrict mask 102. A combined thickness of 100 nm-1000 nm or more is preferred, and typically 1000 nm. By choosing a thermally stable growth restrict mask 102 at the interface of the ELO III-nitride layers 105, a better surface 906 for removing the bars 110 of devices 111 can be obtained.
To obtain a smooth interface at the removed ELO III-nitride layer 105 back surface and a higher yield, a thicker growth restrict mask 102 or multiple layers for the growth restrict mask 102 are more preferable than a thinner growth restrict mask 102.
A proof of concept study for the results of the above cases are presented in
As can be seen in
After removing bars 110 of devices 111, mesas are etched and a second light reflecting mirror 313 is defined by aligning with the first light reflecting layer, as shown in
Preferably, DBR mirror layers for the resonant cavity of the VCSEL device 111 are displaced away from the open region, for example, more than 1-2 μm away, in order to reduce effects on performance of the VCSEL of unwanted crystal quality near the ELO III-nitride layer 105 bending shape from the open region.
Alternatively, a pre-fabricated DBR mirror can be attached onto the removed ELO bars 110 of devices 111 by surface activation bonding or some other diffusion bonding mechanisms. The external DBR mirrors that are being attached can be of epitaxial in nature to improve thermal performance of the devices 111.
The surface shown in the image is an N-polar surface, which, in principle, when exposed to chemicals, such as potassium hydroxide (KOH), will become rough. For example, when photoelectric chemical etching method is used to remove Ga-polar semiconductor layers, the surface which is exposed to the chemicals cannot be used to make DBR mirrors. In this method, the as-grown ELO III-nitride layers 105 on the growth restrict mask 102 are used to make the DBR mirrors.
The images shown included magnified images of the back (interface) surface viewed through a laser microscope, scanning electron microscope (SEM) images, and images from atomic force microscopy (AFM) conducted on one of the back surfaces. The surface roughness was found to be from sub-nanometer to 1 or 2 nanometers, which are best for placing a second DBR mirror to complete a resonant cavity of a VCSEL device 111.
The images shown include a back surface of the ELO III-nitride layers 105 on the polymer film. The surface shown in the image is a back surface of the 20-21 surface, which, in principle, when exposed to chemicals like KOH will become rough. For example, when photoelectric chemical etching method is used to remove Ga-polar semiconductor layers, the surface which is exposed to the chemicals used in this method will back the worse interface. The degree of roughness increases with increasing nitrogen polarity of the exposed surface to the chemicals. The interfaces are useful for making DBR mirrors. In this method, the as-grown ELO III-nitride layers 105 on the growth restrict mask 102 are used to make the DBR mirrors.
The images include magnified images of the back (interface) surface viewed through a laser microscope, SEM images and AFM images conducted on one of the back surfaces, particularly on a wing region. The surface roughness was found to be from sub-nanometer to a few nanometers, which are best for placing a second DBR mirror to complete a resonant cavity of a VCSEL device 111.
Similarly,
The images include magnified images of the back (interface) surface viewed through a laser microscope, SEM images, and AFM images conducted on one of the back surfaces, particularly on a wing region. The surface roughness was found to be from sub-nanometer to a few nanometers, which are best for placing a second DBR mirror to complete a resonant cavity of a VCSEL device 111.
These images include magnified images of the back (interface) surface viewed through a laser microscope and AFM images conducted on one of the back surfaces, particularly on a wing region. The AFM results indicate the surface roughness of the ELO wings when they lie on SiO2 and SiN, respectively. On the SiN surface, the ELO III-nitride layers 105 have finer grain structure as compared to ELO III-nitride layers 105 on the SiO2 surface. The surface roughness was found to be from sub-nanometer to a few nanometers, which are best for placing a second DBR mirror to complete a resonant cavity of a VCSEL device 111.
As explained above, the growth restrict mask 102 may have an influence on the back surface. However, controlling the interface when chemicals are not involved is a much simpler way of doing things than chemically or mechanically polishing, or photo-electro-chemical etching. Preferably, using thicker growth restrict masks 102 and/or multiple growth restrict masks 102, yields at the interfaces can be improved.
Alternatively, placing metal-layers on top of growth restrict mask 102, which can withstand the temperatures used for forming ELO III-nitride layers 105, may give a mirror-like finish at the interface of the removed ELO III-nitride layers 105. The backside interface of the removed ELO III-nitride layers 105 at the wing regions can later be used to place a second DBR mirror for the resonant cavity of the VCSEL.
This invention helps in obtaining better crystal quality and smoother surfaces for DBR mirrors of the resonant cavity of VCSEL devices 111. Also, this approach is independent of crystal orientation, whereas other techniques are either tedious, chemically sensitive to crystal orientations, or less tolerances for mass production.
The essence of this invention lies not only in using ELO technology to obtain better quality crystal device layers 106, and smooth interfaces for DBR mirrors of the resonant cavity, but also to control cavity thickness and recycle expensive host substrates 101, for example, III-nitride substrates 101.
Step 9: Fabricating an n-Electrode at the Separate Area of the Device
After removing the bar 110 or devices 111 from the substrate 101, the bar 110 remains attached to a carrier, which is shown with the bar 110 positioned in an upside-down manner, as shown in
Then, the n-electrode 1401 is deposited on the back side of the device 111 after removing the bar 110 from the substrate 101. The n-electrode 1401 preferably includes the step-like feature 1402. The step-like feature 1402 may not exposed to robust environments during process #2 and is in intact with the host substrate 101 until its separation, which would make a good surface condition for the n-electrode 1401 for obtaining low contact resistivity. The area 1402 is not exposed in process #2 until the bar 110 or devices 111 are removed from its host substrate 101. A second light reflecting DBR mirror 313 is preferably placed away from the step-like feature 1402 edge, for example, at least more than 1-2 μm, to benefit the better crystal quality for the VCSEL devices 111. Therefore, using step-like feature 1402, the yield of VCSEL devices 111 can be increased as the n-electrode 1401 of the device 111 can find a space which may not be useful for the resonant cavity structure.
Alternatively, the n-electrode 1401 also can be disposed on the top surface of the bar 110 or devices 111, which is a surface made for a p-electrode 305.
Typically, the n-electrode 1401 is comprised of the following materials: Ti, Hf, Cr, Al, Mo. W, Au. For example, the n-electrode may be comprised of Ti—Al—Pt—Au (with a thickness of 30-100-30-500 nm) but is not limited to those materials. The deposition of these materials may be performed by electron beam evaporation, sputter, thermal heat evaporation, etc.
When process #2 is used to remove ELO III-nitride layers 105 from the host substrate 101, a bar 110 of devices 111 with ELO wings having a step-like feature 1402 lying in-between can be lifted onto a carrier or a polymer film. The possible device 111 configurations in this case span the same range as depicted in
Step 10: Breaking the Bar into Separate Devices
After disposing the n-electrode, each bar 110 is divided into a plurality of devices 111, as shown in
The dividing support region 1501 helps divide the bar 110 into the individual devices 111, as shown in
Step 11: Mounting Each Device on a Heat Sink Plate
After Step 8, the divided bar 110 is lifted using one of three approaches: (1) attaching a polymer film 1201 to the bars 110 of devices 111 as shown in
In one embodiment, the polymer film 1201 is a UV light-sensitive dicing tape that is exposed to UV light, which can reduce the adhesive strength of the film 1201. This makes it easy to remove the devices 111 from the film 1201.
In this step, a heat sink plate 1601 comprised of AlN is prepared. An Au—Sn solder 1602 is disposed on the heat sink plate 1601, the heat sink plate 1601 is heated over the melting temperature of the solder 1602, and the devices 111 on the polymer film 1201 are bonded to the heat sink plate 1601 using the Au—Sn solder 1602. The devices 111 can be mounted on the heat sink plate 1601 in two ways: (1) n-electrode 1401 side down or (2) p-electrode 305 side down, depending on which is exposed as the light emitting side.
Step 12: Dividing the Heat Sink Plate
As shown in
Mass Transfer for Display Applications
Method 1
This invention provides a solution to the problem of mass transferring of smaller light emitting apertures, alternatively called as emissive inorganic pixels, when targeted sizes are below 50 μm.
VCSELs devices 111, fabricated on the ELO III-nitride layers 105, can be removed as mentioned above. In particular, these devices 111 preferably have larger ELO wing regions and smaller open areas 103, that is a ratio between the wing region and open area 103 should be more than 1, more preferably 5-10, and in particular, open areas 103 should be around 1-5 μm. Therefore, devices 111 can be removed from the III-nitride substrate 101 more easily and can be transferred to external carriers or processed in further steps in an easy manner.
The devices 111 are shown in
The devices 111 of interest can be a bar 110 of devices 111 having VCSEL devices 111 on either side of the open area 103 or single VCSEL devices 111 on one of the ELO wings. For example,
Individual devices 111 as shown in
The JNH stamp 2002 may transfer adjacent devices 111, e.g., every x device 111, as shown in
In a simple rough estimation, for example, when typical device 111 dimensions of 40 μm×40 μm with a pitch 20 μm are considered, a stamp 2002 may accommodate 333 devices 111 lengthwise and 333 breadthwise. Therefore, at least 100000 devices 111 may be transferred in a minute (which can be made faster with advanced instrumentation).
Also, a micro-LED display transfer process can be easily adopted to this transfer process, as shown in
Process #1 and process #2 both have the potential to meet industrial standards when the removing process and fabrication techniques are adopted for both VCSEL devices 111 and micro LED devices 111.
Advantages of this method include the following:
Method 2
The bars 110 of devices 111 are removed onto the UV sensitive polymer film 2201 and then are integrated onto a functional back panel 2204, for example, thin film transistor, integrated back panel, or CMOS circuits back panel, having electrical pads 2205 or other components. The bars 110 of devices 111 on the UV sensitive polymer film 2201 are bombarded by the pulsed UV laser 2202 from the back side of the polymer film 2201 while bringing the functional back panel 2204 to their proximity.
III-Nitride-Based Substrate
The III-nitride-based substrate 101 may comprise any type of III-nitride-based substrate, as long as a III-nitride-based substrate enables growth of III-nitride-based semiconductor layers 105, 106, 109 through a growth restrict mask 102, any GaN substrate 101 that is sliced on a {0001}, {11-22}. {1-100}, {20-21}, {20-2-1}, {10-11}, {10-1-1} plane, etc., or other plane, from a bulk GaN, and AlN crystal substrate.
Hetero-Substrate
Moreover, the present invention can also use a hetero-substrate 101. For example, a GaN template or other III-nitride-based semiconductor layer may be grown on a hetero-substrate 101, such as sapphire, Si, GaAs, SiC, etc., prior to the growth restrict mask 102. The GaN template or other III-nitride-based semiconductor layer is typically grown on the hetero-substrate 101 to a thickness of about 2-6 μm, and then the growth restrict mask 102 is disposed on the GaN template or other III-nitride-based semiconductor layer.
Growth Restrict Mask
The growth restrict mask 102 comprises a dielectric layer, such as SiO2, SiN, SiON, Al2O3, AlN, AlON, MgF, ZrO2, etc., or a refractory metal or precious metal, such as W, Mo, Ta, Nb, Rh, Ir, Ru, Os, Pt, etc. The growth restrict mask 102 may be a laminate structure selected from the above materials. It may also be a multiple-stacking layer structure chosen from the above materials.
In one embodiment, the thickness of the growth restrict mask 102 is about 0.05-3 μm. The width of the mask is preferably larger than 20 μm, and more preferably, the width is larger than 40 μm. The growth restrict mask 102 is deposited by sputter, electron beam evaporation, plasma-enhanced chemical vaper deposition (PECVD), ion beam deposition (IBD), etc., but is not limited to those methods.
On an m-plane free standing GaN substrate 101, the growth restrict mask 102 comprises a plurality of opening areas 103, which are arranged in a first direction parallel to the 11-20 direction of the substrate 101 and a second direction parallel to the 0001 direction of the substrate 101, periodically at intervals extending in the second direction. The length of the opening area 103 is, for example, 200 to 35000 μm; the width is, for example, 2 to 180 μm; and the interval of the opening area 102 is, for example, 20 to 180 μm. The width of the opening area 103 is typically constant in the second direction but may be changed in the second direction as necessary.
On a c-plane free standing GaN substrate 101, the opening areas 103 are arranged in a first direction parallel to the 11-20 direction of the substrate 101 and a second direction parallel to the 1-100 direction of the substrate 101.
On a semipolar (20-21) or (20-2-1) GaN substrate 101, the opening areas 103 are arranged in a direction parallel to [−1014] and [10-14], respectively.
Alternatively, a hetero-substrate 101 can be used. When a c-plane GaN template is grown on a c-plane sapphire substrate 101, the opening area 103 is in the same direction as the c-plane free-standing GaN substrate 101; when an m-plane GaN template is grown on an m-plane sapphire substrate 101, the opening area 103 is same direction as the m-plane free-standing GaN substrate 101. By doing this, an m-plane cleaving plane can be used for dividing the bar 110 of the device 111 with the c-plane GaN template, and a c-plane cleaving plane can be used for dividing the bar 110 of the device 111 with the m-plane GaN template; which is much preferable.
III-Nitride-Based Semiconductor Layers
The ELO III-nitride layers 105, the III-nitride semiconductor device layers 106 and the island-like III-nitride semiconductor layers 109 can include In, Al and/or B, as well as other impurities, such as Mg, Si, Zn, O, C, H, etc.
The III-nitride-based semiconductor device layers 106 generally comprise more than two layers, including at least one layer among an n-type layer, an undoped layer and a p-type layer. The III-nitride-based semiconductor device layers 106 specifically comprise a GaN layer, an AlGaN layer, an AlGaInN layer, an InGaN layer, etc. In the case where the device 111 has a plurality of III-nitride-based semiconductor layers, the distance between the island-like III-nitride semiconductor layers 109 adjacent to each other is generally 30 μm or less, and preferably 10 μm or less, but is not limited to these figures. In the semiconductor device 111, a number of electrodes according to the types of the semiconductor device 111 are disposed at predetermined positions.
Epitaxial Lateral Overgrowth
The crystallinity of the island-like III-nitride semiconductor layers 109 grown using ELO upon the growth restrict mask 102 from a striped opening are 103 of the growth restrict mask 102 is very high.
Furthermore, two advantages may be obtained using a III-nitride-based substrate 101. One advantage is that a high-quality island-like III-nitride semiconductor layer 109 can be obtained, such as with a very low defects density, as compared to using a sapphire substrate 101.
Another advantage in using a similar or the same material for both the epilayer 109 and the substrate 101, is that it can reduce strain in the epilayer 109. Also, thanks to a similar or the same thermal expansion, the method can reduce the amount of bending of the substrate 101 during epitaxial growth. The effect, as above, is that the production yield can be high, in order to improve the uniformity of temperature.
The use of a hetero-substrate 101, such as sapphire (m-plane, c-plane), LiAlO2, SiC, Si, etc., for the growth of the epilayers 105, 106, 109 is that these substrates are low-cost substrates. This is an important advantage for mass production.
When it comes to the quality of the device 111, the use of a free standing III-nitride-based substrate 101 is more preferable, due to the above reasons. On the other hand, the use of a hetero-substrate 101 makes it easy to remove the III-nitride-based semiconductor layers 105, 106, 109, due to a weaker bonding strength at the cleaving points.
Also, when a plurality of island-like III-nitride semiconductor layers 109 are grown, these layers 109 are separated from each other, that is, are formed in isolation, so tensile stress or compressive stress generated in each of the island-like III-nitride semiconductor layers 109 is limited within the layers 109, and the effect of the tensile stress or compressive stress does not fall upon other III-nitride-based semiconductor layers.
Also, as the growth restrict mask 102 and the ELO III-nitride layers 105 are not bonded chemically, the stress in the ELO III-nitride layers 105 can be relaxed by a slide caused at the interface between the growth restrict mask 102 and the ELO III-nitride layers 105.
Also, the existence of gaps between each the island-like III-nitride semiconductor layers 109, as shown by no-growth region 104 in
Therefore, even if a slight warpage, curvature, or deformation occurs in the substrate 101, this can be easily corrected by a small external force, which avoids the occurrence of cracks. As a result, the handling of substrates 101 by vacuum chucking is possible, which makes the manufacturing process of the semiconductor devices 111 more easily carried out.
As explained, island-like III-nitride semiconductor layers 109 made of high quality semiconductor crystal can be grown by suppressing the curvature of the substrate 101, and further, even when the III-nitride-based semiconductor layers 105, 106, 109 are very thick, occurrences of cracks, etc., can be suppressed, and thereby a large area semiconductor device 111 can be easily realized.
Flat Surface Region
The flat surface region 107 is between layer bending regions 108. Furthermore, the flat surface region 107 is in the region of the growth restrict mask 102.
Fabrication of the semiconductor device 111 is mainly performed on the flat surface region 107. The width of the flat surface region 107 is preferably at least 5 μm, and more preferably is 10 μm or more. The flat surface region 107 has a high uniformity of thickness for each of the semiconductor layers 105, 106, 109 in the flat surface region 107.
Layer Bending Region
If the layer bending region 108 that includes an active layer 106a remains in the VCSEL device 111, the laser mode may be affected by the layer bending region 108 due to a low refractive index (e.g., an InGaN layer). As a result, it is preferable to remove at least a part of the active layer 106a in the layer bending region 108 by etching.
The emitting region formed by the active layer 106a is a current injection region. In the case of a VCSEL 111, the emitting region is a resonant cavity aperture structure vertically above p-side or below n-side or vice versa.
For the VCSEL, the edge of the emitting region should be at least 1 μm or more from the edge of the layer bending region 108, and more preferably 5 μm.
From another point of view, an epitaxial layer of the flat surface region 107 except for the opening area 103 has a lesser defect density than an epitaxial layer of the opening area 103. Therefore, it is more preferable that the aperture structures should be formed in the flat surface region 107 including on a wing region.
Semiconductor Device
The semiconductor device 111 is, for example, a Schottky diode, a light-emitting diode, a semiconductor laser, a photodiode, a transistor, etc., but is not limited to these devices 111. This invention is particularly useful for VCSELs. This invention is especially useful for a semiconductor laser which require smooth regions for cavity formation.
Polymer Film
The polymer film 1201 is used in order to remove the island-like III-nitride semiconductor layers 109 from the III-nitride-based substrate 101 or the GaN template used with the hetero-substrate 101. In the present invention, dicing tape, including UV-sensitive dicing tape, which are commercially sold, can be used as the polymer film 1201. For example, the structure of the polymer film 1201 may comprise triple layers or double layers, but is not limited to those examples. The base film material, for example, having a thickness of about 80 μm, may be made of polyvinyl chloride (PVC). The backing film material, for example, having a thickness of about 30 μm, may be made of polyethylene terephthalate (P.E.T.). The adhesive layer, for example, having a thickness of about 15 μm, may be made of acrylic UV-sensitive adhesive.
When the polymer film 1201 is a UV-sensitive dicing tape and is exposed to UV light, the stickiness of the film 1201 is drastically reduced. After removing the island-like III-nitride semiconductor layers 109 from the substrate 101, the polymer film 1201 is exposed by the UV light, which makes it is easy to remove.
Heat Sink Plate
As noted above, the removed bar 110 may be transferred to a heat sink plate 1701, which may be AlN, SiC, Si, Cu, CuW, and the like. As shown in
In the case of bonding devices 111 to the heat sink plate 1701, the size of the heat sink plate 1701 does not matter, and it can be designed as desired.
Light-Reflecting DBR Mirror
The light reflecting layer mentioned in this invention is also referred to as a dielectric DBR mirror. The DBR mirror is comprised of, for example, a semiconductor multilayer film or a dielectric multilayer film. Examples of a dielectric materials include but not limited to Si, Mg, Al, Hf, Nb, Zr, Sc, Ta, Ga, Zn, Y, B, Ti, etc., or nitrides of these elements, like SiN, AlN, AlGaN, GaN, BN, etc., or oxides of these elements, like SiOx, TiOx, NbOx, ZrOx, TaOx, ZnOx, AlOx, HfOx, SiNx, AlNx, etc. The light reflecting layer can be obtained by alternatively laminating one or more dielectric materials having different refractive indices. The materials of different refractive indices, different thickness and various number of material layers chosen to obtain desired light reflectance. The thickness of each film of dielectric layer can be adjusted depending on the material and the oscillation wavelength of the emitted light from the resonant cavity.
Preferably, the thickness of these layers as odd multiples of a quarter of oscillation wavelengths. The reflectance of the two light reflective elements, one on the top and one on the bottom are different. These two lights reflecting elements including active layer, n-GaN layer and part of p-GaN layer collectively called as a resonant cavity. In general light emitting side of the device's light reflecting layer reflectance is smaller than the other side.
Current Confinement Region
The resonant cavity can be created by shaping current flowing through the VCSEL device 111 narrow enough to confine within the diameter of the resonant cavity of the aperture. This can be achieved by making the layers around the aperture where the current injection takes place more conductive than its neighborhood. For example, either using reactive ion etching or plasma etching, or dielectric masks, the neighboring region of the aperture can be made resistive.
A III-nitride-based semiconductor device 111 and a method for manufacturing thereof, according to a first embodiment are explained.
In the first embodiment, as shown in
In this embodiment, the island-like III-nitride semiconductor layers 109 are largely uniform with a very smooth surface. Thereafter, as shown in
The bar 110 of devices 111 containing the island-like III-nitride semiconductor layers 109 are removed using process #1 or process #2. The second light reflecting mirror is placed on the back region at the interface between the growth restrict mask 102 and the ELO III-nitride layer 105 interface, and then an n-electrode is defined, depending on the device 111 design as explained in
First, the island-like III-nitride semiconductor layers 109 are removed from the free standing GaN substrate 101. The freestanding GaN substrate 101 has a lot of defects, such as dislocations and stacking faults. However, only exposing a small region for epitaxial growth and allowing the epitaxial layers to relax on wing regions which have no direct contact with III-nitride substrate 101 vertically, one can realize a less defect regions for light emitting apertures. Moreover, the island-like III-nitride semiconductor layers 109 are made by MOCVD, so they have an extremely high crystal quality.
Second, the width of the open region and the height of the breaking area are very narrow and short, which causes epitaxial layers to be easily removed. The width is about 1-5 μm, and the height is about 5-180 μm. The island-like semiconductor layers 109 is processed by Steps 1-13 of the method set forth above, in order to obtain VCSELs.
When a non-coalesced stripe-like pattern approach is chosen to fabricate VCSEL devices 111 as discussed for semipolar and nonpolar ELO III-nitride layers 105, unlike the polar ELO III-nitride layers 105, the ELO III-nitride layers 105 of nonpolar and semipolar tend to form an aspect ratio with not much space to fabricate an entire VCSEL cavity and its electrode pads, for example, as illustrated in
This method is advantageous for obtaining smooth interfaces for fabricating DBR mirrors of a VCSEL device 111. General approaches like thinning substrate 101 or removing semiconductor layers by photo electrical etching for fabricating DBR mirrors is tedious and crystal orientation dependent. However, this approach is robust and crystal plane independent. Substrates 101 that are used to produce device layers 106 can be recycled several times for similar fabrication. The approach of this invention not only provides a smooth crystal interface for DBR mirrors, but also a good crystal quality device 111, as this invention proposes fabricating a resonant cavity completely on the ELO III-nitride layers 105 wing. Preferably, this does not include the open region of the substrate 101 from where the device layers 106 are grown.
In a second embodiment, ELO III-nitride layers 105 on the III-nitride substrate 101 are made to coalesce as shown in
The third embodiment is similar to the first and second embodiments for designing VCSEL devices 111, except for shaping a III-nitride substrate 101 surface which in previous embodiments was covered by a planar growth restrict mask 102. The growth restrict mask 102, the shape of which later serves as an interface for placing a second DBR, can be shaped either as a finite radius curve having a center of curvature away from the surface of the host substrate 101 or as a rectangular/tapered vessel surface as shown in
Throughout this invention, device 111 designs are displayed using a cross-sectional view even though their actual representation should be best presented with a top view stripe structure illustrated. One of such glimpses was given in
Alternatively, this embodiment can also be practiced on a III-nitride substrate 101 having a highly doped III-nitride semiconductor layer 301.
Once the host substrate 101 is patterned as desired, ELO III-nitride layers 105 formed from the open region adopt the shape of the growth restrict mask 102 by leaving a smooth interface between the growth restrict mask 102 and ELO III-nitride layers 105. In particular, the patterned shape on the host substrate 101 serves as a wing of ELO III-nitride layer 105.
Once the desired ELO III-nitride layers 105 and semiconducting device layers 106 are formed, VCSEL device 111 processes are performed similar to those mentioned above. The ELO III-nitride layers 105 are removed from the host substrate 101 either by process #1 or process #2. A second DBR mirror of the resonant cavity of VCSEL is placed at the interface.
The fourth embodiment uses process #2 and lifting devices 111 in pairs. For example, devices 111 are divided such that each unit contains two devices 111, one on each wing of the ELO III-nitride layers 105 separated by the open region.
In a fifth embodiment, ELO can be performed at least two times, as shown in
For example, in the design shown in
This design can have several alterations, like using III-nitride semiconductor layers 105 for heat extraction or can thin them to avoid light emitting cone interference, or can open the p-side electrode pattern to allow light to emit by closing the n-side electrode structure, etc.
When process #2 is followed, a device 111 that was removed from the host substrate 101 can be carefully engineered to have two resonant cavities, one on each side wing of the open region, as shown in
In a sixth embodiment, AlGaN layers are used as the island-like III-nitride semiconductor layers 109. The AlGaN layers may be grown as an ELO III-nitride layer 105 on various off angle substrates 101, with an Al composition set to be 0.03-0.05. The AlGaN layers 109 can have a very smooth surface using the present invention. Using the present invention, the AlGaN layers 109 can be removed, as the island-like III-nitride semiconductor layers 109, from various off angle substrates 101.
In a seventh embodiment, an ELO III-nitride layer 105 is grown on various off angle substrates 101. The off-angle orientations range from 0 to +15 degrees and 0 to −28 degrees from the m-plane towards the c-plane. The present invention can remove the bar 110 from the various off-angle substrates 101 without breaking the bars 110. When various crystal plane substrates 101 are used, the removed region of the bar 110 at the open area may process the cleaved surfaces like the staircase when bar 110 is removed mechanically, making the open area unsuitable for fabricating DBR mirrors for VCSEL devices 111; however, independent of crystal orientation, the surface on the bar's removed wing regions are smooth enough to fabricate such delicate DBR mirrors for VCSEL devices 111. For example, when a semi-polar bar 110 is removed from its host semi-polar plane, 20-2-1 or 20-21, the open region of the removed portion of the bar 110 may contain a cleaved non-polar plane, 10-10 or the like, which is at an angle of 75 or 15 degrees from the host semi-polar plane, and which looks like a staircase pattern at the open region, as shown in
In an eighth embodiment, an ELO III-nitride layer 105 is grown on c-plane substrates 101 with two different mis-cut orientation. The island-like III-nitride semiconductor layers 109 are removed after processing a desired device 111.
In a ninth embodiment, a sapphire substrate 101 is used as the hetero-substrate. This structure is almost the same as the first embodiment's structure, except for using the sapphire substrate 101 and a buffer layer. In this embodiment, the buffer layer may also include an additional n-GaN layer or undoped GaN layer. The buffer layer is grown at a low temperature of about 500-700° C. degrees. The n-GaN layer or undoped GaN layer is grown at a higher temperature of about 900-1200° C. degrees. The total thickness is about 1-3 μm. Then, the growth restrict mask 102 is disposed on the buffer layer and the n-GaN layer or undoped GaN layer. The rest of process to complete the device 111 is the same as the first to fourth embodiments.
On the other hand, it is not necessary to use the buffer layer. For example, the growth restrict mask 102 can be disposed on the hetero-substrate 101 directly. After that, the ELO III-nitride layer 105 and/or III-nitride-based semiconductor device layers 106 can be grown. In this case, the interface between the hetero-substrate 101 surface and the bottom surface of the ELO III-nitride layer 105 divides easily due to the hetero-interface, which includes a lot of defects.
Employing the present invention, smooth interfaces of the ELO III-nitride layer 105 can be obtained for a resonant cavity, even using the hetero-substrate 101, because a wing region of the ELO III-nitride layer's 105, and an interface between the growth restrict mask 102 and the ELO III-nitride layer 105, are used as resonant cavity mirrors in the device 111.
The use of the hetero-substrate 101 also has a large impact for mass production. For example, the hetero substrate 101 used can be a low cost and large size substrate 101, such as sapphire, GaAs and Si, as compared to a free standing GaN substrate 101. This results in low cost devices 111. Moreover, sapphire and GaAs substrates are well known as low thermal conductivity materials, so devices 111 using these substrates have thermal problems. However, using the present invention, since the device 111 is removed from the hetero-substrate 101, it can avoid these thermal problems.
Furthermore, in the case using the ELO growth method for removing the bar 110 of the device 111, this method can reduce drastically dislocation density and stacking faults density, which has become a critical issue in the case of using hetero-substrates 101.
Therefore, this invention can solve many of the problems resulting from the use of hetero-substrates 101.
A tenth embodiment removes the ELO III-nitride layers 105 using a secured delicate hook, which temporarily holds the ELO III-nitride layers 105 and releases them onto a either temporary carrier substrate or permanently bonding to a substrate. CMOS panel, or TFT back panel. Using ELO technique larger wings can be obtained, on these wings several devices 111 like, VCSELs, LEDs, power electronic devices can be fabricated. By doing so these devices 111 own a unique feature of reduced defects compared to devices 111 fabricated from conventional substrates.
This is described in
This process may be performed after finishing all the front-end processes on coalesced or discrete ELO III-nitride layers 105. For example, in the case of small size LEDs, the operating device 111 designed on the ELO wing includes p-electrode and n-electrodes on the III-nitride semiconducting layers 109 top side. The 701 mask used for etching the III-nitride layers 109 on the host substrate 101 can also be served as a passivation layer to protect from electrical leaks or improve efficiencies for small sized LEDs.
Using a mask 701, typically SiO2, the desired chip dimensions are etched down at least to expose the growth restrict mask 102. Then, in Type-2 etching, a hook layer 702 is placed to contact the exposed growth restrict mask 102. Alternatively, the hook layer 702 may contact the host substrate 101 at the open ELO window. Also, the process of etching III-nitride semiconducting layers 109 down to expose the underlying growth restrict mask 102 can be done in two steps, for example, in the case of thicker III-nitride semiconducting layers 109, >10 μm, a hard mask 701 is used first to etch to slightly above the growth restrict mask 102, so that the underlying growth restrict mask 102 is not exposed at this time; then, in the second step, a soft mask 701, like the photoresist, is used to at least expose the underlying growth restrict mask 102. This configuration leads to one of the hooking 702 designs, Pattern 1 named in Type-2 etching. It may also be possible using only either a hard mask 701 and/or soft mask 701 that the underlying growth restrict mask 102 can be exposed without a two-step etching process.
In Type-2 etching, after exposing the underlaying growth restrict mask 102, the etched layers possess no support from the host substrate 101, as shown in
Alternatively, a further securing process may be possible by placing a thin layer, a chip securing layer 702, preferably a dielectric SiO2 of thickness 10 nm to 300 nm, on top of the etch mask 701, as shown in
Now, a carrier wafer can be temporary or permanent, and may be attached to the III-nitride layered devices 111. Imposing ultrasonic or mechanical or thermal treatments, the only support hook layer 702 can be broken, and the devices 111 can be transferred onto the carrier wafer.
This unique process is helpful not only in solving the present micro-LEDs mass transfer problem, but also helps to realize unique patterns of VCSELs and dual clad edge emitting Fabry Perot lasers, as described below.
VCSEL: n-Side Curved Mirror on an Epitaxial Layer with No Substrate Involved
After placing a secured chip layer 702, the devices 111 may be transferred onto a temporary carrier 703 either using a crystal bond, electron wax or a temporary attachment layer, as indicated in
Dual clad Fabry Perot (FP) Laser
Mass Production
One of the designs experimented with embedding a DBR-like mirror structure, for example, a growth restrict mask 102 with ELO III-nitride layers 105 as shown in
Thermal expansion coefficients of embedded DBR mirror material, mostly dielectric layers from the growth restrict mask 102, and semiconducting ELO III-nitride layers 105 differ significantly. As a result, significant stress will be developed between these layers 102, 105 when temperatures of the environment change. In general, ELO III-nitride layers 105 are fabricated in an MOCVD environment around 700° C.-1200° C. and they must be cooled down to room temperatures for fabrication of devices 111. This is the most frequent scenario when embedded DBR mirror patterns are implemented.
The built-up internal stress between the ELO III-nitride layers 105 and DBR mirror material 102 may gradually lead to cracks being generated in the layers of the device 111. This also makes for unreliable contact between the embedded DBR mirror 102 and the ELO III-nitride layers 105 laid on top of it. The cracks in the layers of the device 111 attract moisture and make the DBRs vulnerable to the environment and, in a worst case scenario, device layers 106 can be self-lifted. This will affect the reflectivity of the DBR mirrors and the longevity of the device 111. Experimentally, cracks in the ELO III-nitride layers 105 were observed when a growth restrict mask 102, comprising a dielectric layer of SiO2, was embedded by forming ELO III-nitride layers 105 on top of growth restrict mask 102, as shown in
In summary, when a DBR mirror is placed without first removing the ELO III-nitride layers 105, several reliability problems follow:
The weak bond between the ELO III-nitride layers 105 and the DBR mirror, which may have adverse effects, may also be advantageous in certain aspects:
This invention mitigates these problems by taking advantage of the weakly-bonded interface between the DBR mirror and the ELO III-nitride layers 105:
Additionally, the DBR mirror may be deposited externally after removing the ELO III-nitride layers 105 or device layers 106 from the host substrate 101. By doing so, the device layers 106 become stress-free due to their free-standing nature. Next, a DBR mirror may be deposited or placed at the interface of the ELO wing region, which makes a reliable bonding with the wing interface, thus making the desired function of the DBR realizable.
Preferably, the DBR should be placed at least 1 μm distance away L from the edge of the etched portions to avoid etch damage. It was experimentally observed that the interface of the removed ELO wing has a roughness less than 2 nm and, at most, can reach to a sub-nanometer level. Further, improvements in the reduction of the interface's roughness was proposed using a multi-layer approach or a thermally stable growth restrict mask 102 or material parameter development.
In the end, the approach of this invention is cost effective, since the device 111 is removed from the host substrate 101 and the host substrate 101 can be recycled several times.
Alternative Designs
Design 1
The above portion of this application describes one type of design, known as Design 1, as shown in
Design 2
Another type of design, known as Design 2, is shown in
In this design, the first light reflecting mirror 301 was designed at a designated portion of the wing regions of the ELO III-nitride layer 105 by defining a current confinement region 308 on the p-GaN side.
Later, a current spreading layer 309 and a contact layer, for example ITO, are deposited on the region comprising the current confinement aperture. Light reflecting DBR mirror 301 is a combination of dielectric layers with different refractive indices placed over the current confinement aperture such that the contact layer lies between the p-GaN and DBR.
At this stage, a single aperture device 111 as shown in
Later, single or double aperture bars 110 are then attached to the carrier plate 307 via a bonding layer 306. The devices 111 are then removed from the substrate 101 using an adhesive film.
A second light reflecting mirror 313 is blanket deposited at the backside of the device 111, which is n-GaN, at the side at the interface 312 between the growth restrict mask 102 and the ELO III-nitride layers 105.
Design 3
Another type of design, known as Design 3, is shown in
In this design, the first light reflecting mirror is designed at a designated portion of the wing regions of the bar 110 by defining a current confinement region 308 on the p-GaN side.
Later, a current spreading layer 309 and a contact layer, for example ITO, are deposited on the region comprising the current confinement aperture. Light reflecting DBR mirror 301, which is a combination of dielectric layers with different refractive indices, is placed over the current confinement aperture such that the contact layer lies between the p-GaN and DBR.
At this stage, a single aperture device 111 as shown in
The device 111 is attached to a carrier 307 via bonding layer 306. The devices 111 are then removed from the substrate 101 using an adhesive film. Then, a convex shape 1010 is transferred onto the n-GaN side at the interface between the growth restrict mask 102 and the ELO region, lithographically.
The second light reflecting DBR mirror 313 is deposited on the convex shape. The n-pad is blanket deposited for electrical connection.
Finally, the device 111 is transferred onto a carrier plate 307a via bonding layer 306a. Or, by selecting a carrier 307 and bonding layer 306 transparent to emitting light of the device 111, one can avoid the transfer process to a second carrier plate 307a.
Design 4
Another type of design, known as Design 4, is shown in
In this design, the first light reflecting mirror is designed at a designated portion of the wing regions of the bar 110 by defining a current confinement region 308 on the p-GaN side.
Later, a current spreading layer 309 and a contact layer, for example ITO, are deposited on the region comprising the current confinement aperture. Light reflecting DBR mirror 301, which is a combination of dielectric layers with different refractive indices, is placed over the current confinement aperture such that the contact layer lies between the p-GaN and DBR.
At this stage, a single aperture device 111 as shown in
To define the n-pad 311, the III-nitride semiconductor layers 105, 106, 109 are etched from the top down to expose the n-GaN layer. The n-pad 311 is deposited at the designated portion.
The device 111 is attached to a carrier 307 via bonding layer 307. The devices 111 are then removed from the substrate 101 using an adhesive film. Then, a convex shape is transferred onto the n-GaN side at the interface between the growth restrict mask 102 and the ELO III-nitride layer 105, lithographically.
The second light reflecting DBR mirror 313 is deposited on the convex shape.
Finally, the device 111 is transferred onto a carrier plate 307a via bonding layer 306a.
Or, by selecting a carrier 307 and bonding layer 306 transparent to emitting light of the device 111, one can avoid the transfer process to a second carrier plate 307a.
Design 5
Another type of design, known as Design 5, is shown in
This design can be fabricated on III-nitride layers grown by the methods mentioned in
In this design, a convex shape was patterned on the p-side of the device 111. Specifically, the III-nitride base epitaxial layers 106 of the device 111 terminated with a p-type layer. To fabricate a curved surface, a thick n-GaN layer 310 was re-deposited on the p-GaN layer, after defining a current confinement region 308 in the p-layer.
A convex shape is then patterned on the thicker n-GaN layer on either side of the open region conforming to the wing region of the ELO. A current spreading layer 309, for example ITO, was deposited over the convex region, and a light reflective element 313 was then deposited on the convex shape followed by a p-pad 305.
At this stage, a single aperture device 111 as shown in
The device 111 is then attached to a carrier 307 via bonding layer 306. The devices 111 are then removed from the substrate 101 using an adhesive film.
On the backside of the device 111, which is n-GaN, at the interface 312 between the growth restrict mask 102 and the ELO III-nitride layers 105, a second light reflecting mirror 313 is defined lithographically and n-pads 311 are deposited to contact the n-GaN layer.
Design 6
Another type of design, known as Design 6, is shown in
In this design, a convex shape was patterned on the p-side of the device 111. Specifically, the III-nitride base epitaxial layers 106 of the device 111 terminated with a p-type layer. To fabricate a curved surface, a thick n-GaN layer 310 was re-deposited on the p-GaN layer, after defining a current confinement region 308 in the p-layer.
A convex shape was patterned on the thicker n-GaN layer 310 on either side of the open region conforming to the wing region of the ELO III-nitride layer 105. A current spreading layer 309, for example, ITO, is deposited over the convex region, and a light reflective element 301 was then deposited on the convex shape followed by a p-pad layer 305.
In this design, the n-pad 311 and p-pad 305 are on the same side of the device 111, where the III-nitride semiconductor layers 105, 106, 109 are etched from the top down and the n-pad 311 was deposited at the designated region.
At this stage, a single aperture device 111 as shown in
The device 111 is attached to a carrier 307 via a bonding layer 306. The devices 111 are then removed from the substrate 101 using an adhesive film.
On the backside of the device 111, which is n-GaN, at the interface 312 between the growth restrict mask 102 and the ELO III-nitride layers 105, a second light reflecting mirror 313 is defined lithographically or blanked deposited to finish the device 111.
Design 7
Another type of design, known as Design 7, is shown in
In this design, the light reflecting mirror DBR 301 is placed over initially grown coalesced III-nitride semiconductor layers 105. The DBR 301 is embedded in the second stage of MOCVD growth as a result a coalescence line that appears above the newly established growth restrict mask 303. Once the DBR 301 is embedded, the III-nitride semiconductor layers 106 containing active and p-GaN layers are grown, as shown in
The design of
In
The p-pad 305 and n-pad 311 are on opposite sides of the device 111. A current confinement layer 308 is designed at the designated place on the p-GaN layer using lithography. Afterwards, a current spreading layer 309 is placed over the p-GaN layer containing the current confinement aperture. A light reflecting DBR mirror 301 is placed over the current confining aperture. The design is only used with a single aperture. The aperture on the p-side basically overlaps between two wing regions obtained during two ELO growths, and more specifically, between two coalescence lines generated from the secondary ELO growth. The p-pad 305 is defined over the light reflecting mirror 301. The device 111 is attached to a carrier 307 via bonding layer 306. The devices 111 are then removed from the substrate 101 using an adhesive film. The n-pad 311 is then deposited on the back side at the designated area in a manner that does not obstruct emitting light.
In
Pattern 1
Pattern 1 is illustrated in
For example, Pattern 1 of
Pattern 2
Pattern 2 is illustrated in
For example, Pattern 2 in
Design 8: Devices on Pattern 1
In this design, known as Design 8 with Pattern 1, epitaxial layers are grown laterally on the patterned mask from
The III-nitride epitaxial layers 105 take the concave shape 403 at the window on either side of the open region 405. Later, III-nitride base layers 106 comprising active and p-GaN layers are grown over 405. The device 111 can be singulated with a single aperture device 111 or can be integrated as whole containing two apertures as a single device 111 as desired.
The device 111 configuration is best suited for a long-cavity resonating cavity 412 between two light reflecting mirrors 408, 413. By having long light reflecting cavities, better thermal management and less tolerance to active layer placement in the cavity 412 can be achieved, and therefore more feasible manufacturability can be foreseen.
After growing the active and p-GaN layers on top of the base III-nitride semiconductor layers, a current confinement layer 406 is designed at the designated place on the p-GaN layer using lithography. Afterwards, a current spreading layer 407 is placed over the p-GaN layer containing the current confinement aperture. A light reflecting mirror 408, such as a DBR mirror, is placed over the current confining aperture. Single or double apertures are feasible with these designs. The aperture on the p-side is placed vertically above the concave shaped region. The p-pad 409 is defined over the light reflecting mirror.
The device 111 is then attached to a carrier 410 via bonding layer 411. The devices 111 are then removed from the substrate 101 using an adhesive film. After transferring the devices 111 onto a carrier, a light reflecting mirror is deposited on the convex shape region (when looking at the backside of the device 111) and then n-pads are defined.
If only a device 111 with a single aperture is needed, then separation of the double aperture device 111 along the YY′ line may be made as indicated in
If the carrier and the bonding layers are transparent to the emitted light of the aperture, then no further transfer is required; however, if an opaque carrier and/or bonding layer is chosen, then the devices 111 must be transferred to a carrier 410 using a bonding layer 411 after fabricating the n-side light reflecting mirror and n-pad.
Design 9: Devices on Pattern 2
In this design, known as Design with Pattern 2, epitaxial layers are laterally grown on a patterned mask shown in
The III-nitride epitaxial layers 105 take the designed shape (sharp or tapered) 510 at the window on either side of the open region 505. Later, III-nitride base layers 106 comprising active and p-Gan layers are grown over 105. The device 111 can be singulated as a single aperture device 111 or can be integrated as a whole containing two apertures as a single device 111 as per the demand.
The device 111 configuration is best suited for a long-cavity resonating cavity 512 between two light reflecting mirrors. By having long light reflecting cavities, better thermal management and less tolerance to active layer placement in the cavity can be achieved, therefore feasible manufacturability can be foreseen.
After growing the active and p-GaN layers on top of base III-nitride semiconductor layers, a current confinement layer 506 is designed at the designated place on the p-GaN layer using lithography. Afterwards, a current spreading layer 507 is placed over the p-GaN layer containing the current confinement aperture. A light reflecting mirror 508 is placed over the current confining aperture. Single or double apertures are feasible in these designs. The aperture on the p-side is placed vertically above the concave shaped region. The p-pad 509 is defined over the light reflecting mirror.
The device 111 is then attached to a carrier 510 via bonding layer 511. The devices 111 are then removed from the substrate 101 using an adhesive film. After transferring the devices 111 onto carrier 510, a light reflecting mirror is deposited on the designed shape 504 (when looking at the backside of the device 111) and n-pads are defined.
If only a device 111 with a single aperture is needed, then separation of the double aperture device 111 is made along YY′ line as indicated in
If the carrier and the bonding layers are transparent to the emitted light of the aperture, then no further transfer is required; however, if an opaque carrier and/or bonding layer is chosen, then the devices 111 must be transferred to a carrier 510 using a bonding layer 511 after fabricating the n-side light reflecting mirror and n-pad.
The devices 111 described above are comprised of the following III-nitride semiconductor device layers 106 laid one on top of another, in the order mentioned, grown on the ELO III-nitride layers 105 deposited on the growth restrict mask 102; an n-Al0.06GaN clad layer, an n-GaN guiding layer, an InGaN/GaN multiple quantum well (MQW) active layer, an AlGaN EBL layer, a p-GaN waveguide layer, an ITO cladding layer, an SiO2 current limiting layer (or reactive ion etching can used to limit the current to aperture), and a p-electrode.
An optical resonator is comprised of a cavity structure, wherein a cavity is formed at the top and bottom of the device 111. A dielectric DBR, also referred to as a light reflecting mirror, is comprised of multiple dielectric layers with different refractive indices. The optical resonator provides optical confinement in a vertical direction. The length between two DBRs of the optical resonator structure is on the order of 5 to 50 μm and typically is 10 μm. ITO used as current spreading layer.
Conventional methods, such as photolithography and dry etching or reactive ion etching, can be used to fabricate the aperture structure. The current confinement region depth (from the top surface to the bottom surface) is in the p-GaN waveguide layer. The region of interest for current blocking is pre-determined before etching is performed, based on simulation or previous experimental data.
In one embodiment, the p-electrode 509 may be comprised of one or more of the following materials: Pd, Ni, Ti, Pt, Mo, W. Ag, Au, etc. For example, the p-electrode 509 may comprise Pd—Ni—Au (with thicknesses of 3-30-300 nm). These materials may be deposited by electron beam evaporation, sputter, thermal heat evaporation, etc. In addition, the p-electrode 509 is typically deposited on the ITO current spreading layer 507.
Process Steps
Block 2501 represents the step of providing a host substrate 101. In one embodiment, the substrate 101 is a semiconducting substrate, independent of crystal orientations, such as III-nitride based substrate 101, for example, a GaN-based substrate 101, or a hetero-substrate 101, such as a sapphire substrate 101. This step may also include an optional step of depositing a template layer on or above the substrate 101, wherein the template layer may comprise a buffer layer or an intermediate layer, such as a GaN underlayer.
Block 2502 represents the step of depositing a growth restrict mask 102 on or above the substrate 101, i.e., on the substrate 101 itself or on the template layer. The growth restrict mask 102 is patterned to include a plurality of striped opening areas 103. The growth restrict mask 102 may comprises a multi-layer structure.
Block 2503 represents the step of forming one or more III-nitride layers 105 on or above the growth restrict mask 102 using epitaxial lateral overgrowth (ELO). This step may or may not include stopping the growth of the ELO III-nitride layers 105 before adjacent ones of the ELO III-nitride layers 105 coalesce to each other.
Block 2504 represents the step of growing one or more III-nitride device layers 106 on or above the ELO III-nitride layers 105, thereby fabricating a bar 110 forming one or more devices 111 on the substrate 101. Additional device 111 fabrication may take place before and/or after the bar 110 is removed from the substrate 101.
Block 2505 represents the step of fabricating the bars 110 into devices 111.
Block 2506 represents the steps of removing the bar 110 comprised of the ELO III-nitride layers 105 and the III-nitride device layers 106 from the substrate 101. The removed ELO III-nitride layers 105 contain at least a partially processed portion of the VCSEL device 111. A thickness of the removed ELO III-nitride layers 105 are controlled epitaxially to realize a functional version of the VCSEL device 111. At least one of the removed ELO III-nitride layers 105 is used to extract heat from the VCSEL device 111 during device 111 operation.
Block 2507 represents the steps of placing one or more dielectric distributed Bragg reflector (DBR) mirrors for a resonant cavity of the VCSEL device 111 on a backside of the removed ELO III-nitride layers 105, wherein the backside of the removed ELO III-nitride layers 105 has a non-planar shape and the dielectric DBR mirrors are placed on the backside of the removed ELO III-nitride layers 105 at a wing region of the removed ELO III-nitride layers 105. The host substrate is pre-patterned to realize the non-planar shape, and the non-planar shape comprises a curvature, the backside of the removed ELO III-nitride layers 105 has a finite radius of the curvature, and a center of the curvature is on a side of the host substrate's 101 surface. At least one of the dielectric DBR mirrors is sandwiched between the removed ELO III-nitride layers 105. The dielectric DBR mirrors are placed on the backside of the removed ELO III-nitride layers 105 at a distance of at least 1 μm away from a coalesced region and open area 103 edge. The resonant cavity of the VCSEL device 111 formed by the DBR mirrors does not contain a substantial portion of the host substrate 101.
Block 2508 represents the optional step of dividing the bar 110 into one or more devices 111 at dividing support regions formed along the bar 110.
Block 2509 represents the step of mounting the devices 111 in a module, wherein the devices 111 are mounted to a stem and stage of the module.
Block 2510 represents the resulting product of the method, namely, one or more III-nitride based semiconductor devices 111, such as VCSEL devices 111, fabricated according to this method, as well as a substrate 101 that has been removed from the devices 111 and is available for recycling and reuse.
The devices 111 may comprise one or more ELO III-nitride layers 105 grown on or above a growth restrict mask 102 on a substrate 101, wherein the growth of the ELO III-nitride layers 105 is stopped before adjacent ones of the ELO III-nitride layers 105 coalesce to each other. The devices 111 may further comprise one or more additional III-nitride device layers 106 grown on or above the ELO III-nitride layers 105 and the substrate 101.
Advantages and Benefits
The present invention provides a number of advantages and benefits:
This concludes the description of the preferred embodiment of the present invention. The foregoing description of one or more embodiments of the invention has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be limited not by this detailed description, but rather by the claims appended hereto.
This application claims the benefit under 35 U.S.C. Section 119(e) of the following co-pending and commonly-assigned application: U.S. Provisional Application Ser. No. 62/924,756, filed on Oct. 23, 2019, by Srinivas Gandrothula, Takeshi Kamikawa and Masahiro Araki, entitled “METHOD OF FABRICATING A RESONANT CAVITY AND DISTRIBUTED BRAGG REFLECTOR MIRRORS FOR A VERTICAL CAVITY SURFACE EMITTING LASER ON A WING OF AN EPITAXIAL LATERAL OVERGROWTH REGION,” attorneys' docket number G&C 30794.0745USP1 (UC 2020-071-1);which application is incorporated by reference herein. This application is related to the following co-pending and commonly-assigned applications: U.S. Utility patent application Ser. No. 16/608,071, filed on Oct. 24, 2019, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE,” attorney's docket no. 30794.0653USWO (UC 2017-621-2), which application claims the benefit under 35 U.S.C. Section 365(c) of co-pending and commonly-assigned PCT International Patent Application Serial No. PCT/US18/31393, filed on May 7, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE,” attorney's docket no. 30794.0653WOU1 (UC 2017-621-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application Ser. No. 62/502,205, filed on May 5, 2017, by Takeshi Kamikawa, Srinivas Gandrothula, Hongjian Li and Daniel A. Cohen, entitled “METHOD OF REMOVING A SUBSTRATE,” attorney's docket no. 30794.0653USP1 (UC 2017-621-1);U.S. Utility patent application Ser. No. 16/642,298, filed on Feb. 26, 2020, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” attorney's docket no. 30794.0659USWO (UC 2018-086-2), which application claims the benefit under 35 U.S.C. Section 365(c) of co-pending and commonly-assigned PCT International Patent Application Serial No. PCT/US18/51375, filed on Sep. 17, 2018, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE.” attorney's docket no. 30794.0659WOU1 (UC 2018-086-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application Ser. No. 62/559,378, filed on Sep. 15, 2017, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF REMOVING A SUBSTRATE WITH A CLEAVING TECHNIQUE,” attorney's docket no. 30794.0659USP1 (UC 2018-086-1);U.S. Utility patent application Ser. No. 16/978,493, filed on Sep. 4, 2020, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH,” attorney's docket no. 30794.0680USWO (UC 2018-427-2), which application claims the benefit under 35 U.S.C. Section 365(c) of co-pending and commonly-assigned PCT International Patent Application Serial No. PCT/US19/25187, filed on Apr. 1, 2019, by Takeshi Kamikawa, Srinivas Gandrothula and Hongjian Li, entitled “METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH,” attorney's docket no. 30794.0680WOU1 (UC 2018-427-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Patent Application Ser. No. 62/650,487, filed on Mar. 30, 2018, by Takeshi Kamikawa, Srinivas Gandrothula, and Hongjian Li, entitled “METHOD OF FABRICATING NON-POLAR AND SEMI-POLAR DEVICES USING EPITAXIAL LATERAL OVERGROWTH,” attorney docket number G&C 30794.0680USP1 (UC 2018427-1);U.S. Utility patent application Ser. No. 17/048,383, filed on Oct. 16, 2020, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES.” attorney's docket no. 30794.0681USWO (UC 2018-605-2), which application claims the benefit under 35 U.S.C. Section 365(c) of co-pending and commonly-assigned PCT International Patent Application Serial No. PCT/US19/32936, filed on May 17, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES,” attorney's docket no. 30794.0681WOU1 (UC 2018-605-2), which application claims the benefit under 35 U.S.C. Section 119(c) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/672,913, filed on May 17, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR DIVIDING A BAR OF ONE OR MORE DEVICES,” attorneys' docket number G&C 30794.0681USP1 (UC 2018-605-1);PCT International Patent Application Serial No. PCT/US19/34868, filed on May 30, 2019, by Srinivas Gandrothula and Takeshi Kamikawa, entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE.” attorneys' docket number G&C 30794.0682WOU1 (UC 2018-614-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/677,833, filed on May 30, 2018, by Srinivas Gandrothula and Takeshi Kamikawa, entitled “METHOD OF REMOVING SEMICONDUCTING LAYERS FROM A SEMICONDUCTING SUBSTRATE,” attorneys' docket number G&C 30794.0682USP1 (UC 2018-614-1);PCT International Patent Application Serial No. PCT/US19/59086, filed on Oct. 31, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH,” attorneys' docket number G&C 30794.0693WOU1 (UC 2019-166-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/753,225, filed on Oct. 31, 2018, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD OF OBTAINING A SMOOTH SURFACE WITH EPITAXIAL LATERAL OVERGROWTH,” attorneys' docket number G&C 30794.0693USP1 (UC 2019-166-1);PCT International Patent Application Serial No. PCT/US20/13934, filed on Jan. 16, 2020, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH,” attorneys' docket number G&C 30794.0713WOU1 (UC 2019-398-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/793,253, filed on Jan. 16, 2019, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled “METHOD FOR REMOVAL OF DEVICES USING A TRENCH,” attorneys' docket number G&C 30794.0713USP1 (UC 2019-398-1);PCT International Patent Application Serial No. PCT/US20/20647, filed on Mar. 2, 2020, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER,” attorneys' docket number G&C 30794.0720WOU1 (UC 2019-409-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/812,453, filed on Mar. 1, 2019, by Takeshi Kamikawa and Srinivas Gandrothula, entitled “METHOD FOR FLATTENING A SURFACE ON AN EPITAXIAL LATERAL GROWTH LAYER,” attorneys' docket number G&C 30794.0720USP1 (UC 2019-409-1);PCT International Patent Application Serial No. PCT/US20/22735, filed on Mar. 13, 2020, by Takeshi Kamikawa, Masahiro Araki and Srinivas Gandrothula, entitled “SUBSTRATE FOR REMOVAL OF DEVICES USING VOID PORTIONS,” attorneys' docket number G&C 30794.0722WOU1 (UC 2019-412-2), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/817,757, filed on Mar. 13, 2019, by Takeshi Kamikawa, Masahiro Araki and Srinivas Gandrothula, entitled “SUBSTRATE FOR REMOVAL OF DEVICES USING VOID PORTIONS,” attorneys' docket number G&C 30794.0722USP1 (UC 2019-412-1); andPCT International Patent Application Serial No. PCT/US20/22430, filed on Mar. 12, 2020, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled “METHOD FOR REMOVING A BAR OF ONE OR MORE DEVICES USING SUPPORTING PLATES,” attorneys' docket number G&C 30794.0724WOU1 (UC 2019-416-1), which application claims the benefit under 35 U.S.C. Section 119(e) of co-pending and commonly-assigned U.S. Provisional Application Ser. No. 62/817,216, filed on Mar. 12, 2019, by Takeshi Kamikawa, Srinivas Gandrothula and Masahiro Araki, entitled “METHOD FOR REMOVING A BAR OF ONE OR MORE DEVICES USING SUPPORTING PLATES,” attorneys' docket number G&C 30794.0724USP1 (UC 2019-416-1);all of which applications are incorporated by reference herein.
Filing Document | Filing Date | Country | Kind |
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PCT/US20/57026 | 10/23/2020 | WO |
Number | Date | Country | |
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62924756 | Oct 2019 | US |