The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating metal-insulator-metal (MIM) capacitors.
Circular or angular spiral metal-insulator-metal (MIM) capacitors are useful semiconductor devices.
U.S. Pat. No. 6,309,922 B1 to Liu et al. describes a spiral inductor process.
U.S. Pat. No. 6,274,502 B1 to Ohkuni describes a circular inductor process.
U.S. Pat. No. 6,258,652 B1 to Stacey describes a spiral inductor process having air gaps.
U.S. Pat. No. 6,054,329 to Burghartz et al. describes another spiral inductor process.
Accordingly, it is an object of the present invention to provide improved methods of forming a circular or angular spiral metal-insulator-metal (MIM) capacitors.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, substrate having a lower low-k dielectric layer formed thereover is provided with the lower low-k dielectric layer having a dielectric constant of less than about 3.0. Metal vertical electrode plates are formed within the lower low-k dielectric layer so that the adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween. The lower low-k dielectric layer portions between the adjacent metal vertical electrode plates are replaced with high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.
The features and advantages of the present invention will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which like reference numerals designate similar or corresponding elements, regions and portions and in which:
FIGS. 3 to 9 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention with
For the purposes of this invention, a low-k dielectric material has a dielectric constant of less than about 3.0 and a high-k dielectric material has a dielectric constant of preferably greater than about 3.0 and more preferably from about 7.0 to 50.0.
Regardless of whether an angular spiral MIM capacitor 10′ or a circular MIM capacitor 10″ is to be formed, the following description of the method of the present invention applies to the fabrication of each MIM capacitor 10′, 10″. For ease of understanding, the corresponding structures of angular spiral MIM capacitor 10′ and circular MIM capacitor 10″ will be illustrated without a prime suffix. That is, e.g., angular spiral MIM capacitor 10′ and circular MIM capacitor 10″ will both be annotated as MIM capacitor 10.
FIGS. 3 to 9 schematically illustrate in cross-sectional representation a preferred embodiment of the present invention with
It is noted that while six adjacent portions 16′, 18′, 20′, 22′, 24′, 26′ for a spiral MIM capacitor 10′ and six adjacent portions 16″, 18″, 20″, 22″, 24″, 26″ for a circular MIM capacitor 10″ are shown being formed in FIGS. 3 to 9, one skilled in the art recognizes that less or more such respective adjacent portions may be formed depending upon the final spiral MIM capacitor 10′ or circular MIM capacitor 10″ desired to be fabricated.
Initial Structure—
Structure 40 is understood to possibly include a semiconductor wafer or substrate, active and passive devices formed within the wafer, conductive layers and dielectric layers (e.g., inter-poly oxide (IPO), intermetal dielectric (IMD), etc.) formed over the wafer surface. The term “semiconductor structure” is meant to include devices formed within a semiconductor wafer and the layers overlying the wafer.
Low-k dielectric material layer 30 is preferably comprised of TEOS, FTEOS, Coral™, Black Diamond™ or an organic material and is more preferably comprised of an organic material.
A first patterned mask layer 42 is formed over the low-k dielectric material layer 30 to define the capacitor 10 vertical electrode plates 16, 18, 20, 22, 24, 26.
Formation of Vertical Electrode Plate Openings 17, 19, 21, 23, 25, 27—
As shown in
Formation of Metal Vertical Electrode Plates 16, 18, 20, 22, 24, 26 And Metal Trench Structure 28—
As shown in
Trenches 17, 19, 21, 23, 25, 27 and proximate trench 29 are preferably lined with respective metal barrier layers 50, 52, 54, 56, 58, 60, 62 and are filled with respective planarized metal vertical electrode plate structures 16, 18, 20, 22, 24, 26 and metal trench structure 28.
Metal vertical electrode plate structures 16, 18, 20, 22, 24, 26 and proximate metal structure 28 are preferably comprised of copper (Cu) or tungsten (W) and are more preferably copper (Cu). Metal barrier layers 50, 52, 54, 56, 58, 60, 62 are preferably comprised of Ta or TaN and are more preferably Ta/TaN.
A second patterned mask layer 70 is then formed over patterned low-k dielectric material layer 30 to leave the portions of patterned low-k dielectric material layer 30 between the metal vertical electrode plate structures 16, 18, 20, 22, 24, 26 exposed as shown in
Removal of the Exposed Patterned Low-k Dielectric Material Layer 30—
As shown in
Formation of High-k Dielectric Material Portions 9092, 9496, 98—
As shown in
Openings/trenches 72, 74, 76, 78, 80 between the metal vertical electrode plate structures 16, 18, 20, 22, 24, 26 are filled with a high-k dielectric material to form respective high-k dielectric material portions 90, 92, 94, 96, 98 between the metal vertical electrode plate structures 16, 18, 20, 22, 24, 26. The high-k dielectric material portions 90, 92, 94, 96, 98 are preferably comprised of SiN, Tax,Oy, Hfx,Oy, Tix,Oy, Al2O3, TaxAlyOz, Tix,AlyOz, SiO2, Tax,NyOz, Tix,NyOz or other non-conductive oxidized refractory metals and is more preferably a low leakage and high breakdown material.
The high-k dielectric material portions 90, 92, 94, 96, 98 are comprised of a material having a dielectric constant of preferably greater than about 3.0 and more preferably from about 7.0 to 50.0.
Formation of Optional Etch Stop Layer 100—
As shown in
Formation of Upper Low-k Dielectric Material Layer 102—
Then, as shown in
A third patterned mask layer 104 is then formed over the upper low-k layer 102 with respective openings 105, 107, 109, 111, 113, 115 positioned over at least a portion of the respective metal vertical electrode plate structures 16, 18, 20, 22, 24, 26 and exposing respective portions of the upper low-k layer 102. Third patterned mask layer 104 may also include an opening or openings 121 positioned over at least a portion of the metal trench structure 28 adjacent the MIM capacitor 10 and exposing respective portion(s) of the upper low-k layer 102.
Formation of Via Openings 125, 127, 129, 131, 133, 135, 141—
As shown in
Formation of Via Structures 146148150152154, 156 And Metal Via Structure 162—
Via openings 125, 127, 129, 131, 133, 135, 141 may then be lined with respective via barrier layers (not shown) and then filled with respective via structures 146, 148, 150, 152, 154, 156 and metal via structure 162.
The via barrier layers are preferably comprised of Ta or TaN.
The via structures 146, 148, 150, 152, 154, 156 and metal via structure 162 are preferably comprised of copper (Cu) or tungsten (W) and are more preferably copper (Cu).
Advantages of the Invention
The advantages of one or more embodiments of the present invention include:
While particular embodiments of the present invention have been illustrated and described, it is not intended to limit the invention, except as defined by the following claims.