Claims
- 1. A method of fabricating a thin film SOI CMOS device comprising the steps of
- providing an insulating substrate,
- depositing a first doped semiconductor layer upon said substrate and patterning it to form simultaneously the source and drain elements of one transistor and the gate element of its complementary transistor,
- depositing a tri-layer stack over said patterned first layer, said stack comprising a pair of intrinsic or lightly doped semiconductor layers separated by a dielectric layer,
- depositing a second doped semiconductor layer upon said tri-layer stack and patterning it to form simultaneously the gate source and drain element of said one transistor and the source and drain elements of said complementary transistor, and
- isolating said transistors into islands by removing any portion of said layers extending between said transistors.
- 2. The method of fabricating a thin film SOI CMOS device as defined in claim 1 wherein said step of patterning said second doped semiconductor layer includes the step of illuminating through said substrate so that said source, drain and gate elements in said second doped semiconductor layer are aligned with said source, drain and gate elements of said first doped semiconductor layer.
Parent Case Info
This is a division of application Ser. No. 07/268,832, filed Nov. 7, 1988, U.S. Pat. No. 4,951,113.
US Referenced Citations (5)
Foreign Referenced Citations (1)
Number |
Date |
Country |
0075876 |
Jul 1978 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Silicon-on-Sapphire Complementary MOS Memory Cells; Allison et al., IEEE; Dec. 67. |
Divisions (1)
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Number |
Date |
Country |
Parent |
268832 |
Nov 1988 |
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