Claims
- 1. A method of forming an antifuse comprising the steps of:
- (a) forming a first conductive layer on a substrate;
- (b) forming a first oxide layer on said first conductive layer;
- (c) forming a via in said first oxide layer which extends to said first conductive layer, wherein said via includes a lower portion forming a profile perpendicular to said first conductive layer, and an upper portion forming a concave profile;
- (d) forming an antifuse layer on said first conductive layer, wherein the top surface of said antifuse layer follows the contours of said lower and upper portions of said via; and
- (e) forming a second conductive layer on said antifuse layer.
- 2. The method of claim 1 wherein said antifuse layer forms a substantially orthogonal angle with each of said first conductive layer and said second conductive layer.
- 3. The method of claim 1 wherein step (d) includes forming an amorphous silicon layer.
- 4. The method of claim 3 wherein said amorphous silicon layer is formed to a thickness between 350.ANG. and 550.ANG..
- 5. The method of claim 3 wherein said amorphous silicon layer is formed to a thickness of approximately 450.ANG..
- 6. The method of claim 3 wherein step (d) includes forming a second oxide layer on the bottom of said via between said first conductive layer and said amorphous silicon layer.
- 7. The method of claim 6 wherein said second oxide layer is formed from said first conductive layer.
- 8. The method of claim 6 wherein said second oxide layer is formed to a thickness between 35.ANG. and 70.ANG..
- 9. The method of claim 7 wherein said second oxide layer includes titanium oxide.
- 10. The method of claim 7 wherein said second oxide layer includes tungsten oxide.
- 11. The method of claim 7 wherein said second oxide layer includes a combination of titanium oxide and tungsten oxide.
- 12. The method of claim 6 wherein step (d) includes forming a third oxide layer between said amorphous silicon layer and said second conductive layer.
- 13. The method of claim 12 wherein said third oxide layer includes a silicon dioxide layer.
- 14. The method of claim 12 wherein said third oxide layer is formed to a thickness between 10.ANG. and 30.ANG..
- 15. The method of claim 12 wherein said third oxide layer completely insulates said amorphous silicon layer from said second conductive layer.
- 16. The method of claim 1 wherein said first conductive layer forms a lower conductive terminal of said antifuse.
- 17. The method of claim 1 wherein said first conductive layer includes a conductive metal.
- 18. The method of claim 17 wherein said conductive metal includes aluminum.
- 19. The method of claim 17 wherein said conductive metal includes an aluminum-silicon alloy.
- 20. The method of claim 17 wherein said conductive metal includes an aluminum-silicon-copper alloy.
- 21. The method of claim 17 wherein said conductive metal includes titanium.
- 22. The method of claim 17 wherein said conductive metal includes titanium nitride.
- 23. The method of claim 17 wherein said conductive metal includes titanium tungsten.
- 24. The method of claim 1 wherein said second conductive layer forms an upper conductive terminal of said antifuse.
CROSS REFERENCE TO RELATED APPLICATION
This application is a division of application Ser. No. 08/132,071, filed Oct. 4, 1993 now U.S. Pat. No. 5,475,253, which is a continuation-in-part of U.S. patent application Ser. No. 07/933,428, entitled "Antifuse Structure and Method for Forming", filed Aug. 21, 1992.
US Referenced Citations (5)
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Kueing-Long Chen, et al., "A Sublithographic Antifuse Structure for Field-Programmable Gate Array Applications", IEEE Electron Device Letters, 13 (1992) Jan., pp. 53-55. |
Cook, Brian; Keller, Steve; "Amorphous Silicon Antifuse Technology for Bipolar Proms", IEEE, 1986 Bipolar Circuits and Technology Meeting, pp. 99-100. |
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Divisions (1)
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Parent |
132071 |
Oct 1993 |
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Continuation in Parts (1)
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933428 |
Aug 1992 |
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